USRE49631E1 - Semiconductor device and production method thereof - Google Patents

Semiconductor device and production method thereof Download PDF

Info

Publication number
USRE49631E1
USRE49631E1 US17/021,673 US202017021673A USRE49631E US RE49631 E1 USRE49631 E1 US RE49631E1 US 202017021673 A US202017021673 A US 202017021673A US RE49631 E USRE49631 E US RE49631E
Authority
US
United States
Prior art keywords
semiconductor device
layer
set forth
semiconductor chip
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US17/021,673
Inventor
Osamu Yamagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to US17/021,673 priority Critical patent/USRE49631E1/en
Application granted granted Critical
Publication of USRE49631E1 publication Critical patent/USRE49631E1/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/92—Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Definitions

  • the present invention relates to a semiconductor device a the production method therefor, and, particularly to a semiconductor device of a type called a system-in-package (SiP), which is packaged at a wafer level, and a production method therefor.
  • SiP system-in-package
  • the package type of a semiconductor device has shifted from the lead-inserted type, such as a dual inline package (DIP), to the surface-mounted type.
  • the flip-chip mounting method for providing a bump (protruding electrode) made of solder or gold on a pad electrode of a semiconductor chip and connecting to the wiring board via the bump with the surface facing downward has been developed.
  • an insulating layer is formed to be a film thickness of 1 ⁇ m or less on a surface of a semiconductor wafer formed with a transistor and other semiconductor elements by the chemical vapor deposition (CVD) method, the sputtering method, the thermal oxidization method or the spin coating method, etc., and dicing processing is performed to obtain a small piece of semiconductor device.
  • CVD chemical vapor deposition
  • sputtering method the thermal oxidization method or the spin coating method, etc.
  • dicing processing is performed to obtain a small piece of semiconductor device.
  • SiP system-in-package
  • a method of forming as the insulating layer of the rewiring layers an insulating layer made of a polyimide resin and an epoxy resin, etc., to be a film thickness of 10 ⁇ m or less by the spin coating method on the surface of the semiconductor wafer formed with a transistor and other semiconductor element and performing dicing processing to obtain a small piece has been widely used.
  • the insulating layer of the rewiring layers is made to be a multilayer of, for example, three layers or more, when assuming that a film thickness of one layer is 10 ⁇ m at minimum, the thickness becomes 30 ⁇ m by putting the three layers together, so that it becomes relatively impossible to ignore the film thickness of the insulating layer of the rewiring layer in the case where, for example, a silicon substrate is made to be as thin as 50 ⁇ m or less.
  • the film thickness of the whole insulating layer of the rewiring layers has to be 50 ⁇ m or more, and an effect given to warps of the semiconductor wafer becomes large.
  • An object of the present invention is to prevent the arising of warps of a semiconductor wafer when an insulating layer in rewiring layers becomes thick in a SiP type semiconductor device, which may cause an adsorption error and a conveyance error in a production facility, breakage, a decline of the yield and a decline of secondary connection reliability due to residual stress.
  • a semiconductor device comprising a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof which are taken out from the electronic circuit, an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip, and a wiring layer formed to be electrically connected to the electrodes and buried in the insulating layer, wherein the plurality of resin layers is formed so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.
  • an insulating layer is configured by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wherein a wiring layer is buried to be electrically connected to electrodes.
  • the plurality of resin layers has the configuration wherein the layers' formation areas become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.
  • a production method of a semiconductor device including the steps of forming integrated electronic circuits corresponding to a plurality of semiconductor chips on a semiconductor wafer, and forming electrodes on a surface of the semiconductor wafer by taking them out from the electronic circuits, forming a pattern of a first resin layer on the surface of the semiconductor wafer except for a scribe line to be a dicing region, forming on the first resin layer a pattern of a first wiring layer electrically connected to the electrodes, forming a pattern of a second resin layer to cover the first resin layer and the first wiring layer except for the scribe line, and dicing the semiconductor wafer on the scribe line, wherein in the step of forming the second resin layer, the second resin layer is formed on a smaller area than that of the first resin layer, so that a side surface and an upper surface of each of the first resin layer and the second resin layer form a stepwise shape.
  • electronic circuits corresponding to a plurality of semiconductor chips are formed to be integrated on the semiconductor wafer first, and electrodes are formed on its surface by being taken out from the electronic circuits.
  • a pattern of a first resin layer is formed on a surface of the semiconductor wafer except for a scribe line to be a dicing region, a pattern of a first wiring layer is formed on the first resin layer and electrically connected to the electrodes, and a pattern of a second resin layer is formed to cover the first resin layer and the first wiring layer except for the scribe line.
  • the second resin layer When forming the second resin layer, it is formed to have a smaller area than that of the first resin layer, so that a side surface and an upper surface of each of the first resin layer and the second resin layer form a stepwise shape.
  • FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 A to FIG. 2 C are views of production steps of the semiconductor device according to the embodiment of the present invention.
  • FIG. 3 A to FIG. 3 C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention.
  • FIG. 4 A to FIG. 4 C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention.
  • FIG. 5 A to FIG. 5 C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention.
  • FIG. 6 A to FIG. 6 C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention.
  • FIG. 1 is a schematic sectional view of a semiconductor device according to the present embodiment.
  • a semiconductor chip (semiconductor substrate) 10 a formed with an electronic circuit including a transistor and other semiconductor elements electrodes (not shown) taken out from the electronic circuit are formed.
  • an insulating layer configured by stacking a first resin layer 20 , a second resin layer 21 , a third resin layer 22 and a fourth resin layer 23 is formed.
  • Wiring layers composed of first wiring layers ( 30 , 31 ), second wiring layers ( 32 , 33 ) and third wiring layers ( 34 , 35 ) are formed by being buried in the insulating layer composed of the above stacked resin layers.
  • the wiring layers are formed to be electrically connected to the electrodes taken out from the electronic circuit of the semiconductor chip 10 a in a not shown part.
  • formation areas of the first resin layer 20 , the second resin layer 21 , the third resin layer 22 and the fourth resin layer 23 become gradually smaller from an area of an upper surface of the semiconductor chip 10 a as they get farther from the semiconductor chip 10 a, so that a side surface and an upper surface of each of the first resin layer 20 , the second resin layer 21 , the third resin layer 22 and the fourth resin layer 23 and an upper surface of the semiconductor chip 10 a form a stepwise shape.
  • Each of the widths (D 1 , D 2 and D 3 ) of exposed upper surfaces of the respective resin layers ( 20 , 21 and 22 ) on the stepwise formed portion is preferably 5 ⁇ m or more, and is, for example, 5 ⁇ m.
  • a width D 0 of an exposed part of the semiconductor chip 10 a being out of the first resin layer 20 depends on the width of the scribe line on the semiconductor wafer before dicing, and is, for example, 10 ⁇ m or so.
  • an insulating layer configured by stacking a plurality of resin layers on a semiconductor chip
  • it is configured so that formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, and consequently, a stress imposed on the semiconductor wafer is small even in a stage before dicing and warps are suppressed.
  • electronic circuits including a transistor and other semiconductor elements and corresponding to a plurality of semiconductor chips are formed to be integrated on the semiconductor wafer 10 . Furthermore, electrodes (not shown) are formed on the surface of the semiconductor wafer 10 so as to be taken out from the electronic circuits.
  • a pattern of the first resin layer 20 is formed, for example, to be a film thickness of 10 ⁇ m or so on the semiconductor wafer 10 .
  • the first resin layer is formed by using a negative photosensitive resin material, such as a polyimide resin, an epoxy resin and an acrylic resin, by the spin coating method, the printing method or the CVD method, etc., and subjected to exposure by using a photomask, so that regions other than the scribe line are irradiated.
  • a photosensitive polyimide resin the exposure is performed by broadband exposure to covering lights of a g-line, an h-line and an i-line with energy of 300 mJ/cm 2 .
  • an epoxy resin exposure is performed with energy of 2000 mJ/cm 2 .
  • development processing is performed by using a 2.38% trimethylammonium hydroxide solution as a developing solution. Due to photosensitivity of the used resin, the scribe line SL opens in the development stage.
  • a pattern shape varies by the exposure condition and the actual condition, but it becomes a tapered opening shape.
  • the scribe line SL is formed to be a width of, for example, 78 ⁇ m.
  • a seed layer 30 is formed all over, for example, by the sputtering method.
  • a seed layer for plating copper for example, a film of Ti/Cu is formed to be a film thickness of 160 nm/600 nm.
  • a negative or positive resist film is formed on the seed layer 30 , for example, by the spin coating; pattern exposure is performed by using a photomask, so that the pattern remains on regions other than formation regions of the first wiring layer in a predetermined wiring circuit pattern; and development processing is performed to form a pattern of the first resist film R 1 .
  • the regions not formed with the first resist film R 1 become formation regions of the first wiring layer. Since the first wiring layer is not formed on the scribe line SL, it is covered with the first resist film R 1 .
  • a copper film is formed on regions other than the formation regions of the first resist film R 1 by performing electroforming plating processing using the seed layer 30 as one electrode, and a copper plating layer 31 is formed in a predetermined wiring circuit pattern.
  • the first resist film R 1 is peeled by solvent processing, etc. to make the copper plating layer 31 exposed.
  • Wet etching, etc. is performed by using the copper plating layer 31 as shown in FIG. 4 A , and the seed layer 30 between the copper plating layers 31 is removed in order to insulate.
  • the first wiring layer composed of the seed layer 30 and the copper plating layer 31 is formed. While the first wiring layer is not shown in FIG. 4 A , it is formed so as to be connected to electrodes (not shown) provided on the surface of the semiconductor wafer 10 .
  • a pattern of the second resin layer 21 is formed to be a film thickness of, for example, 10 ⁇ m or so on the first wiring layer ( 30 , 31 ).
  • the second resin layer 21 can be formed by the same means and material as those of the first resin layer 20 .
  • the layer is formed to have a smaller area than that of the first resin layer 20 , so that a side surface and an upper surface of the first resin layer 20 and the second resin layer 21 form a stepwise shape.
  • a width D 1 of the exposed upper surface of the first resin layer 20 that is out of the second resin layer 21 is preferably 5 ⁇ m or more and is assumed to be, for example, 5 ⁇ m.
  • the via hole VH connected to the first wiring layer ( 30 , 31 ) can be formed in the same way.
  • a seed layer 32 is formed all over, for example, by the sputtering method in the same way as the above.
  • the width D 1 of the exposed upper surface of the first resin layer 20 that is out of the second resin layer 21 is 5 ⁇ m or more, coverage of the seed layer 32 covering the scribe line becomes preferable and step disconnection on the seed layer 32 can be prevented.
  • a resist film is formed on the seed layer 32 , for example, by spin coating and a pattern of a second resist film R 2 for protecting the scribe line SL and regions other than formation regions of the second wiring layer is formed.
  • the width D 1 of the exposed upper surface of the first resin layer 20 that is out of the second resin layer 21 is 5 ⁇ m or more, coverage of the resist film R 2 covering the scribe line becomes preferable and step disconnection on the resist film R 2 can be prevented.
  • electroforming plating processing is performed by using the seed layer 32 as one electrode to form a copper film on regions other than the formation regions of the second resist film R 2 , and a copper plating layer 33 is formed in a predetermined wiring circuit pattern.
  • the second resist film R 2 is peeled, and the seed layer 32 between the respective copper plating layer 33 is removed by etching, as shown in FIG. 6 A , to form a second wiring layer composed of the seed layer 32 and the copper plating layer 33 .
  • the second wiring layer is formed to be electrically connected to the first wiring layer via the via hole VH.
  • the third resin layer 22 and the fourth resin layer 23 are formed in the same way as the first resin layer 20 and the second resin layer 21 , and the third wiring layer ( 34 , 35 ) is formed in the same way as the first wiring layer ( 30 , 31 ) and the second wiring layer ( 32 , 33 ), respectively.
  • the third wiring layer ( 34 , 35 ) is formed to be connected to the second wiring layer ( 32 , 33 ) in the via hole.
  • the layer is formed to have a smaller area than that of the second resin layer 21 , so that a side surface and an upper surface of each of the second resin layer 21 and the third resin layer 22 form a stepwise shape.
  • the layer is formed to have a smaller area than that of the third resin layer 22 , and a width (D 2 , D 3 ) of an exposed upper surface of a lower resin layer that is out of its upper resin layer is 5 ⁇ m or more, for example 5 ⁇ m, so that a side surface and an upper surface of each of the third resin layer 22 and the fourth resin layer 23 form a stepwise shape.
  • the first to fourth resin layers ( 20 , 21 , 22 and 23 ) are not formed on the scribe line SL on the semiconductor wafer 10 , and the upper surface of the semiconductor wafer 10 is exposed.
  • warps of the semiconductor wafer (a distance of one end portion floating from a plane when pressing the other end of the wafer on the plane) could be reduced by 200 ⁇ m by applying the present embodiment.
  • resin layers on the scribe line are removed when stacking the resin layers at a wafer level, and furthermore, a side surface and an upper surface of each of the resin layers are formed to be a stepwise shape, so that warps of the semiconductor wafer can be prevented even without using a resin layer material having special properties.
  • the film thickness of the resin layers stacked on the surface other than the scribe line causes warps
  • the film thickness of the stacked resin layers can be made thicker compared with that in the configuration in which the scribe line is not removed. Namely, when assuming that the film thickness per one layer is not changed, the number of resin layers to be stacked can be increased.
  • warps of the wafer are reduced only by making the scribe line wide.
  • the present invention is not limited to the above explanation.
  • an electronic element and/or a semiconductor chip may be formed by being buried so as to be electrically connected to a lower wiring layer.
  • the stacked body may be two-layered, three-layered, five-layered or more.
  • a buffer layer having an intermediate linear expansion coefficient of both may be provided in accordance with need.
  • the buffer layer is, for example, composed of an epoxy resin layer, etc. filled with filler.
  • the layer is configured so that formation areas of the plurality of resin layers become gradually smaller from an area of the upper surface of the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, so that a stress imposed on the semiconductor wafer is small even in a stage before dicing and warps are suppressed.
  • the layers are formed so that their areas become gradually smaller from an area of an upper surface of the semiconductor chip, and a side surface and an upper surface of each of the first resin layer and the second resin layer form a stepwise shape, and consequently, a stress imposed on the semiconductor wafer is small even in a stage before dicing and warps can be suppressed in producing a semiconductor device.
  • the semiconductor device of the present invention can be applied to a system-in-package-type semiconductor device.
  • the production method of the semiconductor device of the present invention can also be applied for producing a system-in-package-type semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.

Description

CROSS REFERENCE TO RELATED APPLICATION
This application is a Reissue of U.S. Pat. No. 7,170,175, issued Jan. 30, 2007, which claims priority to Japanese Application No. P2003-335703, filed Sep. 26, 2003, the entire contents of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device a the production method therefor, and, particularly to a semiconductor device of a type called a system-in-package (SiP), which is packaged at a wafer level, and a production method therefor.
2. Description of the Related Art
Demands for more compact, thinner and lighter portable electronic devices, such as digital video cameras, digital cellular phones, and notebook computers, only get stronger. To respond thereto, seven tenths of a reduction has been realized in three years in a recent VLSI and other semiconductor devices, while studies and developments have been made on the significant issue of how to improve packaging density of components on a mounting board (printed wiring board) in an electronic circuit device wherein such a semiconductor device is mounted on a printed wiring board.
For example, the package type of a semiconductor device has shifted from the lead-inserted type, such as a dual inline package (DIP), to the surface-mounted type. Furthermore, a flip-chip mounting method for providing a bump (protruding electrode) made of solder or gold on a pad electrode of a semiconductor chip and connecting to the wiring board via the bump with the surface facing downward has been developed.
In the above semiconductor device, when forming multilayer wiring, also called rewiring layers, on the semiconductor substrate (chip), for example, an insulating layer is formed to be a film thickness of 1 μm or less on a surface of a semiconductor wafer formed with a transistor and other semiconductor elements by the chemical vapor deposition (CVD) method, the sputtering method, the thermal oxidization method or the spin coating method, etc., and dicing processing is performed to obtain a small piece of semiconductor device.
In the above production method, even when a step is generated on the insulating layer and warps arise on the wafer, it is sufficient to pay attention only to the blade and chipping at the dicing stage and it is unnecessary to pay attention to the step disconnection of a resist and warps of the wafer.
Furthermore, development has been advanced to a complicated type of package called a system-in-package (SiP) wherein a passive element, such as a coil, and other semiconductor chips are buried in an interlayer of an insulating layer for insulating rewiring layers formed on a semiconductor substrate (chip) and packaged at a wafer level.
As a production method of the SiP, for example, a method of forming as the insulating layer of the rewiring layers an insulating layer made of a polyimide resin and an epoxy resin, etc., to be a film thickness of 10 μm or less by the spin coating method on the surface of the semiconductor wafer formed with a transistor and other semiconductor element and performing dicing processing to obtain a small piece has been widely used.
Here, in the case where property values of the insulating layer are different in an elastic modulus and a thermal expansion coefficient from those in the semiconductor made by silicon, etc., a method of removing a resin on a scribe line in advance and cutting on the exposed scribe line to obtain a small piece is used.
In the production method of the SiP as above, in the case where the insulating layer of the rewiring layers is made to be a multilayer of, for example, three layers or more, when assuming that a film thickness of one layer is 10 μm at minimum, the thickness becomes 30 μm by putting the three layers together, so that it becomes relatively impossible to ignore the film thickness of the insulating layer of the rewiring layer in the case where, for example, a silicon substrate is made to be as thin as 50 μm or less.
Furthermore, in the case of forming a coil and other passive elements in an interlayer of the insulation layer of the rewiring layers in the SiP structure and in the case of burying a semiconductor chip, the film thickness of the whole insulating layer of the rewiring layers has to be 50 μm or more, and an effect given to warps of the semiconductor wafer becomes large.
When warps arise on the semiconductor wafer, an adsorbent error and a conveyance error may be caused in a production facility and breakage and a decline of the yield may also be brought. Furthermore, a disadvantage of a decline of secondary connection reliability is unfavorably caused due to residual stress.
SUMMARY OF THE INVENTION
An object of the present invention is to prevent the arising of warps of a semiconductor wafer when an insulating layer in rewiring layers becomes thick in a SiP type semiconductor device, which may cause an adsorption error and a conveyance error in a production facility, breakage, a decline of the yield and a decline of secondary connection reliability due to residual stress.
According to the present invention, there is provided a semiconductor device comprising a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof which are taken out from the electronic circuit, an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip, and a wiring layer formed to be electrically connected to the electrodes and buried in the insulating layer, wherein the plurality of resin layers is formed so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.
In the semiconductor device of the present invention, an insulating layer is configured by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wherein a wiring layer is buried to be electrically connected to electrodes.
Here, the plurality of resin layers has the configuration wherein the layers' formation areas become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.
Also, according to the present invention, there is provided a production method of a semiconductor device, including the steps of forming integrated electronic circuits corresponding to a plurality of semiconductor chips on a semiconductor wafer, and forming electrodes on a surface of the semiconductor wafer by taking them out from the electronic circuits, forming a pattern of a first resin layer on the surface of the semiconductor wafer except for a scribe line to be a dicing region, forming on the first resin layer a pattern of a first wiring layer electrically connected to the electrodes, forming a pattern of a second resin layer to cover the first resin layer and the first wiring layer except for the scribe line, and dicing the semiconductor wafer on the scribe line, wherein in the step of forming the second resin layer, the second resin layer is formed on a smaller area than that of the first resin layer, so that a side surface and an upper surface of each of the first resin layer and the second resin layer form a stepwise shape.
In the production method of the semiconductor device of the present invention, electronic circuits corresponding to a plurality of semiconductor chips are formed to be integrated on the semiconductor wafer first, and electrodes are formed on its surface by being taken out from the electronic circuits.
Next, a pattern of a first resin layer is formed on a surface of the semiconductor wafer except for a scribe line to be a dicing region, a pattern of a first wiring layer is formed on the first resin layer and electrically connected to the electrodes, and a pattern of a second resin layer is formed to cover the first resin layer and the first wiring layer except for the scribe line.
Next, dicing for cutting the semiconductor wafer on the scribe line is performed.
When forming the second resin layer, it is formed to have a smaller area than that of the first resin layer, so that a side surface and an upper surface of each of the first resin layer and the second resin layer form a stepwise shape.
BRIEF DESCRIPTION OF DRAWINGS
These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, in which:
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
FIG. 2A to FIG. 2C are views of production steps of the semiconductor device according to the embodiment of the present invention;
FIG. 3A to FIG. 3C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention;
FIG. 4A to FIG. 4C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention;
FIG. 5A to FIG. 5C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention; and
FIG. 6A to FIG. 6C are sectional views of production steps of the semiconductor device according to the embodiment of the present invention.
 DESCRIPTION OF THE PREFERRED EMBODIMENT
Below, an embodiment of the present invention will be explained with reference to the drawings.
FIG. 1 is a schematic sectional view of a semiconductor device according to the present embodiment.
On the surface of a semiconductor chip (semiconductor substrate) 10a formed with an electronic circuit including a transistor and other semiconductor elements, electrodes (not shown) taken out from the electronic circuit are formed. On the semiconductor substrate (chip) 10a, an insulating layer configured by stacking a first resin layer 20, a second resin layer 21, a third resin layer 22 and a fourth resin layer 23 is formed.
Wiring layers composed of first wiring layers (30, 31), second wiring layers (32, 33) and third wiring layers (34, 35) are formed by being buried in the insulating layer composed of the above stacked resin layers. The wiring layers are formed to be electrically connected to the electrodes taken out from the electronic circuit of the semiconductor chip 10a in a not shown part.
In the above configuration, formation areas of the first resin layer 20, the second resin layer 21, the third resin layer 22 and the fourth resin layer 23 become gradually smaller from an area of an upper surface of the semiconductor chip 10a as they get farther from the semiconductor chip 10a, so that a side surface and an upper surface of each of the first resin layer 20, the second resin layer 21, the third resin layer 22 and the fourth resin layer 23 and an upper surface of the semiconductor chip 10a form a stepwise shape.
Each of the widths (D1, D2 and D3) of exposed upper surfaces of the respective resin layers (20, 21 and 22) on the stepwise formed portion is preferably 5 μm or more, and is, for example, 5 μm. Note that a width D0 of an exposed part of the semiconductor chip 10a being out of the first resin layer 20 depends on the width of the scribe line on the semiconductor wafer before dicing, and is, for example, 10 μm or so. When the above widths (D1, D2 and D3) are 5 μm or more, coverage of a resist film covering over the scribe line becomes preferable in the production method.
It is also possible to form the electronic element and/or the semiconductor chip by burying them in the insulating layer so as to be electrically connected to the respective wiring layers.
According to the semiconductor device of the above present embodiment, in a SiP-type semiconductor device wherein an insulating layer is configured by stacking a plurality of resin layers on a semiconductor chip, it is configured so that formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, and consequently, a stress imposed on the semiconductor wafer is small even in a stage before dicing and warps are suppressed.
Next, a production method of the above semiconductor device will be explained with reference to the drawings.
First, as shown in FIG. 2A, electronic circuits (not shown) including a transistor and other semiconductor elements and corresponding to a plurality of semiconductor chips are formed to be integrated on the semiconductor wafer 10. Furthermore, electrodes (not shown) are formed on the surface of the semiconductor wafer 10 so as to be taken out from the electronic circuits.
Next, as shown in FIG. 2B, except for a scribe line SL to be a dicing region, a pattern of the first resin layer 20 is formed, for example, to be a film thickness of 10 μm or so on the semiconductor wafer 10.
The first resin layer is formed by using a negative photosensitive resin material, such as a polyimide resin, an epoxy resin and an acrylic resin, by the spin coating method, the printing method or the CVD method, etc., and subjected to exposure by using a photomask, so that regions other than the scribe line are irradiated. When using, for example, a photosensitive polyimide resin, the exposure is performed by broadband exposure to covering lights of a g-line, an h-line and an i-line with energy of 300 mJ/cm2. In the case of an epoxy resin, exposure is performed with energy of 2000 mJ/cm2.
Furthermore, development processing is performed by using a 2.38% trimethylammonium hydroxide solution as a developing solution. Due to photosensitivity of the used resin, the scribe line SL opens in the development stage. Here, in the case of a negative photosensitive resin, as a result that curing proceeds by photoreaction, a pattern shape varies by the exposure condition and the actual condition, but it becomes a tapered opening shape.
The scribe line SL is formed to be a width of, for example, 78 μm.
Next, as shown in FIG. 2C, a seed layer 30 is formed all over, for example, by the sputtering method. As a seed layer for plating copper, for example, a film of Ti/Cu is formed to be a film thickness of 160 nm/600 nm.
Next, as shown in FIG. 3A, a negative or positive resist film is formed on the seed layer 30, for example, by the spin coating; pattern exposure is performed by using a photomask, so that the pattern remains on regions other than formation regions of the first wiring layer in a predetermined wiring circuit pattern; and development processing is performed to form a pattern of the first resist film R1. The regions not formed with the first resist film R1 become formation regions of the first wiring layer. Since the first wiring layer is not formed on the scribe line SL, it is covered with the first resist film R1.
Next, as shown in FIG. 3B, a copper film is formed on regions other than the formation regions of the first resist film R1 by performing electroforming plating processing using the seed layer 30 as one electrode, and a copper plating layer 31 is formed in a predetermined wiring circuit pattern.
Next, as shown in FIG. 3C, the first resist film R1 is peeled by solvent processing, etc. to make the copper plating layer 31 exposed. Wet etching, etc., is performed by using the copper plating layer 31 as shown in FIG. 4A, and the seed layer 30 between the copper plating layers 31 is removed in order to insulate. As a result, the first wiring layer composed of the seed layer 30 and the copper plating layer 31 is formed. While the first wiring layer is not shown in FIG. 4A, it is formed so as to be connected to electrodes (not shown) provided on the surface of the semiconductor wafer 10.
Next, as shown in FIG. 4B, except for the scribe line SL to be a dicing region and a via hole VH, a pattern of the second resin layer 21 is formed to be a film thickness of, for example, 10 μm or so on the first wiring layer (30, 31).
The second resin layer 21 can be formed by the same means and material as those of the first resin layer 20. In the step of forming the second resin layer 21, the layer is formed to have a smaller area than that of the first resin layer 20, so that a side surface and an upper surface of the first resin layer 20 and the second resin layer 21 form a stepwise shape.
On the stepwise formed portion, a width D1 of the exposed upper surface of the first resin layer 20 that is out of the second resin layer 21 is preferably 5 μm or more and is assumed to be, for example, 5 μm.
The via hole VH connected to the first wiring layer (30, 31) can be formed in the same way.
Next, as shown in FIG. 4C, a seed layer 32 is formed all over, for example, by the sputtering method in the same way as the above.
Since the width D1 of the exposed upper surface of the first resin layer 20 that is out of the second resin layer 21 is 5 μm or more, coverage of the seed layer 32 covering the scribe line becomes preferable and step disconnection on the seed layer 32 can be prevented.
Next, as shown in FIG. 5A, a resist film is formed on the seed layer 32, for example, by spin coating and a pattern of a second resist film R2 for protecting the scribe line SL and regions other than formation regions of the second wiring layer is formed.
Since the width D1 of the exposed upper surface of the first resin layer 20 that is out of the second resin layer 21 is 5 μm or more, coverage of the resist film R2 covering the scribe line becomes preferable and step disconnection on the resist film R2 can be prevented.
Next, as shown in FIG. 5B, electroforming plating processing is performed by using the seed layer 32 as one electrode to form a copper film on regions other than the formation regions of the second resist film R2, and a copper plating layer 33 is formed in a predetermined wiring circuit pattern.
Next, as shown in FIG. 5C, the second resist film R2 is peeled, and the seed layer 32 between the respective copper plating layer 33 is removed by etching, as shown in FIG. 6A, to form a second wiring layer composed of the seed layer 32 and the copper plating layer 33. The second wiring layer is formed to be electrically connected to the first wiring layer via the via hole VH.
Next, as shown in FIG. 6B, by repeating the same steps as above, the third resin layer 22 and the fourth resin layer 23 are formed in the same way as the first resin layer 20 and the second resin layer 21, and the third wiring layer (34, 35) is formed in the same way as the first wiring layer (30, 31) and the second wiring layer (32, 33), respectively. The third wiring layer (34, 35) is formed to be connected to the second wiring layer (32, 33) in the via hole.
Here, in a step of forming the third resin layer 22, the layer is formed to have a smaller area than that of the second resin layer 21, so that a side surface and an upper surface of each of the second resin layer 21 and the third resin layer 22 form a stepwise shape. Also, in a step of forming the fourth resin layer 23, the layer is formed to have a smaller area than that of the third resin layer 22, and a width (D2, D3) of an exposed upper surface of a lower resin layer that is out of its upper resin layer is 5 μm or more, for example 5 μm, so that a side surface and an upper surface of each of the third resin layer 22 and the fourth resin layer 23 form a stepwise shape.
In the above steps, the first to fourth resin layers (20, 21, 22 and 23) are not formed on the scribe line SL on the semiconductor wafer 10, and the upper surface of the semiconductor wafer 10 is exposed.
Here, by performing a dicing step for cutting the semiconductor wafer 10 into a semiconductor chip 10a along the scribe line SL by using a dicing blade B (with a blade rotation speed of 3000 rpm and a feeding speed of 10 to 15 mm/second), a semiconductor device made to be a small piece, as shown in FIG. 1 , is obtained.
In the above dicing step, only the semiconductor wafer is cut and it is not necessary to cut the resin layers; there is therefore the advantage that it is not necessary to select a special blade, either.
In a laminated beam model obtained by putting one substrate with other substrate, when the temperature changes from T0 to T1, expansion of one substrate (a linear expansion coefficient α1) becomes α1 (T1−T0), and expansion of the other substrate (a linear expansion coefficient α2) becomes α2 (T1−T0).
When assuming that the Young's modulus of one substrate is E1 and that of the other substrate is E2 and α1<α2, a compression stress of ¼E(α2−α1)(T1−T0) acts on the one substrate, and the same amount of an extension stress acts on the other substrate.
Accordingly, the effects of removing resin layers on the scribe line as above are to shorten a unit length and to disperse the stresses.
EXAMPLE
In the case of forming a resin layer as four stacked layers (a film thickness of 50 μm in total) on a semiconductor wafer, on which semiconductor chips of 3 mm square are integrated, warps of the semiconductor wafer (a distance of one end portion floating from a plane when pressing the other end of the wafer on the plane) could be reduced by 200 μm by applying the present embodiment.
As explained above, in the production method of a semiconductor device according to the present embodiment, resin layers on the scribe line are removed when stacking the resin layers at a wafer level, and furthermore, a side surface and an upper surface of each of the resin layers are formed to be a stepwise shape, so that warps of the semiconductor wafer can be prevented even without using a resin layer material having special properties.
Also, since the film thickness of the resin layers stacked on the surface other than the scribe line causes warps, the film thickness of the stacked resin layers can be made thicker compared with that in the configuration in which the scribe line is not removed. Namely, when assuming that the film thickness per one layer is not changed, the number of resin layers to be stacked can be increased.
Also, when using resin layers having the same property values, warps of the wafer are reduced only by making the scribe line wide.
Furthermore, in the dicing step, only the semiconductor wafer is cut and it is not necessary to cut resin layers, so that it is not necessary to select a special blade, either. Additionally, it is difficult for the semiconductor wafer and the resin layers to come apart when dicing, and adjustment of the blade feeding speed becomes unnecessary. Accordingly, high throughput can be attained.
The present invention is not limited to the above explanation.
For example, while not described in the above production method of the embodiment, in the step of forming stacked resin layers and a wiring layer on a boundary surface thereof, an electronic element and/or a semiconductor chip may be formed by being buried so as to be electrically connected to a lower wiring layer.
In the above embodiment, four resin layers are stacked, but the number of the layers is not limited to this; the stacked body may be two-layered, three-layered, five-layered or more.
Also, between the semiconductor chip and the resin layers, a buffer layer having an intermediate linear expansion coefficient of both may be provided in accordance with need. The buffer layer is, for example, composed of an epoxy resin layer, etc. filled with filler.
Other than the above, a variety of modifications may be made within the scope of the present invention.
According to the semiconductor device of the present invention, in a SiP-type semiconductor device wherein an insulating layer is configured by stacking a plurality of resin layers on a semiconductor chip, the layer is configured so that formation areas of the plurality of resin layers become gradually smaller from an area of the upper surface of the semiconductor chip, and a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, so that a stress imposed on the semiconductor wafer is small even in a stage before dicing and warps are suppressed.
According to the production method of the semiconductor device of the present invention, in a production method of a SiP-type semiconductor device wherein an insulating layer is configured by a plurality of resin layers stacked on a semiconductor chip, when forming by stacking the first resin layer and the second resin layer, except for the scribe line that is to be a dicing region, the layers are formed so that their areas become gradually smaller from an area of an upper surface of the semiconductor chip, and a side surface and an upper surface of each of the first resin layer and the second resin layer form a stepwise shape, and consequently, a stress imposed on the semiconductor wafer is small even in a stage before dicing and warps can be suppressed in producing a semiconductor device.
The semiconductor device of the present invention can be applied to a system-in-package-type semiconductor device.
The production method of the semiconductor device of the present invention can also be applied for producing a system-in-package-type semiconductor device.

Claims (39)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof that are taken out from the electronic circuit;
an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip; and
a wiring layer formed so as to be electrically connected to the electrodes and buried in the insulating layer; wherein
the plurality of the resin layers is formed, so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and
a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, wherein widths of exposed upper surfaces of the resin layers at the stepwise shaped portion are 5 μm or more in the plurality of the resin layers.
2. The semiconductor device as set forth in claim 1, wherein widths of exposed upper surfaces of the resin layers at the stepwise shaped portion are 5 μm or more in the plurality of the resin layers.
3. The semiconductor device as set forth in claim 1, wherein further comprising an electronic element and/or a another semiconductor chip are formed by being buried in the insulating layer so as to be electrically connected to the wiring layer.
4. A semiconductor device, comprising:
a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof that are taken out from the electronic circuit;
an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip; and
a wiring layer formed so as to be electrically connected to the electrodes and buried in the insulating layer; wherein
the plurality of the resin layers is formed, so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and
a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, wherein an electronic element and/or another semiconductor chip are formed by being buried in the insulating layer so as to be electrically connected to the wiring layer.
5. A semiconductor device, comprising:
a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof that are taken out from the electronic circuit;
an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip; and
a wiring layer formed so as to be electrically connected to the electrodes and buried in the insulating layer; wherein
the plurality of the resin layers is formed, so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and
a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, wherein
the plurality of resin layers includes a first resin layer having a tapered edge.
6. The semiconductor device as set forth in claim 5, wherein:
the plurality of resin layers includes a second resin layer, the second resin layer have a smaller formation area than the first resin layer.
7. The semiconductor device as set forth in claim 6, wherein
a ratio of a thickness of the first resin layer to a distance, D1, from an outer edge of the first resin layer to an outer edge of the second resin layer being 2 or less.
8. The semiconductor device as set forth in claim 6, wherein
a distance from an outer edge of the first resin layer to an outer edge of the second resin layer being 5 μm or more.
9. The semiconductor device as set forth in claim 5, wherein
a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.
10. The semiconductor device as set forth in claim 9, wherein
the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.
11. The semiconductor device as set forth in claim 6, wherein
in at least one location, a film thickness of at least one of the first resin layer and the second resin layer being substantially 10 μm.
12. The semiconductor device as set forth in claim 5, wherein
the first resin layer being at least one of polymide, epoxy and/or acrylic.
13. The semiconductor device as set forth in claim 5, further comprising:
a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.
14. The semiconductor device as set forth in claim 5, wherein
an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.
15. The semiconductor device as set forth in claim 5, wherein
a length of at least one side surface of the semiconductor chip being 3 mm or less.
16. The semiconductor device as set forth in claim 5, further comprising:
a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.
17. The semiconductor device as set forth in claim 16, wherein
the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.
18. The semiconductor device as set forth in claim 7, wherein
a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.
19. The semiconductor device as set forth in claim 18, wherein
the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.
20. The semiconductor device as set forth in claim 19, further comprising:
a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.
21. The semiconductor device as set forth in claim 20, wherein
an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.
22. The semiconductor device as set forth in claim 21, further comprising:
a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.
23. The semiconductor device as set forth in claim 22, wherein
the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.
24. The semiconductor device as set forth in claim 1, wherein:
the plurality of resin layers includes a second resin layer, the second resin layer have a smaller formation area than the first resin layer.
25. The semiconductor device as set forth in claim 24, wherein
a ratio of a thickness of the first resin layer to a distance, D1, from an outer edge of the first resin layer to an outer edge of the second resin layer being 2 or less.
26. The semiconductor device as set forth in claim 1, wherein
a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.
27. The semiconductor device as set forth in claim 26, wherein
the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.
28. The semiconductor device as set forth in claim 27, further comprising:
a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.
29. The semiconductor device as set forth in claim 28, wherein
an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.
30. The semiconductor device as set forth in claim 29, further comprising:
a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.
31. The semiconductor device as set forth in claim 30, wherein
the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.
32. The semiconductor device as set forth in claim 4, wherein:
the plurality of resin layers includes a second resin layer, the second resin layer have a smaller formation area than the first resin layer.
33. The semiconductor device as set forth in claim 32, wherein a ratio of a thickness of the first resin layer to a distance, D1, from an outer edge of the first resin layer to an outer edge of the second resin layer being 2 or less.
34. The semiconductor device as set forth in claim 4, wherein
a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.
35. The semiconductor device as set forth in claim 34, wherein
the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.
36. The semiconductor device as set forth in claim 35, further comprising:
a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.
37. The semiconductor device as set forth in claim 36, wherein
an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.
38. The semiconductor device as set forth in claim 37, further comprising:
a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.
39. The semiconductor device as set forth in claim 38, wherein
the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.
US17/021,673 2003-09-26 2020-09-15 Semiconductor device and production method thereof Active 2025-07-17 USRE49631E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/021,673 USRE49631E1 (en) 2003-09-26 2020-09-15 Semiconductor device and production method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2003-335703 2003-09-26
JP2003335703A JP4206885B2 (en) 2003-09-26 2003-09-26 Manufacturing method of semiconductor device
US10/930,797 US7170175B2 (en) 2003-09-26 2004-09-01 Semiconductor device and production method thereof
US17/021,673 USRE49631E1 (en) 2003-09-26 2020-09-15 Semiconductor device and production method thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/930,797 Reissue US7170175B2 (en) 2003-09-26 2004-09-01 Semiconductor device and production method thereof

Publications (1)

Publication Number Publication Date
USRE49631E1 true USRE49631E1 (en) 2023-08-29

Family

ID=34373220

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/930,797 Ceased US7170175B2 (en) 2003-09-26 2004-09-01 Semiconductor device and production method thereof
US11/588,315 Active 2025-09-14 US7510910B2 (en) 2003-09-26 2006-10-27 Semiconductor device and production method thereof
US17/021,673 Active 2025-07-17 USRE49631E1 (en) 2003-09-26 2020-09-15 Semiconductor device and production method thereof

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10/930,797 Ceased US7170175B2 (en) 2003-09-26 2004-09-01 Semiconductor device and production method thereof
US11/588,315 Active 2025-09-14 US7510910B2 (en) 2003-09-26 2006-10-27 Semiconductor device and production method thereof

Country Status (2)

Country Link
US (3) US7170175B2 (en)
JP (1) JP4206885B2 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4206885B2 (en) 2003-09-26 2009-01-14 ソニー株式会社 Manufacturing method of semiconductor device
JP3880600B2 (en) * 2004-02-10 2007-02-14 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP4331769B2 (en) * 2007-02-28 2009-09-16 Ｔｄｋ株式会社 Wiring structure, method for forming the same, and printed wiring board
US7691682B2 (en) * 2007-06-26 2010-04-06 Micron Technology, Inc. Build-up-package for integrated circuit devices, and methods of making same
KR100872711B1 (en) * 2007-06-29 2008-12-05 주식회사 동부하이텍 Chip stacked structure and method of fabricating the same
KR20100071485A (en) * 2008-12-19 2010-06-29 삼성전기주식회사 Manufacturing method of wafer level package
US8436252B2 (en) * 2009-06-30 2013-05-07 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP5536388B2 (en) * 2009-08-06 2014-07-02 株式会社テラプローブ Semiconductor device and manufacturing method thereof
US20110068537A1 (en) * 2009-09-23 2011-03-24 Marshall Menachem 52-Splits Poker Game
JP2011192726A (en) * 2010-03-12 2011-09-29 Renesas Electronics Corp Electronic device, and method of manufacturing the same
JP2012038965A (en) * 2010-08-09 2012-02-23 Lapis Semiconductor Co Ltd Semiconductor device and manufacturing method of the same
US8569086B2 (en) * 2011-08-24 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of dicing semiconductor devices
US8772934B2 (en) 2012-08-28 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Aluminum interconnection apparatus
JP2014154867A (en) * 2013-02-14 2014-08-25 Seiko Epson Corp Semiconductor wafer and semiconductor wafer manufacturing method
US9455184B2 (en) * 2014-06-17 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Aluminum interconnection apparatus
US9806088B2 (en) 2016-02-15 2017-10-31 Toshiba Memory Corporation Semiconductor memory device having memory cells arranged three-dimensionally and method of manufacturing the same
KR102704110B1 (en) 2019-08-09 2024-09-06 삼성전자주식회사 Semiconductor devices including a thick metal layer and a bump
CN114586175B (en) * 2020-09-30 2023-04-18 英诺赛科(苏州)科技有限公司 Semiconductor device and method of manufacturing semiconductor device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5309024A (en) * 1991-06-06 1994-05-03 Kabushiki Kaisha Toshiba Multilayer package
US5723385A (en) * 1996-12-16 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd Wafer edge seal ring structure
US20010023983A1 (en) * 2000-02-28 2001-09-27 Toshiyuki Kobayashi Semiconductor devices
US20020048931A1 (en) * 2000-08-28 2002-04-25 Farrar Paul A. Damascene structure and method of making
US6495917B1 (en) * 2000-03-17 2002-12-17 International Business Machines Corporation Method and structure of column interconnect
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US20030193090A1 (en) * 2000-09-06 2003-10-16 Miharu Otani Semiconductor device and method of manufacturing the semiconductor device
US20030199125A1 (en) * 2001-09-03 2003-10-23 Kabushiki Kaisha Toshiba Fabrication method and wafer structure of semiconductor device using low-k film
US6924238B2 (en) * 2003-06-05 2005-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Edge peeling improvement of low-k dielectric materials stack by adjusting EBR resistance
US7170175B2 (en) 2003-09-26 2007-01-30 Sony Corporation Semiconductor device and production method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251052A (en) 1985-04-27 1986-11-08 Oki Electric Ind Co Ltd Dicing into chips of semiconductor wafer
JPH02188942A (en) 1989-01-17 1990-07-25 Fujitsu Ltd Manufacture of semiconductor device provided with multilayer wiring structure
US5686171A (en) * 1993-12-30 1997-11-11 Vlsi Technology, Inc. Integrated circuit scribe line structures and methods for making same
JPH1074891A (en) 1997-08-07 1998-03-17 Nec Corp Semiconductor device
JP2001127010A (en) 1999-10-25 2001-05-11 Hitachi Ltd Semiconductor device and manufacturing method thereof
NO20001360D0 (en) 2000-03-15 2000-03-15 Thin Film Electronics Asa Vertical electrical connections in stack

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5309024A (en) * 1991-06-06 1994-05-03 Kabushiki Kaisha Toshiba Multilayer package
US5723385A (en) * 1996-12-16 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd Wafer edge seal ring structure
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US20010023983A1 (en) * 2000-02-28 2001-09-27 Toshiyuki Kobayashi Semiconductor devices
US6495917B1 (en) * 2000-03-17 2002-12-17 International Business Machines Corporation Method and structure of column interconnect
US20020048931A1 (en) * 2000-08-28 2002-04-25 Farrar Paul A. Damascene structure and method of making
US20030193090A1 (en) * 2000-09-06 2003-10-16 Miharu Otani Semiconductor device and method of manufacturing the semiconductor device
US20030199125A1 (en) * 2001-09-03 2003-10-23 Kabushiki Kaisha Toshiba Fabrication method and wafer structure of semiconductor device using low-k film
US6924238B2 (en) * 2003-06-05 2005-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Edge peeling improvement of low-k dielectric materials stack by adjusting EBR resistance
US7170175B2 (en) 2003-09-26 2007-01-30 Sony Corporation Semiconductor device and production method thereof

Also Published As

Publication number Publication date
US20070042561A1 (en) 2007-02-22
US20050067706A1 (en) 2005-03-31
US7170175B2 (en) 2007-01-30
JP4206885B2 (en) 2009-01-14
JP2005101463A (en) 2005-04-14
US7510910B2 (en) 2009-03-31

Similar Documents

Publication Publication Date Title
USRE49631E1 (en) Semiconductor device and production method thereof
US7462511B2 (en) Semiconductor device and the method of producing the same
US6759268B2 (en) Semiconductor device and manufacturing method therefor
JP3877717B2 (en) Semiconductor device and manufacturing method thereof
US8143531B2 (en) Electronic component mounting package
US7229856B2 (en) Method of manufacturing electronic part packaging structure
KR100773461B1 (en) Package substrate for a semiconductor device, and a semiconductor device
US7602047B2 (en) Semiconductor device having through vias
KR100605349B1 (en) Semiconductor device and method of manufacturing the same
US8378229B2 (en) Circuit board and method for manufacturing semiconductor modules and circuit boards
KR100583966B1 (en) Integrated circuit packages having redistributed metal lines and methods of fabricating the same
US8330050B2 (en) Wiring board having heat intercepting member
US20110221071A1 (en) Electronic device and manufacturing method of electronic device
US20080142945A1 (en) Semiconductor package with redistribution layer of semiconductor chip directly contacted with substrate and method of fabricating the same
US7902672B2 (en) Semiconductor device and method of manufacturing same
JP2007173749A (en) Semiconductor device and its manufacturing method
JP2004342862A (en) Semiconductor device and its manufacturing method, false wafer and its manufacturing method, and multi-chip module
TW200843063A (en) Structure of semiconductor chip and package structure having semiconductor chip embedded therein
JP2004165193A (en) Semiconductor device and its manufacturing method
US7791196B2 (en) Semiconductor device having a smaller electrostatic capacitance electrode
JP4413206B2 (en) Semiconductor device and manufacturing method thereof
JP4794507B2 (en) Semiconductor device
US20080179727A1 (en) Semiconductor packages having immunity against void due to adhesive material and methods of fabricating the same

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY