USRE42619E1 - Magnetic tunnel junction magnetic device, memory and writing and reading methods using said device - Google Patents
Magnetic tunnel junction magnetic device, memory and writing and reading methods using said device Download PDFInfo
- Publication number
- USRE42619E1 USRE42619E1 US11/861,974 US86197402A USRE42619E US RE42619 E1 USRE42619 E1 US RE42619E1 US 86197402 A US86197402 A US 86197402A US RE42619 E USRE42619 E US RE42619E
- Authority
- US
- United States
- Prior art keywords
- layer
- magnetic
- storage
- magnetization
- storage layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005291 magnetic effect Effects 0.000 title claims abstract description 191
- 238000000034 method Methods 0.000 title claims description 31
- 230000015654 memory Effects 0.000 title claims description 25
- 238000003860 storage Methods 0.000 claims abstract description 246
- 230000000903 blocking effect Effects 0.000 claims abstract description 72
- 230000005415 magnetization Effects 0.000 claims abstract description 59
- 230000005290 antiferromagnetic effect Effects 0.000 claims abstract description 49
- 238000002347 injection Methods 0.000 claims abstract description 7
- 239000007924 injection Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 497
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 29
- 238000001816 cooling Methods 0.000 claims description 28
- 238000010438 heat treatment Methods 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 17
- 229910045601 alloy Inorganic materials 0.000 claims description 16
- 239000000956 alloy Substances 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 16
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 15
- 230000007423 decrease Effects 0.000 claims description 11
- 229910052697 platinum Inorganic materials 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 9
- 229910005335 FePt Inorganic materials 0.000 claims description 8
- 229910019041 PtMn Inorganic materials 0.000 claims description 8
- 229910017052 cobalt Inorganic materials 0.000 claims description 8
- 239000010941 cobalt Substances 0.000 claims description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052763 palladium Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 6
- 229910052742 iron Inorganic materials 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 230000003993 interaction Effects 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910020708 Co—Pd Inorganic materials 0.000 claims description 2
- 229910020707 Co—Pt Inorganic materials 0.000 claims description 2
- 229910015187 FePd Inorganic materials 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052702 rhenium Inorganic materials 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 230000010287 polarization Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 24
- 230000000694 effects Effects 0.000 description 9
- 230000006870 function Effects 0.000 description 9
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 239000002885 antiferromagnetic material Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229920006395 saturated elastomer Polymers 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 101100450272 Caenorhabditis elegans hcf-1 gene Proteins 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005294 ferromagnetic effect Effects 0.000 description 2
- 239000000696 magnetic material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910018979 CoPt Inorganic materials 0.000 description 1
- 229910015136 FeMn Inorganic materials 0.000 description 1
- 229910003289 NiMn Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000001955 cumulated effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/3254—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y25/00—Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/3286—Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/329—Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/3268—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
- H01F10/3272—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets
Definitions
- the present invention concerns a magnetic tunnel junction device and a memory using said device.
- the invention further concerns a thermomagnetic writing method in said device and a reading method of said device.
- the invention finds an application in electronics and, in particular, in the formation of storage elements and MRAM (Magnetic Random Access Memory) type memories or direct (or random) access magnetic memory.
- MRAM Magnetic Random Access Memory
- MRAM magnetic memories There has been renewed interest in MRAM magnetic memories with the development of MTJ (magnetic tunnel junctions) that have high magnetoresistance at ambient temperature.
- MTJ magnetic tunnel junctions
- FIGS. 1A and 1B schematically illustrate the structure and the function of a known magnetic tunnel junction.
- the junction bears the reference 2 . It is a stack comprising an oxide layer 3 b sandwiched between two magnetic layers. This system functions like a spin gate, with the difference that the current flows perpendicularly to the planes of the layers.
- One 3 a of the magnetic layers is called “free” or “storage” since one can orient its magnetisation in the desired direction by means of an external magnetic field (two directional arrow); the other magnetic layer 3 c is called “pinned” or “reference” since its magnetisation direction is fixed by exchange coupling with an antiferromagnetic layer (single directional arrow).
- the resistance of the junction is high; when the magnetisations are parallel, said resistance becomes low.
- the relative variation of resistance between these two states can attain 40% through an appropriate choice of materials for the layers in the slack and/or thermal treatments of said materials.
- the junction 2 is placed between a switching transistor 4 and a current supply line 6 forming an upper conductive line.
- a current I 1 flowing in said line produces a first magnetic field 7 .
- a conductor 8 forming a lower conductive line, orthogonal to the current supply line 6 enables, by making a current I 2 flow in said line, a second magnetic field 9 to be produced.
- the transistor 4 In the “writing” mode ( FIG. 1A ), the transistor 4 is placed in blocked mode and therefore no current passes through this transistor. One circulates current impulses in the current supply line 6 and in the conductor 8 . The junction 2 is therefore subjected to two orthogonal magnetic fields. One is applied along the axis of difficult magnetisation of the free layer 3 a, in order to reduce its reversal field, whereas the other is applied along its easy axis in order to provoke the reversal of the magnetisation and thus the writing of the storage element.
- the transistor In the “reading” mode ( FIG. 1B , the transistor is place in saturated regime (in other words, the current crossing this transistor is maximum) by sending a positive current impulse in the gate of the transistor.
- the current 13 sent in the line 6 only crosses the storage element in which the transistor is placed in saturated mode.
- the state of the storage element (“0” or “1”) may thus be determined: one then knows if the magnetisation of the storage layer 3 a is parallel or antiparallel to that of the reference layer 3 c.
- the writing mode uses two current lines at 90°, which limits the integration density.
- the aim of the present invention is to overcome the above-mentioned disadvantages.
- a further aim of the present invention is to improve magnetic memories by reducing the size of their storage elements, while at the same time keeping the information stable at ambient temperature, as well as the level of writing errors of said memories.
- the present invention concerns a magnetic device comprising a magnetic tunnel junction that comprises:
- a first magnetic layer forming a reference layer and having a magnetisation of fixed direction
- a second magnetic layer forming a storage layer and having a magnetisation of variable direction
- a third layer that is semiconductive or electrically insulating and which separates the first layer from the second layer
- means for heating the storage layer to a temperature higher than the blocking temperature of the magnetisation of said storage layer said means of heating the storage layer being means provided to make an electric current flow through the magnetic tunnel junction
- the blocking temperatures of the storage and reference layers have values greater than the value of the operating temperature of the device outside of heating of the tunnel junction (one knows that the device heats up when it operates).
- the magnetisation of each of the storage and reference layers is substantially perpendicular to the plane of said layers.
- the storage layer may be a mono-layer in Co—Pt or Co—Pd alloy or a multi-layer formed by a stack of Co layers alternating with layers of Pt or Pd in such a way that the coercive field of the storage layer rapidly decreases when the temperature increases.
- the storage layer may be a mono-layer in cobalt rich alloy with iron or nickel or chromium and platinum or palladium, or a multi-layer formed by a stack of layers of an alloy rich in cobalt with iron or nickel or chromium, alternating with layers of Pt or Pd in such a way that the coercive field of the storage layer rapidly decreases when the temperature increases.
- each of the storage and reference layers is substantially parallel to the plane of said layers.
- the device of the invention may further comprise a first antiferromagnetic layer combined with the reference layer.
- the blocking temperature of the magnetisation of said first antiferromagnetic layer is higher than the blocking temperature of the storage layer.
- the reference layer is a multi-layer comprising two magnetic layers and an intermediate layer in Ru or Re or Ir or Rh, the two magnetic layers being separated by the intermediate layer and coupled in an antiparallel manner by interaction through said intermediate layer.
- said device further comprises a second antiferromagnetic layer coupled to the storage layer by exchange anisotropy.
- the blocking temperature of the magnetisation of said second antiferromagnetic layer is lower than the blocking temperature of the reference layer.
- the means of applying the magnetic field torque to the magnetization of the storage layer may comprise means of injecting, in said storage layer, a current of electrons in which the spin is polarised.
- the present invention also concerns a memory comprising a matrix of storage elements that are addressable by addressing lines and columns, said memory being characterised in that each storage element comprises:
- each magnetic device being linked to an addressing line and each means of switching being linked to an addressing column.
- the present invention also concerns a method for writing information in a magnetic device according to the invention, in which:
- the value, seen by the reference layer, of the magnetic field applied during the storage is less than the value that the reversal magnetic field of the magnetisation of the reference layer reaches at the maximum temperature attained by said layer during the heating of the junction.
- the storage layer is coupled to an antiferromagnetic layer by exchange anisotropy and one heats the storage layer and said antiferromagnetic layer to a temperature higher than the blocking temperatures of the magnetisation of said layers and, during the cooling of the antiferromagnetic layer, one orientates the magnetisation of the storage layer in any direction whatsoever predefined by the direction of magnetisation of the magnetic field applied during the cooling,
- the present invention further concerns a method for reading information memorised in a device according to the invention, in which
- FIGS. 1A and 1B schematically illustrate the operating principle of a known magnetic tunnel junction device, and have already been described
- FIG. 2 is a schematic and partial view of a memory comprising a matrix of magnetic tunnel junction devices
- FIG. 3 schematically illustrates the operating principle of a magnetic tunnel junction device according to the invention
- FIG. 4 is a schematic cross sectional view of a tunnel junction that may be used in the present invention and in which the layers have a magnetisation perpendicular to the plane of said layers,
- FIG. 5 is a graph illustrating the formation of two different coercive fields by coupling to an antiferromagnetic material one of the two layers of a tunnel junction that may be used in the invention
- FIG. 6 is a graph showing the variations in the reversal field as a function of the temperature for multi-layers that may be used in the invention.
- FIG. 7 schematically illustrates an example of a series of magnetic devices according to the invention, using tunnel junctions with magnetisation perpendicular to the plane of their layers,
- FIG. 8 schematically illustrates an example of magnetic device according to the invention, using the combination of heating by Joule effect and magnetic switching by injection of a current of electrons in which the spin is polarised
- FIG. 9 is a schematic cross sectional view of an example of tunnel junction that may be used in the invention and has a planar magnetisation
- FIG. 10 is a schematic view of an example of magnetic device according to the invention, using a tunnel junction with planar magnetisation, and
- FIG. 11 is a schematic view of another example of said device.
- a magnetic memory comprises a matrix of magnetic devices according to the invention.
- Each of said devices also called “storage elements”, comprises a magnetic tunnel junction of the form F 1 /O/F 2 where F 1 and F 2 respectively designate the magnetic storage layer, also called the “storage magnetic electrode”, and the magnetic reference layer, also called “reference magnetic electrode”, and O designates the layer that is comprised between F 1 and F 2 and forms a tunnel barrier.
- Each of the layers F 1 and F 2 is characterised by a reversal field of its magnetisation, said field being a function of the temperature of the material forming this layer.
- the materials of layers F 1 and F 2 are chosen in such a way that the reduction in temperature of the reversal field of layer F 1 , designated HcF 1 , is a lot quicker than that of the reversal field of layer F 2 , designated HcF 2 .
- the materials for layers F 1 and F 2 in such a way that their reversal fields are, at ambient temperature (around 20° C.), around 100 Oe (around 8000 A/m) for F 1 (it is recalled that 1 Oe equals 1000/(4 ⁇ ) A/m) and around 600 Oe (around 48000 A/m) for F 2 and, at 200° C., around 5 Oe (around 400 A/m) for F 1 and 400 Oe (around 32000 A/m) for F 2 .
- the materials for layers F 1 and F 2 in such a way that the blocking temperature of the magnetisation of layer F 1 , also called “magnetic blocking temperature” of layer F 1 or, more simply, “blocking temperature” of layer F 1 , is significantly lower than the blocking temperature of the magnetisation of layer F 2 .
- the principle of the selection of a storage element then consists in provoking a very brief heating (up to a temperature Tmax, typically up to 200° C.) of said storage element, said heating having the effect of lowering the reversal field of the magnetisation of the magnetic layer F 1 in which the information is stored.
- the storage and reference layers must preferably have blocking temperatures higher than the operating temperature of the device outside of heating.
- the heating of the junction may be controlled by sending a short current impulse (around 10 5 A/cm 2 to 10 6 A/cm 2 for a few nanoseconds) through the junction.
- the magnetic field He is created by sending current impulses in the conductive lines situated in the planes lying above and/or below the magnetic tunnel junctions.
- a second possibility of provoking the switching of the magnetisation of the storage layer during its cooling may consist in injecting in said layer a current of electrons in which the spin is polarised, according to one of the techniques detailed hereafter.
- the present invention consists in this case in combining the heating of the material of the storage layer, in order to reduce the reversal field of the magnetisation of said layer, with the application of a magnetic torque to this magnetisation, during the cooling of the storage layer, by flowing a current of electrons in which the spin is polarised through the storage layer.
- the present invention enables much better selection of storage elements than known technologies. Indeed, let us assume that the storage elements are organised into a square array as seen in FIG. 2 , which represents the architecture of a known MRAM.
- control lines 14 that act on the transistor gates 4 to put them into the passing position (saturated) or closed position (blocked).
- the writing is carried out by sending current impulses along the upper and lower conductive lines, which cross at the storage element that one wishes to address.
- certain storage elements situated along the lines risk reversing in an uncontrolled manner.
- FIG. 3 shows a magnetic device 16 according to the invention, forming a storage element, or cell, of a MRAM memory according to the invention.
- Said storage element comprises a magnetic tunnel junction 18 , comprising a storage layer 20 a, a reference layer 20 c and an insulating or semiconduetive layer 20 b between these layers.
- This junction is placed between an upper conductive line 22 and a switching transistor 24 and combined with a lower conductive line 26 that is perpendicular to the line 22 .
- junctions of the memory of FIG. 3 are organised in a square array as in the memory in FIG. 2 (in which the references of the elements are moreover followed, in brackets, by references of the corresponding elements of FIG. 3 ). Consequently, only one junction of the whole array will be heated by the current impulse 30 , all of the others remaining at ambient temperature.
- the lowering of the reversal field linked to the temperature rise (typically from 100 Oe, at 20° C., to 5 Oe, at 200° C.) is a much more significant than the distribution width of the reversal field at ambient temperature (typically 100 Oe ⁇ 20 Oe).
- the line 26 is not indispensable for creating the magnetic field.
- the operation of the storage element 16 of FIG. 3 is therefore as follows: since the addressing transistor 24 is in the passing state, the writing is achieved by sending a current impulse through the junction 18 to heat the junction up to around 200° C. During the cooling of the junction, a current impulse is sent in the lower conductive line 26 to generate a magnetic field in the storage layer 20 a, which has the effect of switching the magnetisation of said layer in the desired direction.
- the reading is achieved with the transistor in the passing state by making a current flow through the junction (the current being lower than during the writing so that the heating is less), which makes it possible to measure the resistance and thus to know if the magnetisation of the storage layer 20 a is parallel or antiparallel to that of the reference layer 20 c.
- the electrical consumption may be divided by 10 with the operating principle of the present invention.
- the present invention makes it possible to use, for the storage layer, materials with high pinning energy at ambient temperature. In the prior art, this is not possible since the higher the pinning of the storage layer, the more it is necessary to supply energy to switch the magnetisation of the storage layer.
- K and V respectively designate the magnetic anisotropy per unit of volume (or, more generally, the pinning energy per unit of volume) and the volume of the storage layer, the information becomes unstable if KV ⁇ 25 kT (where k is the Boltzmann constant and T the temperature).
- this limit is always reached at one moment or another when one reduces the size of the storage element whereas, in the present invention, one can very easily compensate the reduction in the volume by an increase in the pinning energy at ambient temperature and thus reduce the size of the storage element as far as the manufacturing method used (for example, lithography/engraving) allows.
- the basic structure in the present invention, comprises two magnetic layers F 1 and F 2 separated by a tunnel barrier O in such a way that one may designate this structure F 1 /O/F 2 .
- the two magnetic layers are such that the reversal field of the magnetisation of one of these two magnetic layers (the storage layer) decreases much more quickly, when the temperature increases, than that of the other magnetic layer (the reference layer).
- the magnetisations of the two layers F 1 and F 2 are perpendicular to the plane of the layers or, more precisely, to the interfaces of said layers.
- Layers F 1 and F 2 may comprise a pure material, an alloy or a series of alternating layers, certain of which are magnetic.
- Co layers of hexagonal structure, have their magnetisation perpendicular to the plane of these layers if the axis c of the hexagonal lattice is perpendicular to the plane of the sample containing said layers. Alloy layers such as CoPt, FePd and FePt may also have magnetisations perpendicular to their planes. Finally, multi-layers comprising alternating layers of two different materials at least one of which is magnetic, such as for example Co 0.6 nm/Pt 1.4 nm, may also have magnetisations perpendicular to the plane.
- the cobalt may easily be replaced by an alloy rich in Co (greater than 70%) with for example Fe or Ni or Cr.
- FIG. 4 An example of forming a multi-layer Co/Pt based magnetic tunnel junction, which may be used in the present invention, is shown in FIG. 4 .
- said magnetic tunnel junction comprises a reference layer 36 and a storage layer 38 that have a magnetisation perpendicular to the plane of said layers;
- the reference layer 36 comprises layers 40 in cobalt that alternate with layers 42 in platinum;
- the storage layer 38 comprises layers 44 in cobalt that alternate with layers 46 in platinum;
- the layers 36 and 38 are separated by a tunnel barrier layer 48 in alumina.
- the adjacent ferromagnetic layer sees the value of its blocking temperature increase up to the value of that of the antiferromagnetic layer.
- perpendicular anisotropy multi-layers which may be used in the invention, are for example Co/Pd, Co/Ni and Cu/Ni.
- FIG. 5 shows that one may obtain a structure with magnetisation perpendicular to the plane, which combines two multi-layers with different coerciveness.
- the increase in the coerciveness of one of the multi-layers is obtained by coupling the magnetisation of said multi-layer to an adjacent antiferromagnetic layer (for example, NiO (case of FIG. 5 ), PtMn, PdPtMn or FeMn).
- an adjacent antiferromagnetic layer for example, NiO (case of FIG. 5 ), PtMn, PdPtMn or FeMn.
- the same result may be obtained by combining a multi-layer of Co/Pt to an alloy of FePt.
- each of the abovementioned materials has its own variation of coercive field as a function of the temperature.
- FIG. 6 shows, for example, the variations in the Hr reversal field (in Oe) of a multi-layer (Co 0.6 nm/Pt 1.4 nm) as a function of the temperature T (in ° C.) for a “full wafer” wafer, of macroscopic lateral dimension (curve I), and in arrays of pads of submicronic dimensions (curve II).
- the Hr reversal field decreases rapidly with the temperature and virtually cancels itself out at a temperature Tc of around 200° C.
- the reversal field decreases less rapidly, in other words cancels out at a temperature greater than 200° C. Similarly, in the alloy FePt, the reversal field cancels out around 500° C.
- a magnetic tunnel junction that combines a multi-layer, formed of alternating layers of Co and layers of Pt, with a FePt alloy electrode, one forms a structure according to the invention.
- a current impulse By sending a current impulse through the junction, one raises the temperature of said junction up to around 200° C.
- FIG. 7 illustrates an example of forming a series of several storage elements from tunnel junctions with magnetisation perpendicular to the plane according to the present invention.
- Said junctions 52 a, 52 b, 52 c and 52 d each comprise a reference layer 54 , a storage layer 56 and, between these, an insulating or semiconductive layer 58 .
- Said junctions 52 a, 52 b, 52 c and 52 d are placed between the switching transistors 60 a, 60 b, 60 c and 60 d and a conductive line 62 .
- upper conductive lines such as the lines 64 , 66 and 68 , which are located on either side of the junctions.
- junction 52 b For the writing of a storage element, for example that which comprises the junction 52 b, said junction is heated above the blocking temperature of the storage layer but below the blocking temperature of the reference layer by sending an impulse through the junction.
- the transistors are put in the blocked state except for the transistor 60 b combined with the junction 52 b, which is put in the passing state.
- the two upper conductive lines 64 and 66 located on either side of the junction to address 52 b are supplied by substantially opposite currents to create two magnetic fields 70 and 72 substantially perpendicular to the plane, which add themselves to the level of the junction to be addressed. Said fields serve to polarise the magnetisation of the storage layer during its cooling below its blocking temperature.
- the magnetisation of the storage layer may take here two states (binary storage).
- a second method for achieving the switching during the cooling consists in injecting a current of electrons with polarised spin through the storage layer.
- a structure that makes it possible to carry out this operation is shown in FIG. 8 .
- FIG. 8 shows a stack 74 placed between an upper conductive line 76 and a switching transistor 78 .
- the stack comprises, going from the line 76 to the transistor 78 , a layer 80 in PtMn, a reference layer 82 , an alumina layer 84 , a storage layer 86 , a copper layer 88 , a layer 90 called “polarising” and a layer 92 in PtMn.
- the storage layer 86 here comprises a material with perpendicular magnetisation in which the reversal field cancels out around 200° C. such as, for example, a multi-layer (Co/Pt).
- the reference layer 82 comprises a material in which the reversal field and the magnetisation remain significant at 200° C. such as, for example, FePt.
- the magnetisation of the second magnetic layer of FePt forming the polarising layer 90 remains significant at 200° C.
- the principle of magnetic switching is as follows: one applies a current impulse either from the top to the bottom or from the bottom to the top through the tunnel junction.
- Said current impulse has a specific profile: it shows its maximum value in a time of around 1 ns to several nanoseconds then drops again progressively to zero in several nanoseconds.
- Said current impulse has the effect, in a first phase, of heating the junction then, in a second phase, during the decrease of the current, in other words during the cooling of the junction, of orientating the magnetisation in a specific direction.
- electrons with spin polarised “towards the bottom” are injected into the multi-layer of Co/Pt.
- the electrons that are going to cross the alumina barrier 84 by tunnel effect are preferentially electrons in which the spin is parallel to the magnetisation of the layer 82 of FePt and are thus electrons with spin “towards the top”.
- the interest of the additional polarising layer 90 is to make it possible to cumulate the current of electrons with polarised spin coming from the other layer 82 of the tunnel junction and the current of electrons with polarised spin coming from the polarising layer 90 .
- This structure of the storage element is particularly simple since it only requires, in addition to the addressing transistor and the tunnel junction, one level of conductive line.
- the magnetisations of the two layers F 1 and F 2 are parallel to the plane of the layers or, more precisely, to the interfaces of said layers.
- the magnetic materials making up the magnetic tunnel junction must be chosen in such a way that one has a faster thermal decrease of its coercive field than the other.
- the material of the reference layer F 2 may be an alloy based on Co, Fe, Ni (for example COCo 90 Fe 10 ) and its magnetisation may be pinned by an exchange interaction with an antiferromagnetic material with high blocking temperature (a lot higher than 200° C.) such as PtMn.
- the material of layer F 1 may be formed of art alloy in which the Curie temperature is reduced in volume to enable the switch over of its magnetisation to be facilitated when said material is heated to around 200° C.
- An advantageous means of obtaining this property consists in coupling the magmetisation of the storage layer to an antiferromagnetic layer with low blocking temperature (for example Fe 50 Mn 50 or Ir 20 Mn 80 in which the blocking temperature is below 200° C. where as the magnetisation of the other magnetic layer (the reference layer) is coupled to an antiferromagnetic layer with high blocking temperature, for example PtMn in which the blocking temperature is greater than 280° C.
- low blocking temperature for example Fe 50 Mn 50 or Ir 20 Mn 80 in which the blocking temperature is below 200° C.
- FIG. 9 shows an example of tunnel junction with planar magnetisation that may be used in the present invention.
- the reference layer 94 in Co 90 Fe 10 is pinned by interaction with an antiferromagnetic layer 96 with high blocking temperature (well above 200° C.), for example in PtMn or NiMn.
- the storage layer 98 in Ni 80 Fe 20 is coupled to an antiferromagnetic layer 100 with low blocking temperature (between 100° C. and 200° C.), for example in Fe 50 Mn 50 or in Ir 20 Mn 80 and said layer 98 is separated from the layer 94 by a tunnel barrier layer 102 in Al 2 O 3 .
- one way of lowering the blocking temperature of the antiferromagnetic layer coupled to the storage layer may be to reduce its thickness. Indeed, it is known that the thinner an antiferromagnetic layer, the lower its blocking temperature.
- the writing of the information is carried out as previously by sending a current impulse through the junction, which has the effect of heating the material of the storage layer (comprising the adjacent antiferromagnetic layer) to a temperature enabling the reversal of the magnetisation of said layer, whereas the reference layer remains at a sufficiently low temperature for its magnetisation to remain fixed.
- FIG. 10 shows an example of forming a storage element from a tunnel junction with planar magnetisation according to the present invention.
- the junction is heated above the blocking temperature of the storage layer 98 but below the blocking temperature of the reference layer 94 , by sending a current impulse through the junction, said impulse going along the conductive line 104 to the transistor 106 , which is then made passing.
- the upper conductive line 108 serves to create the magnetic field 110 , which polarises the magnetisation of the storage layer 98 in the desired direction during its cooling. Said magnetisation of the storage layer can only take here two states (binary storage).
- the line 108 is not obligatory: its function may advantageously be performed by the line 104 . In this case, one also has to verify that the magnetisation directions of the layers are orthogonal to the direction of the line 104 .
- This device in which the storage layer is coupled to an antiferromagnetic layer in which the blocking temperature is lower than the reference layer, has two major advantages.
- the magnetic storage layer is coupled to an antiferromagnetic layer in which the anisotropy is relatively high at ambient temperature but decreases rapidly when one approaches the blocking temperature of said layer (around 200° C.), then the superparamagnetic limit is pushed back.
- the energy barrier to overcome to reverse the magnetisation of the storage layer at ambient temperature is now equal to A(K f E f +K a E a ) where A designates the common area of the magnetic storage layer and the antiferromagnetic layer, E f and E a respectively designate the thicknesses of said storage and antiferromagnetic layers and K f and K a respectively designate their magnetic anisotropies.
- K a E a may be 100 times higher at ambient temperature than the term K f E f . This implies that the area of the junction may be 100 times smaller while at the same time remaining above the superparamagnetic limit. Consequently, this makes it possible to attain much high higher integration densities.
- a storage element has two possible states that correspond to the two magnetic configurations parallel and antiparallel, said configurations corresponding respectively to parallel and antiparallel alignments of the magnetisation of the storage layer in relation to that of the reference layer.
- bistable type systems are obtained by giving to the storage layer a magnetic anisotropy of magnetocrystalline or shape (storage element, for example, of elliptic shape) origin, with an easy magnetisation axis parallel to the magnetisation of the reference layer.
- the magnetisation of the storage layer may advantageously be orientated in any intermediate direction between the direction parallel and the direction antiparallel to the magnetisation of the reference layer.
- Said lines make it possible to generate magnetic fields along two perpendicular directions. By playing on the relative intensity of the current flowing in the two lines, one can generate a magnetic field in any direction to in the plane of the storage layer.
- FIG. 11 shows an example of forming a storage element from a tunnel junction with planar magnetisation according to the present invention.
- the magnetic tunnel junction is heated above the blocking temperature of the storage layer 112 but below the blocking temperature of the reference layer 114 , by sending a current impulse through the junction.
- the upper 116 and lower 118 conductive lines serve to create magnetic fields 120 and 122 along two perpendicular directions in the plane, which makes it possible to polarise the magnetisation of the storage layer 112 in any desired direction in the plane of the junction, during its cooling.
- the line 116 is not indispensable: it may be replaced by the line 124 .
- the magnetisation of the storage layer may therefore take here more than two states (multilevel storage).
- the reference 123 designates the tunnel barrier layer. Also shown are the conductive line 124 and the switching transistor 126 between which the junction is placed and which makes it possible to make a current flow through said junction when the transistor operates in saturated mode.
- the magnetisation of the magnetic layer creating the polarisation of the spin of the electrons injected must be substantially perpendicular to the magnetic field generated by the current flowing in the conductive line.
- the writing is carried out by measuring the level of resistance of the junction.
- ⁇ R/R par (R ant ⁇ R par )/R par is the total magnetoresistance amplitude.
- the reading of the level of intermediate resistance between the parallel resistance R par and the antiparallel resistance R ant therefore makes it possible to determine the direction of the magnetisation of the storage layer.
- Said thin layers may be magnetic layers, intended to reinforce the polarisation of the electrons in the neighbourhood of the interface with the tunnel barrier layer, or non magnetic layers making it possible to form quantum wells depending on the spin in the neighbourhood of the tunnel barrier layer or to increase the magnetic decoupling of two magnetic layers on either side of the tunnel junction.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Semiconductor Memories (AREA)
- Thin Magnetic Films (AREA)
Abstract
Magnetic tunnel junction magnetic device (16) for writing and reading uses a reference layer (20c) and a storage layer (20a) separated by a semiconductor or insulating layer (20b), which can include an antiferromagnetic layer adjacent the storage layer. The blocking temperature of the magnetisation magnetization of the storage layer is less than that of the reference layer. The storage layer is heated (22, 24) above the blocking temperature of its magnetisation magnetization. A magnetic field (34) or a magnetic torque created by the injection of spin polarized electrons is applied (26) to it orientating its magnetization with respect to that of the reference layer without modifying the orientation of the reference layer.
Description
This is a reissue application of U.S. application Ser. No. 10/495,637, now U.S. Pat. No. 6,950,335.
This application claims priority based on International Patent Application No. PCT/FR02/03896, entitled “Magnetic Device with Magnetic Tunnel Junction, Memory Array and Read/Write Methods Using Same” by Bernard Dieny and Olivier Redon, which claims priority of French Application No. 01 14840, filed on Nov. 16, 2001, and which was not published in English.
The present invention concerns a magnetic tunnel junction device and a memory using said device.
The invention further concerns a thermomagnetic writing method in said device and a reading method of said device.
The invention finds an application in electronics and, in particular, in the formation of storage elements and MRAM (Magnetic Random Access Memory) type memories or direct (or random) access magnetic memory.
There has been renewed interest in MRAM magnetic memories with the development of MTJ (magnetic tunnel junctions) that have high magnetoresistance at ambient temperature.
With regard to magnetic memories using magnetic tunnel junctions, one should refer, for example, to the following documents:
- (1) U.S. Pat. No. 5,640,343 A (Gallagher et al.)
- (2) S. S. P. Parking et al., J. Appl. Phys., vol. 85, no 8, 1999, pp. 5828-5833.
Appended FIGS. 1A and 1B schematically illustrate the structure and the function of a known magnetic tunnel junction.
The junction bears the reference 2. It is a stack comprising an oxide layer 3b sandwiched between two magnetic layers. This system functions like a spin gate, with the difference that the current flows perpendicularly to the planes of the layers.
One 3a of the magnetic layers is called “free” or “storage” since one can orient its magnetisation in the desired direction by means of an external magnetic field (two directional arrow); the other magnetic layer 3c is called “pinned” or “reference” since its magnetisation direction is fixed by exchange coupling with an antiferromagnetic layer (single directional arrow).
When the magnetisations of the magnetic layers are antiparallel, the resistance of the junction is high; when the magnetisations are parallel, said resistance becomes low. The relative variation of resistance between these two states can attain 40% through an appropriate choice of materials for the layers in the slack and/or thermal treatments of said materials.
The junction 2 is placed between a switching transistor 4 and a current supply line 6 forming an upper conductive line. A current I1 flowing in said line produces a first magnetic field 7. A conductor 8 forming a lower conductive line, orthogonal to the current supply line 6 enables, by making a current I2 flow in said line, a second magnetic field 9 to be produced.
In the “writing” mode (FIG. 1A ), the transistor 4 is placed in blocked mode and therefore no current passes through this transistor. One circulates current impulses in the current supply line 6 and in the conductor 8. The junction 2 is therefore subjected to two orthogonal magnetic fields. One is applied along the axis of difficult magnetisation of the free layer 3a, in order to reduce its reversal field, whereas the other is applied along its easy axis in order to provoke the reversal of the magnetisation and thus the writing of the storage element.
In principle, only the storage element placed at the intersection of the two lines 6 and 8 is capable of reversing itself, since each magnetic field taken individually is not sufficiently strong to provoke a switch over of the magnetisation.
In the “reading” mode (FIG. 1B , the transistor is place in saturated regime (in other words, the current crossing this transistor is maximum) by sending a positive current impulse in the gate of the transistor. The current 13 sent in the line 6 only crosses the storage element in which the transistor is placed in saturated mode.
This current makes it possible to measure the resistance of the junction of this storage element. In relation to a reference storage element, the state of the storage element (“0” or “1”) may thus be determined: one then knows if the magnetisation of the storage layer 3a is parallel or antiparallel to that of the reference layer 3c.
This type of writing mechanism has disadvantages, in particular, in a tunnel junction array:
1) Since the reversal of the magnetisation of the free layer of a junction is produced under the effect of exterior fields an since the reversal fields are statistically distributed, it is not impossible to accidentally reverse certain neighbouring junctions simply by the effect of the magnetic field produced along a lower or upper conductive line. Since, for high density memories, the size of the storage elements is distinctly submicronic, the number of addressing errors increases.
2) The reduction in the size of the storage elements leads to an increase in the value of the individual reversal field; a higher current is then necessary to write the storage elements, which tends to increase the electricity consumption.
3) The writing mode uses two current lines at 90°, which limits the integration density.
The aim of the present invention is to overcome the above-mentioned disadvantages.
According to one aspect of the present invention, one proposes a magnetic tunnel junction magnetic device that may be used in a MRAM and in which the writing mechanism is insensitive to the distribution of the reversal fields in order to eliminate the addressing errors and to obtain good reproducibility in the writing of information.
According to another aspect of the invention, one proposes a magnetic tunnel junction magnetic device in which the energy consumption is low.
According to another aspect, one proposes a magnetic tunnel junction magnetic device that enables a multi-level storage of information. This has the advantage, in a memory according to the invention, of increasing the storage capacity for a same number of storage elements.
A further aim of the present invention is to improve magnetic memories by reducing the size of their storage elements, while at the same time keeping the information stable at ambient temperature, as well as the level of writing errors of said memories.
In the invention, one uses a known property of a magnetic material, according to which the reversal field of the magnetisation is very low when one increases the temperature of said material beyond the blocking temperature of the magnetisation of said material.
More precisely, the present invention concerns a magnetic device comprising a magnetic tunnel junction that comprises:
a first magnetic layer forming a reference layer and having a magnetisation of fixed direction,
a second magnetic layer forming a storage layer and having a magnetisation of variable direction, and
a third layer that is semiconductive or electrically insulating and which separates the first layer from the second layer,
said device being characterised in that the blocking temperature of the magnetisation of the storage layer is lower than the blocking temperature of the magnetisation of the reference layer and in that the device further comprises:
means for heating the storage layer to a temperature higher than the blocking temperature of the magnetisation of said storage layer, said means of heating the storage layer being means provided to make an electric current flow through the magnetic tunnel junction, and
means for applying, to said storage layer, a magnetic field capable of orientating the magnetisation of said storage layer in relation to the magnetisation of the reference layer, without modifying the orientation of said reference layer.
According to a preferred embodiment of the invention, the blocking temperatures of the storage and reference layers have values greater than the value of the operating temperature of the device outside of heating of the tunnel junction (one knows that the device heats up when it operates).
According to a first specific embodiment of the device of the invention, the magnetisation of each of the storage and reference layers is substantially perpendicular to the plane of said layers.
In this case, the storage layer may be a mono-layer in Co—Pt or Co—Pd alloy or a multi-layer formed by a stack of Co layers alternating with layers of Pt or Pd in such a way that the coercive field of the storage layer rapidly decreases when the temperature increases.
As a variant, the storage layer may be a mono-layer in cobalt rich alloy with iron or nickel or chromium and platinum or palladium, or a multi-layer formed by a stack of layers of an alloy rich in cobalt with iron or nickel or chromium, alternating with layers of Pt or Pd in such a way that the coercive field of the storage layer rapidly decreases when the temperature increases.
According to a second specific embodiment, the magnetisation of each of the storage and reference layers is substantially parallel to the plane of said layers.
The device of the invention may further comprise a first antiferromagnetic layer combined with the reference layer.
Preferably, the blocking temperature of the magnetisation of said first antiferromagnetic layer is higher than the blocking temperature of the storage layer.
According to a specific embodiment of the invention, the reference layer is a multi-layer comprising two magnetic layers and an intermediate layer in Ru or Re or Ir or Rh, the two magnetic layers being separated by the intermediate layer and coupled in an antiparallel manner by interaction through said intermediate layer.
According to a preferred embodiment of the device of the invention, said device further comprises a second antiferromagnetic layer coupled to the storage layer by exchange anisotropy.
Preferably, the blocking temperature of the magnetisation of said second antiferromagnetic layer is lower than the blocking temperature of the reference layer.
The means of applying the magnetic field torque to the magnetization of the storage layer may comprise means of injecting, in said storage layer, a current of electrons in which the spin is polarised.
The present invention also concerns a memory comprising a matrix of storage elements that are addressable by addressing lines and columns, said memory being characterised in that each storage element comprises:
a magnetic device according to the invention, and
a means of current switching placed in series with said magnetic device,
each magnetic device being linked to an addressing line and each means of switching being linked to an addressing column.
The present invention also concerns a method for writing information in a magnetic device according to the invention, in which:
one heats the storage layer to a temperature higher than the blocking temperature of the magnetisation of said storage layer, and
during the cooling of the storage layer, one applies to said storage layer a magnetic field capable of orientating the magnetisation of said storage layer in relation to the magnetisation of the reference layer, without modifying the orientation of said reference layer.
Preferably, the value, seen by the reference layer, of the magnetic field applied during the storage, is less than the value that the reversal magnetic field of the magnetisation of the reference layer reaches at the maximum temperature attained by said layer during the heating of the junction.
According to a preferred embodiment of the writing method of the invention, the storage layer is coupled to an antiferromagnetic layer by exchange anisotropy and one heats the storage layer and said antiferromagnetic layer to a temperature higher than the blocking temperatures of the magnetisation of said layers and, during the cooling of the antiferromagnetic layer, one orientates the magnetisation of the storage layer in any direction whatsoever predefined by the direction of magnetisation of the magnetic field applied during the cooling,
The present invention further concerns a method for reading information memorised in a device according to the invention, in which
one determines the resistance value of the magnetic tunnel junction, and
one deduces the orientation of the magnetisation of the storage layer from said resistance value.
The present invention will be more fully understood on reading the description of embodiments that follows, given by way of illustration and in nowise limitative, and by referring to the appended drawings, in which:
In an example of the present invention, a magnetic memory comprises a matrix of magnetic devices according to the invention. Each of said devices, also called “storage elements”, comprises a magnetic tunnel junction of the form F1/O/F2 where F1 and F2 respectively designate the magnetic storage layer, also called the “storage magnetic electrode”, and the magnetic reference layer, also called “reference magnetic electrode”, and O designates the layer that is comprised between F1 and F2 and forms a tunnel barrier.
Each of the layers F1 and F2 is characterised by a reversal field of its magnetisation, said field being a function of the temperature of the material forming this layer.
In the present invention, the materials of layers F1 and F2 are chosen in such a way that the reduction in temperature of the reversal field of layer F1, designated HcF1, is a lot quicker than that of the reversal field of layer F2, designated HcF2.
Typically, one chooses the materials for layers F1 and F2 in such a way that their reversal fields are, at ambient temperature (around 20° C.), around 100 Oe (around 8000 A/m) for F1 (it is recalled that 1 Oe equals 1000/(4π) A/m) and around 600 Oe (around 48000 A/m) for F2 and, at 200° C., around 5 Oe (around 400 A/m) for F1 and 400 Oe (around 32000 A/m) for F2.
In other words, one chooses the materials for layers F1 and F2 in such a way that the blocking temperature of the magnetisation of layer F1, also called “magnetic blocking temperature” of layer F1 or, more simply, “blocking temperature” of layer F1, is significantly lower than the blocking temperature of the magnetisation of layer F2.
During the writing, the principle of the selection of a storage element then consists in provoking a very brief heating (up to a temperature Tmax, typically up to 200° C.) of said storage element, said heating having the effect of lowering the reversal field of the magnetisation of the magnetic layer F1 in which the information is stored.
Since the operating principle of the device is based on temperature variations, it appears obvious that the storage and reference layers must preferably have blocking temperatures higher than the operating temperature of the device outside of heating.
Moreover, since the aim of this device is to store information in a stable manner, it is therefore, for this reason, preferable that said layers have blocking temperatures significantly higher than the operating temperature of the device.
During the cooling of the storage element, a magnetic field of amplitude He such that
HcF1(Tmax)<He<HcF2(Tmax)
HcF1(Tmax)<He<HcF2(Tmax)
He this being typically between around 20 Oe and 60 Oe (around 1600 A/m and 4800 A/m), is applied in the direction in which one wishes to orientate the magnetisation of the storage layer F1.
The magnetisation of said storage layer F1 than orientates itself in the direction of the applied field He whereas that of the reference layer F2, also called “pinned layer”, always remains orientated in the same direction.
The heating of the junction may be controlled by sending a short current impulse (around 105 A/cm2 to 106 A/cm2 for a few nanoseconds) through the junction.
The magnetic field He is created by sending current impulses in the conductive lines situated in the planes lying above and/or below the magnetic tunnel junctions.
A second possibility of provoking the switching of the magnetisation of the storage layer during its cooling may consist in injecting in said layer a current of electrons in which the spin is polarised, according to one of the techniques detailed hereafter.
The present invention consists in this case in combining the heating of the material of the storage layer, in order to reduce the reversal field of the magnetisation of said layer, with the application of a magnetic torque to this magnetisation, during the cooling of the storage layer, by flowing a current of electrons in which the spin is polarised through the storage layer.
It is also possible to combine the switching, through application of a local field generated by sending a current in an upper or lower conductive line, with the injection of a current of electrons with polarised spin in the storage layer of the junction.
Four major advantages of the present invention may be highlighted:
1) Flawless Selection of Storage Elements:
The present invention enables much better selection of storage elements than known technologies. Indeed, let us assume that the storage elements are organised into a square array as seen in FIG. 2 , which represents the architecture of a known MRAM.
In said known memory, one distinguishes three levels of lines:
upper conductive lines 10 that serve to generate the magnetic field Hx to apply to the magnetic tunnel junctions 2 during the writing and that also serve as electrical contacts for said junctions during the reading,
lower conductive lines 12 that only serve to generate the magnetic field Hy at the moment of the writing, and
According to a known writing procedure, the writing is carried out by sending current impulses along the upper and lower conductive lines, which cross at the storage element that one wishes to address. However, if there if is a distribution of reversal field, certain storage elements situated along the lines risk reversing in an uncontrolled manner.
In the present invention, this problem is not posed. This is schematically illustrated by FIG. 3 , which shows a magnetic device 16 according to the invention, forming a storage element, or cell, of a MRAM memory according to the invention.
Said storage element comprises a magnetic tunnel junction 18, comprising a storage layer 20a, a reference layer 20c and an insulating or semiconduetive layer 20b between these layers. This junction is placed between an upper conductive line 22 and a switching transistor 24 and combined with a lower conductive line 26 that is perpendicular to the line 22.
By turning the transistor 24 of the storage element 16 to the passing state, said transistor being commanded by a control line 28, and by sending a current impulse 30 in the corresponding upper conductive line 22, said current impulse crosses the junction 18 and provokes its heating.
However, the junctions of the memory of FIG. 3 are organised in a square array as in the memory in FIG. 2 (in which the references of the elements are moreover followed, in brackets, by references of the corresponding elements of FIG. 3 ). Consequently, only one junction of the whole array will be heated by the current impulse 30, all of the others remaining at ambient temperature.
The lowering of the reversal field linked to the temperature rise (typically from 100 Oe, at 20° C., to 5 Oe, at 200° C.) is a much more significant than the distribution width of the reversal field at ambient temperature (typically 100 Oe±20 Oe).
Consequently, by sending a current impulse 32 in the lower conductive line 26, which generates a magnetic field 34 of around 10 Oe during the cooling of the addressed junction, one is sure to only switch the magnetisation of the storage layer 20a of said junction.
However, the line 26 is not indispensable for creating the magnetic field. One could quite easily use the upper line 22 (used in a first phase to provoke the heating) to generate, in a second phase, the magnetic field during the cooling.
In the case of FIG. 3 , if one eliminates the line 26, it is necessary to make sure that the directions of magnetisation of the layers is perpendicular to the current line 22 generating the magnetic field (for example, by making the device pivot by orienting the magnetization of the reference layer 20c perpendicular to line 22 and setting axis of magnetization of the layer 20a perpendicular to line 22).
The operation of the storage element 16 of FIG. 3 is therefore as follows: since the addressing transistor 24 is in the passing state, the writing is achieved by sending a current impulse through the junction 18 to heat the junction up to around 200° C. During the cooling of the junction, a current impulse is sent in the lower conductive line 26 to generate a magnetic field in the storage layer 20a, which has the effect of switching the magnetisation of said layer in the desired direction.
The reading is achieved with the transistor in the passing state by making a current flow through the junction (the current being lower than during the writing so that the heating is less), which makes it possible to measure the resistance and thus to know if the magnetisation of the storage layer 20a is parallel or antiparallel to that of the reference layer 20c.
2) Reduced Consumption:
Given the fact that the fields to be generated for the writing are a lot weaker than in the prior an (typically 10 Oe in the present invention compared to 50 Oe in the prior art), the intensity of the field impulses to send in the conductive lines is considerably reduced.
Moreover, a single impulse in the lower conductive line is necessary in the case of FIG. 3 , compared to one impulse in the lower conductive line and one impulse in the upper conductive line in the prior art.
Since the power required to provoke the heating of the storage element is a lot less than to generate field impulses of 50 Oe (typically 1 pJ to heat a magnetic tunnel junction of 150 nm×150 nm to 200° C. compared to several tens of pJ to generate a field impulse of 50 Oe along a line of 500 storage elements), it follows that the electrical consumption may be divided by 10 with the operating principle of the present invention.
3) Stability of Information for Small Dimensions:
The present invention makes it possible to use, for the storage layer, materials with high pinning energy at ambient temperature. In the prior art, this is not possible since the higher the pinning of the storage layer, the more it is necessary to supply energy to switch the magnetisation of the storage layer.
In the present invention, one lowers the pinning energy during the writing by heating the material. One may thus make it possible to have a high pinning energy at ambient temperature. This presents a considerable advantage for small dimensions. Indeed, in the prior art, the information stored in the storage layer becomes unstable in relation to the thermal fluctuations at ambient temperature.
Indeed, if K and V respectively designate the magnetic anisotropy per unit of volume (or, more generally, the pinning energy per unit of volume) and the volume of the storage layer, the information becomes unstable if KV<25 kT (where k is the Boltzmann constant and T the temperature).
For a given material, this limit is always reached at one moment or another when one reduces the size of the storage element whereas, in the present invention, one can very easily compensate the reduction in the volume by an increase in the pinning energy at ambient temperature and thus reduce the size of the storage element as far as the manufacturing method used (for example, lithography/engraving) allows.
4) Simplicity of production if one uses as switching principle a heating plus an injection of a current of electrons with polarised spin:
Indeed, there is no need, in this case, to add a level of lines for the generation of local magnetic fields. The production of a series of storage elements is simplified, which makes it possible to attain higher integration densities.
We will return later to the use, in the present invention, of a current of electrons with polarised spin.
We will now consider, in the following description, various examples of the invention.
As we have seen above, the basic structure, in the present invention, comprises two magnetic layers F1 and F2 separated by a tunnel barrier O in such a way that one may designate this structure F1/O/F2. The two magnetic layers are such that the reversal field of the magnetisation of one of these two magnetic layers (the storage layer) decreases much more quickly, when the temperature increases, than that of the other magnetic layer (the reference layer).
In a first embodiment of the invention, the magnetisations of the two layers F1 and F2 are perpendicular to the plane of the layers or, more precisely, to the interfaces of said layers.
Layers F1 and F2 may comprise a pure material, an alloy or a series of alternating layers, certain of which are magnetic.
Co layers, of hexagonal structure, have their magnetisation perpendicular to the plane of these layers if the axis c of the hexagonal lattice is perpendicular to the plane of the sample containing said layers. Alloy layers such as CoPt, FePd and FePt may also have magnetisations perpendicular to their planes. Finally, multi-layers comprising alternating layers of two different materials at least one of which is magnetic, such as for example Co 0.6 nm/Pt 1.4 nm, may also have magnetisations perpendicular to the plane.
The cobalt may easily be replaced by an alloy rich in Co (greater than 70%) with for example Fe or Ni or Cr.
An example of forming a multi-layer Co/Pt based magnetic tunnel junction, which may be used in the present invention, is shown in FIG. 4 .
More precisely, as can be seen in FIG. 4 , said magnetic tunnel junction comprises a reference layer 36 and a storage layer 38 that have a magnetisation perpendicular to the plane of said layers; the reference layer 36 comprises layers 40 in cobalt that alternate with layers 42 in platinum; similarly, the storage layer 38 comprises layers 44 in cobalt that alternate with layers 46 in platinum; the layers 36 and 38 are separated by a tunnel barrier layer 48 in alumina.
By playing on the relative thicknesses of Co and Pt, one can vary the coerciveness of the material making up each of the layers 36 and 38 as well as the variation of said coerciveness as a function of the temperature. One can also increase the blocking energy of the magnetisation of one of the layers (the reference layer 36) by coupling iL to an antiferromagnetic material 50 with high blocking temperature, such as PtMn or PtPdMn.
In this case, the adjacent ferromagnetic layer sees the value of its blocking temperature increase up to the value of that of the antiferromagnetic layer.
Other examples of perpendicular anisotropy multi-layers, which may be used in the invention, are for example Co/Pd, Co/Ni and Cu/Ni.
By way of example, FIG. 5 shows that one may obtain a structure with magnetisation perpendicular to the plane, which combines two multi-layers with different coerciveness.
We have plotted the variations in the magnetoresistance MR (in %) as a function of the applied magnetic field H (in kOe) for the structure.
NiO300/Co6/(Pt18/CO6)2/Cu30/(CO6/Pt18)2
NiO30nm/Co0.6nm/(Pt1.8nm/Co0.6nm)2/Cu3nm/(Co0.6nm/Pt1.8nm)2.
NiO300/Co6/(Pt18/CO6)2/Cu30/(CO6/Pt18)2
NiO30nm/Co0.6nm/(Pt1.8nm/Co0.6nm)2/Cu3nm/(Co0.6nm/Pt1.8nm)2.
In the case of FIG. 5 , the increase in the coerciveness of one of the multi-layers is obtained by coupling the magnetisation of said multi-layer to an adjacent antiferromagnetic layer (for example, NiO (case of FIG. 5 ), PtMn, PdPtMn or FeMn).
The same result may be obtained by combining a multi-layer of Co/Pt to an alloy of FePt.
Moreover, each of the abovementioned materials has its own variation of coercive field as a function of the temperature.
With the thicknesses of Co and Pt used, the Hr reversal field decreases rapidly with the temperature and virtually cancels itself out at a temperature Tc of around 200° C.
If one increases the thickness of Co at fixed Pt thickness, the reversal field decreases less rapidly, in other words cancels out at a temperature greater than 200° C. Similarly, in the alloy FePt, the reversal field cancels out around 500° C.
Therefore, by forming for example a magnetic tunnel junction that combines a multi-layer, formed of alternating layers of Co and layers of Pt, with a FePt alloy electrode, one forms a structure according to the invention. By sending a current impulse through the junction, one raises the temperature of said junction up to around 200° C.
One then cuts the current that is flowing through the junction and, during the cooling of said junction, one applies a weak magnetic field by means of lower or upper conductive lines 64 and 66 (see FIG. 7 ). The magnetisation of the reference layer remains unchanged whereas that of the storage layer orientates itself in the direction of the applied field during the cooling.
More precisely, FIG. 7 illustrates an example of forming a series of several storage elements from tunnel junctions with magnetisation perpendicular to the plane according to the present invention. Said junctions 52a, 52b, 52c and 52d each comprise a reference layer 54, a storage layer 56 and, between these, an insulating or semiconductive layer 58. Said junctions 52a, 52b, 52c and 52d are placed between the switching transistors 60a, 60b, 60c and 60d and a conductive line 62.
Also shown are upper conductive lines, such as the lines 64, 66 and 68, which are located on either side of the junctions.
For the writing of a storage element, for example that which comprises the junction 52b, said junction is heated above the blocking temperature of the storage layer but below the blocking temperature of the reference layer by sending an impulse through the junction.
Moreover, the transistors are put in the blocked state except for the transistor 60b combined with the junction 52b, which is put in the passing state.
The two upper conductive lines 64 and 66 located on either side of the junction to address 52b are supplied by substantially opposite currents to create two magnetic fields 70 and 72 substantially perpendicular to the plane, which add themselves to the level of the junction to be addressed. Said fields serve to polarise the magnetisation of the storage layer during its cooling below its blocking temperature. The magnetisation of the storage layer may take here two states (binary storage).
A second method for achieving the switching during the cooling consists in injecting a current of electrons with polarised spin through the storage layer. A structure that makes it possible to carry out this operation is shown in FIG. 8 .
The storage layer 86 here comprises a material with perpendicular magnetisation in which the reversal field cancels out around 200° C. such as, for example, a multi-layer (Co/Pt). The reference layer 82 comprises a material in which the reversal field and the magnetisation remain significant at 200° C. such as, for example, FePt. Similarly, the magnetisation of the second magnetic layer of FePt forming the polarising layer 90 remains significant at 200° C.
The principle of magnetic switching is as follows: one applies a current impulse either from the top to the bottom or from the bottom to the top through the tunnel junction.
Said current impulse has a specific profile: it shows its maximum value in a time of around 1 ns to several nanoseconds then drops again progressively to zero in several nanoseconds. Said current impulse has the effect, in a first phase, of heating the junction then, in a second phase, during the decrease of the current, in other words during the cooling of the junction, of orientating the magnetisation in a specific direction.
If the current flows from the top to the bottom (in other words if the electrons flow from the bottom to the top), electrons with spin polarised “towards the bottom” are injected into the multi-layer of Co/Pt. Moreover, the electrons that are going to cross the alumina barrier 84 by tunnel effect are preferentially electrons in which the spin is parallel to the magnetisation of the layer 82 of FePt and are thus electrons with spin “towards the top”.
This generates, in the multi-layer of Co/Pt, an excess of electrons towards the bottom. Said excess of electrons towards the bottom, cumulated with the injection of electrons towards the bottom from the lower polarising layer, forces the magnetisation of the multi-layer of Co/Pt to orientate itself towards the bottom during its cooling.
On the other hand, if the current flows from the bottom to the top (in other words, if the electrons flow from the top to the bottom), there is an accumulation of electrons “towards the top” in the layer of Co/Pt, which has the effect of forcing the magnetisation of said layer to orientate itself towards the top during its cooling.
We should point out that this magnetic switching principle could also operate without the lower polarising layer but the shape of the current impulse would then be more difficult to adjust to find a good balance between a sufficient reduction of current so that the temperature of the junction drops sufficiently and a sufficient flow of current to be able to polarise the magnetisation of the storage layer during its cooling.
The interest of the additional polarising layer 90 is to make it possible to cumulate the current of electrons with polarised spin coming from the other layer 82 of the tunnel junction and the current of electrons with polarised spin coming from the polarising layer 90.
This structure of the storage element is particularly simple since it only requires, in addition to the addressing transistor and the tunnel junction, one level of conductive line.
In a second embodiment of the invention, the magnetisations of the two layers F1 and F2 are parallel to the plane of the layers or, more precisely, to the interfaces of said layers.
As previously, the magnetic materials making up the magnetic tunnel junction must be chosen in such a way that one has a faster thermal decrease of its coercive field than the other.
The material of the reference layer F2 may be an alloy based on Co, Fe, Ni (for example COCo90Fe10) and its magnetisation may be pinned by an exchange interaction with an antiferromagnetic material with high blocking temperature (a lot higher than 200° C.) such as PtMn.
The material of layer F1 may be formed of art alloy in which the Curie temperature is reduced in volume to enable the switch over of its magnetisation to be facilitated when said material is heated to around 200° C.
An advantageous means of obtaining this property consists in coupling the magmetisation of the storage layer to an antiferromagnetic layer with low blocking temperature (for example Fe50Mn50 or Ir20Mn80 in which the blocking temperature is below 200° C. where as the magnetisation of the other magnetic layer (the reference layer) is coupled to an antiferromagnetic layer with high blocking temperature, for example PtMn in which the blocking temperature is greater than 280° C.
This is schematically illustrated in FIG. 9 , which shows an example of tunnel junction with planar magnetisation that may be used in the present invention.
The reference layer 94 in Co90Fe10 is pinned by interaction with an antiferromagnetic layer 96 with high blocking temperature (well above 200° C.), for example in PtMn or NiMn.
The storage layer 98 in Ni80Fe20 is coupled to an antiferromagnetic layer 100 with low blocking temperature (between 100° C. and 200° C.), for example in Fe50Mn50 or in Ir20Mn80 and said layer 98 is separated from the layer 94 by a tunnel barrier layer 102 in Al2O3.
It should be noted that one way of lowering the blocking temperature of the antiferromagnetic layer coupled to the storage layer may be to reduce its thickness. Indeed, it is known that the thinner an antiferromagnetic layer, the lower its blocking temperature.
The writing of the information is carried out as previously by sending a current impulse through the junction, which has the effect of heating the material of the storage layer (comprising the adjacent antiferromagnetic layer) to a temperature enabling the reversal of the magnetisation of said layer, whereas the reference layer remains at a sufficiently low temperature for its magnetisation to remain fixed.
This is schematically illustrated in FIG. 10 , which shows an example of forming a storage element from a tunnel junction with planar magnetisation according to the present invention.
For the writing, the junction is heated above the blocking temperature of the storage layer 98 but below the blocking temperature of the reference layer 94, by sending a current impulse through the junction, said impulse going along the conductive line 104 to the transistor 106, which is then made passing.
The upper conductive line 108 serves to create the magnetic field 110, which polarises the magnetisation of the storage layer 98 in the desired direction during its cooling. Said magnetisation of the storage layer can only take here two states (binary storage).
For the reasons already given above with regard to other examples, the line 108 is not obligatory: its function may advantageously be performed by the line 104. In this case, one also has to verify that the magnetisation directions of the layers are orthogonal to the direction of the line 104.
This device, in which the storage layer is coupled to an antiferromagnetic layer in which the blocking temperature is lower than the reference layer, has two major advantages.
1) The superparamagnetic stability limit of the storage layer is pushed back in such a way that one can form storage elements of smaller size using this technique.
Indeed, a problem that always appears in the storage of magnetic information in storage elements of small size (submicronic scale) is that of the magnetisation stability vis-à-vis thermal fluctuations (superparamagnetic limit).
If K designates the magnetic anisotropy of the material and V the volume of the magnetic storage layer, the characteristic magnetisation reversal time by going above the energy barrier of height KV is τ=τ0exp(KV/(kT)) where τ0 is a characteristic test time of around 10−9 seconds, k the Boltzmann constant and T the temperature.
In order for the information that one writes in the storage layer to remain stable for at least 10 years, the magnetisation itself must remain stable for this period. Consequently, it is necessary for KV/kT>Log (10 years/10−9 s), in other words: KV>40 kT.
This imposes a minimum limit to the volume of the storage layer and thus its lateral dimension, in other words a minimum limit to the dimension of the storage element.
On the other hand, if the magnetic storage layer is coupled to an antiferromagnetic layer in which the anisotropy is relatively high at ambient temperature but decreases rapidly when one approaches the blocking temperature of said layer (around 200° C.), then the superparamagnetic limit is pushed back.
Indeed, the energy barrier to overcome to reverse the magnetisation of the storage layer at ambient temperature is now equal to A(KfEf+KaEa) where A designates the common area of the magnetic storage layer and the antiferromagnetic layer, Ef and Ea respectively designate the thicknesses of said storage and antiferromagnetic layers and Kf and Ka respectively designate their magnetic anisotropies. aP Since the anisotropy Ka of the antiferromagnetic material is normally a lot lower higher than that (Kf) of the ferromagnetic layer at ambient temperature, it appears that the condition of stability A(KfEf+KaEa)>40 kT could be satisfied for much smaller dimensions than if the magnetic storage layer was alone.
Typically, the term KaEa may be 100 times higher at ambient temperature than the term KfEf. This implies that the area of the junction may be 100 times smaller while at the same time remaining above the superparamagnetic limit. Consequently, this makes it possible to attain much high higher integration densities.
It should be pointed out that it is also possible to use this coupling of the storage layer to an antiferromagnetic layer at low Neel temperature in the case previously described of magnetic layers with magnetisation perpendicular to the plane. Here again, the superparamagnetic limit will be pushed back towards the smallest dimensions at ambient temperature.
2) The second very important advantage resulting from the use of a storage layer coupled to an antiferromagnetic layer is to be able to achieve a multilevel storage of the information.
Indeed, with the junctions of the prior art, a storage element has two possible states that correspond to the two magnetic configurations parallel and antiparallel, said configurations corresponding respectively to parallel and antiparallel alignments of the magnetisation of the storage layer in relation to that of the reference layer.
These bistable type systems are obtained by giving to the storage layer a magnetic anisotropy of magnetocrystalline or shape (storage element, for example, of elliptic shape) origin, with an easy magnetisation axis parallel to the magnetisation of the reference layer.
In the present invention, the magnetisation of the storage layer may advantageously be orientated in any intermediate direction between the direction parallel and the direction antiparallel to the magnetisation of the reference layer.
To achieve this, it is sufficient to heat the storage layer and the adjacent antiferromagnetic layer above the blocking temperature of said layer, by sending a current impulse through the junction, then orientating the magnetisation of the storage layer in the desired direction during the cooling of the antiferromagnetic layer.
In order to give the desired orientation to the magnetisation of the storage layer, it is necessary to apply a local magnetic field to said layer in the desired direction. To achieve this, two possibilities exist:
1) One may use an architecture in which the magnetic switching is achieved by sending current impulses in the perpendicular conductive lines, which are respectively situated above and below said storage element.
Said lines make it possible to generate magnetic fields along two perpendicular directions. By playing on the relative intensity of the current flowing in the two lines, one can generate a magnetic field in any direction to in the plane of the storage layer.
This is illustrated schematically in FIG. 11 , which shows an example of forming a storage element from a tunnel junction with planar magnetisation according to the present invention.
For the writing, the magnetic tunnel junction is heated above the blocking temperature of the storage layer 112 but below the blocking temperature of the reference layer 114, by sending a current impulse through the junction.
The upper 116 and lower 118 conductive lines serve to create magnetic fields 120 and 122 along two perpendicular directions in the plane, which makes it possible to polarise the magnetisation of the storage layer 112 in any desired direction in the plane of the junction, during its cooling.
As we have already explained above with regard to FIG. 10 , the line 116 is not indispensable: it may be replaced by the line 124.
The magnetisation of the storage layer may therefore take here more than two states (multilevel storage).
In FIG. 11 , the reference 123 designates the tunnel barrier layer. Also shown are the conductive line 124 and the switching transistor 126 between which the junction is placed and which makes it possible to make a current flow through said junction when the transistor operates in saturated mode.
2) One can also use the combination of a magnetic field created as previously, by making a current flow in a conductive line situated above or below the tunnel junction, with the magnetic torque exerted by the injection of a current of electrons with polarised spin through the tunnel junction, in the magnetic storage layer.
In this case, the magnetisation of the magnetic layer creating the polarisation of the spin of the electrons injected must be substantially perpendicular to the magnetic field generated by the current flowing in the conductive line.
It is also important in this case to ensure that the current density necessary for orientating the storage layer in the desired direction is substantially lower than that which is necessary for the heating of the junction in such a way that the junction is indeed in a cooling phase below the blocking temperature of the antiferromagnetic layer coupled to the storage layer during the writing process.
The writing is carried out by measuring the level of resistance of the junction.
Indeed, the resistance varies according to the law
R=Rpar[1+(ΔR/Rpar)(1−cos(θs−θp))/2]
where θs and θp respectively represent the angles marking respectively the magnetisations of the storage layer and the pinned layer, or reference layer, in the plane of the junction.
R=Rpar[1+(ΔR/Rpar)(1−cos(θs−θp))/2]
where θs and θp respectively represent the angles marking respectively the magnetisations of the storage layer and the pinned layer, or reference layer, in the plane of the junction.
ΔR/Rpar=(Rant−Rpar)/Rpar is the total magnetoresistance amplitude.
The reading of the level of intermediate resistance between the parallel resistance Rpar and the antiparallel resistance Rant therefore makes it possible to determine the direction of the magnetisation of the storage layer.
In the structures described previously, it is possible to insert thin layers of another material at the interface between the magnetic layer and the tunnel barrier layer.
Said thin layers may be magnetic layers, intended to reinforce the polarisation of the electrons in the neighbourhood of the interface with the tunnel barrier layer, or non magnetic layers making it possible to form quantum wells depending on the spin in the neighbourhood of the tunnel barrier layer or to increase the magnetic decoupling of two magnetic layers on either side of the tunnel junction.
Claims (40)
1. Magnetic A magnetic device comprising a magnetic tunnel junction that comprises:
a first magnetic layer forming defining a reference layer and having a magnetisation magnetization of fixed direction,
a second magnetic layer forming defining a storage layer and having a magnetisation magnetization of variable direction, and
a third layer defining a tunnel barrier that is semiconductive or electrically insulating and which separate's the first layer from the second layer,
wherein the first and second magnetic layers have respective blocking temperatures and wherein the blocking temperature of the magnetisation of the storage layer is lower than the blocking temperature of the magnetisation of the reference layer and in that, wherein the device further comprises:
means for heating the storage layer to a temperature higher than the blocking temperature of the magnetisation of said storage layer, said means for heating the storage layer being means provided to make generating an electric current flow through the magnetic tunnel junction, wherein the storage layer is heated to a temperature higher than the blocking temperature of the storage layer, and
means for applying, to said the storage layer, a magnetic field capable of orientating the magnetisation magnetization of said the storage layer with respect to the magnetisation magnetization of the reference layer, without modifying the orientation of said the magnetization of the reference layer.
2. Device The device according to claim 1 , in which wherein the blocking temperatures of the storage and reference layers have values greater than the value of the operating temperature of the device outside of heating of the tunnel junction.
3. Device The device according to claim 1 , in which wherein the magnetisation magnetization of each of the storage and reference layers is substantially perpendicular to the plane of said the storage and reference layers.
4. Device The device according to claim 3 , in which wherein the storage layer is comprises a Co—Pt or Co—Pd alloy mono-layer or a multi-layer formed by a stack of layers of Co alternating with layers of Pt or Pd in, such a way that the resulting coercive field of the storage layer rapidly decreases when with increasing the temperature increases.
5. Device The device according to claim 3 , in which wherein the storage layer is comprises a mono-layer in of a cobalt rich alloy with iron or nickel or chromium and platinum or palladium, or a multi-layer formed by a stack of cobalt rich layers with iron or nickel or chromium, alternating with layers of Pt or Pd in such a way that, such that the resulting coercive field of the storage layer rapidly decreases when the with increasing temperature increases.
6. Device The device according to claim 1 , in which wherein the magnetisation magnetization of each of the storage and reference layers is substantially parallel to the plane of said the storage and reference layers.
7. Device The device according to claim 1 , further comprising a first an antiferromagnetic layer combined magnetically coupled with the reference layer, wherein the antiferromagnetic layer comprises PtMn alloy or a PtPdMn alloy.
8. Device The device according to claim 7 , in which wherein the blocking temperature of the magnetisation of said first the antiferromagnetic layer is higher than the blocking temperature of the storage layer.
9. Device The device according to claim 1 , in which wherein the reference layer is a multi-layer comprising two magnetic layers and an intermediate layer in of Ru or Re or Ir or Rh, wherein the two magnetic layers being are separated by the intermediate layer and coupled in an antiparallel maimer manner by interaction through said the intermediate layer.
10. Device The device according to claim 1 , further comprising a second anti ferromagnetic an antiferromagnetic layer coupled to the storage layer by exchange anisotropy.
11. Device The device according to claim 10 , in which wherein the blocking temperature of the magnetisation of said second antiferromagnetic layer is lower than the blocking temperature of the reference layer.
12. Device The device according to claim 1 , in which wherein the means for applying a magnetic field to the storage layer comprise means of injecting, in said storage layer, a current of electrons in which the spin is polarised polarized.
13. Memory A memory comprising a matrix of storage elements that are addressable by addressing lines and columns, wherein each storage element comprises: a magnetic device according to claim 1 , and wherein the means for generating an electric current comprises a means of current switching placed circuit in series with said each magnetic device, wherein each magnetic device being is linked to an addressing line and each means of current switching being circuit is linked to an addressing column.
14. Method A method for writing information in a magnetic device according to claim 1 , in which: one heats comprising heating the storage layer to a temperature higher than the blocking temperature of the magnetisation of said the storage layer, and during the cooling of the storage layer, one applies applying to said the storage layer a magnetic field capable of orientating the magnetisation magnetization of said the storage layer with respect to the magnetisation magnetization of the reference layer, without modifying the orientation of said the magnetization of the reference layer.
15. Method The method according to claim 14 , in which wherein the value, seen by magnetic field strength applied at the reference layer, of the magnetic field applied during the storage, writing is less than the value that the magnetic field strength necessary for reversing the magnetisation magnetization of the reference layer takes at the maximum temperature attained by said the reference layer during the heating of the junction.
16. Method The method according to claim 14 , in which wherein the storage layer is coupled to an antiferromagnetic layer by exchange anisotropy and one heats the storage layer and said the antiferromagnetic layer are heated to a temperature higher than the blocking temperatures of the magnetisation of said the storage and antiferromagnetic layers and, during the cooling of the antiferromagnetic layer, one orientates the magnetisation magnetization of the storage layer is oriented in any direction whatsoever predefined by the direction of magnetisation of the magnetic field applied during the cooling.
17. Method A method for reading information memorised memorized in the magnetic device according to claim 1 , in which one determines wherein the resistance value of the magnetic tunnel junction is determined, and one deduces the orientation of the magnetisation of the storage layer is ascertained from said the resistance value.
18. The device according to claim 1, wherein the storage layer comprises a single layer or multilayer structure and wherein the reference layer is in contact with an antiferromagnetic layer.
19. The device according to claim 1, wherein the reference layer comprises a single layer or a multilayer structure, and wherein the storage layer is in contact with an antiferromagnetic layer.
20. The device according to claim 3, wherein the storage layer comprises a Co/Ni or a Cu/Ni or a multilayer comprising a stack of cobalt or copper layers alternating with layers of nickel, such that a resulting coercive field of the storage layer rapidly decreases with increasing temperature, and wherein the reference layer comprises a layer of FePt or FePd alloy.
21. The method according to claim 15 further comprising injecting spin-polarized electrons into the storage layer during writing that apply a magnetic torque to the magnetization of the storage layer, wherein the magnetic torque applied at the reference layer is less than the magnetic torque for reversing the magnetization of the reference layer at the maximum temperature attained by the reference layer during the heating of the junction.
22. A magnetic device comprising:
a magnetic tunnel junction including a first magnetic layer defining a reference layer having a blocking temperature and a magnetization in a fixed direction, a second magnetic layer defining a storage layer having a blocking temperature and having a magnetization of variable direction, and a third layer defining a tunnel barrier layer intermediate to the first layer and the second layer, wherein the blocking temperature of the storage layer is lower than the blocking temperature of the reference layer; and
circuitry configured to inject a current of spin polarized electrons into the storage layer, such that the tunnel junction is heated and a magnetic torque is applied to the storage layer which orients the magnetization of the storage layer with respect to the magnetization of the reference layer, without modifying the orientation of the magnetization of the reference layer.
23. The device according to claim 22, wherein the storage layer, the reference layer, and a layer portion of the circuitry comprise layers having out-of-the-plane magnetization or in-the-plane magnetization.
24. The device according to claim 22, wherein the device comprises a storage element of a memory comprising a matrix of storage elements that are addressable by addressing lines and columns, wherein each storage element comprises a current switching circuit placed in series with each device, wherein each device is linked to one of an addressing line or addressing column, and each current switching circuit is linked to the other of the addressing line or addressing column.
25. The device according to claim 22 further comprising: a spin-polarizing layer on an opposite side of the storage layer from the reference layer; and a non-magnetic metallic layer intermediate to the spin polarizing layer and the storage layer, wherein the reference layer and the spin polarizing layer comprise oppositely magnetized layers.
26. The device according to claim 22 further comprising a conductive line above or below the magnetic tunnel junction and configured to, generate a magnetic field at the storage layer that orients the magnetization of the storage layer with respect to the magnetization of the reference layer, without modifying the magnetization of the reference layer.
27. The device according to claim 26, wherein the magnetic field, generated by the conductive line is substantially perpendicular to the direction of polarization of the spin polarized electrons injected in the storage layer.
28. A method for writing information in a magnetic device according to claim 22, comprising injecting a current impulse of spin polarized electrons through the magnetic tunnel junction during a heating phase, and in a cooling phase, applying a magnetic torque to the magnetization of the storage layer that is capable of orientating the magnetization of the storage layer with respect to the magnetization of the reference layer, without modifying the orientation of the reference layer.
29. The method according to claim 28, in which the magnetic torque applied to the magnetization of the reference layer during writing is less than the magnetic torque necessary for reversing the magnetization of the reference layer at the maximum temperature attained by the reference layer during the heating phase.
30. The method according to claim 28, in which the storage layer is coupled to an antiferromagnetic layer by exchange anisotropy and the storage layer and the antiferromagnetic layer are heated to a temperature higher than blocking temperatures of the storage and antiferromagnetic layers and, during the cooling phase, the magnetization of the storage layer is oriented in a direction corresponding to the direction of magnetization induced by the magnetic torque.
31. The method of claim 28 further comprising applying a magnetic field to the storage layer during the cooling phase to orient the magnetization of the storage layer with respect to the magnetization of the reference layer.
32. A memory cell comprising:
a tunnel junction that includes a storage layer adjacent and in contact with an antiferromagnetic layer; and
a reference layer separated from the storage layer by a tunnel barrier layer.
33. The memory cell of claim 32 further comprising circuitry configured to inject a current of spin-polarized electrons into the storage layer, wherein the spin-polarized electrons heats the storage layer and the antiferromagnetic layer to a temperature higher than blocking temperatures of the storage and antiferromagnetic layers and apply a magnetic torque to set a magnetic orientation of the storage layer with respect to a magnetic orientation of the reference layer, without modifying the magnetic orientation of the reference layer.
34. The memory cell of claim 32 further comprising circuitry configured to generate a magnetic field at the storage layer that orients the magnetization of the storage layer with respect to the magnetization of the reference layer, without modifying the magnetization of the reference layer.
35. A method for writing to a magnetic device comprising:
providing a magnetic tunnel junction including a first magnetic layer forming a reference layer and having a magnetization of set direction, a second magnetic layer forming a storage layer and having a magnetization of variable direction, and a third layer defining a tunnel barrier that separates the first and second layers, wherein the storage layer and reference layer have respective blocking temperatures, and the blocking temperature of the storage layer is lower than the blocking temperature of the reference layer;
flowing electric current through the magnetic tunnel junction and heating the storage layer to a temperature higher than the blocking temperature of the storage layer; and
applying a magnetic field to the storage layer to orient the magnetization of the storage layer with respect to the magnetization of the reference layer, without modifying the orientation of the reference layer.
36. The method of claim 35 further comprising reading information stored in the storage layer by determining a resistance value of the magnetic tunnel junction, and ascertaining the orientation of the magnetization of the storage layer from the resistance value.
37. The method of claim 35, wherein flowing electric current comprises injection a current impulse of spin polarized electrons through the magnetic tunnel junction to apply a magnetic torque to the magnetization of the storage layer capable of orientating the magnetization of the storage layer with respect to the magnetization of the reference layer without modifying the magnetization of the reference layer.
38. A method for writing to a magnetic device comprising:
providing a magnetic tunnel junction including a first magnetic layer defining a reference layer having a blocking temperature and having a magnetization of set direction, a second magnetic layer defining a storage layer having a blocking temperature and having a magnetization of variable direction, and a third layer defining a tunnel barrier intermediate to the first layer and the second layer, wherein the storage layer and the reference layer have respective blocking temperatures, and the blocking temperature of the storage layer is lower than the blocking temperature of the reference layer;
injecting a current impulse of spin polarized electrons through the magnetic tunnel junction during a first phase to heat the storage layer above the blocking temperature of the storage layer, and in a second phase, reducing the current through the tunnel junction to allow the storage layer to cool below the blocking temperature of the storage layer, wherein a magnetic torque of the spin polarized electrons is applied to the storage layer that orients the magnetization of the storage layer with respect to the magnetization of the reference layer, without modifying the orientation of the reference layer.
39. The method of claim 38, wherein the storage layer is coupled to an antiferromagnetic layer by exchange anisotropy and the storage layer and the antiferromagnetic layer are heated to a temperature higher than blocking temperatures of the storage and antiferromagnetic layers and, during the cooling of the antiferromagnetic layer, the magnetization of the storage layer is oriented in a direction corresponding to the direction of magnetization induced by the magnetic torque.
40. The method according to claim 38, further comprising applying a magnetic field to the storage layer, such that the magnetization of the storage layer is oriented with respect to the magnetization of the reference layer, without modifying the orientation of the reference layer.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0114840A FR2832542B1 (en) | 2001-11-16 | 2001-11-16 | MAGNETIC DEVICE WITH MAGNETIC TUNNEL JUNCTION, MEMORY AND METHODS OF WRITING AND READING USING THE DEVICE |
FR0114840 | 2001-11-16 | ||
PCT/FR2002/003896 WO2003043017A2 (en) | 2001-11-16 | 2002-11-14 | Magnetic device with magnetic tunnel junction, memory array and read/write methods using same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/495,637 Reissue US6950335B2 (en) | 2001-11-16 | 2002-11-14 | Magnetic tunnel junction magnetic device, memory and writing and reading methods using said device |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE42619E1 true USRE42619E1 (en) | 2011-08-16 |
Family
ID=8869468
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/861,974 Expired - Lifetime USRE42619E1 (en) | 2001-11-16 | 2002-11-14 | Magnetic tunnel junction magnetic device, memory and writing and reading methods using said device |
US10/495,637 Ceased US6950335B2 (en) | 2001-11-16 | 2002-11-14 | Magnetic tunnel junction magnetic device, memory and writing and reading methods using said device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/495,637 Ceased US6950335B2 (en) | 2001-11-16 | 2002-11-14 | Magnetic tunnel junction magnetic device, memory and writing and reading methods using said device |
Country Status (7)
Country | Link |
---|---|
US (2) | USRE42619E1 (en) |
EP (2) | EP1466329B1 (en) |
JP (2) | JP4777613B2 (en) |
AT (1) | ATE359588T1 (en) |
DE (1) | DE60219526T2 (en) |
FR (1) | FR2832542B1 (en) |
WO (1) | WO2003043017A2 (en) |
Families Citing this family (208)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2832542B1 (en) * | 2001-11-16 | 2005-05-06 | Commissariat Energie Atomique | MAGNETIC DEVICE WITH MAGNETIC TUNNEL JUNCTION, MEMORY AND METHODS OF WRITING AND READING USING THE DEVICE |
US6735111B2 (en) * | 2002-01-16 | 2004-05-11 | Micron Technology, Inc. | Magnetoresistive memory devices and assemblies |
US20060127701A1 (en) * | 2003-06-11 | 2006-06-15 | Koninklijke Phillips Electronics N.C. | Method of manufacturing a device with a magnetic layer-structure |
US6963098B2 (en) * | 2003-06-23 | 2005-11-08 | Nve Corporation | Thermally operated switch control memory cell |
US8755222B2 (en) | 2003-08-19 | 2014-06-17 | New York University | Bipolar spin-transfer switching |
US7911832B2 (en) | 2003-08-19 | 2011-03-22 | New York University | High speed low power magnetic devices based on current induced spin-momentum transfer |
KR100835275B1 (en) * | 2004-08-12 | 2008-06-05 | 삼성전자주식회사 | Methods of operating a magnetic random access memory device using a spin injection mechanism |
JP2005109263A (en) | 2003-09-30 | 2005-04-21 | Toshiba Corp | Magnetic element and magnetic memory |
US20060281258A1 (en) * | 2004-10-06 | 2006-12-14 | Bernard Dieny | Magnetic tunnel junction device and writing/reading method for said device |
FR2860910B1 (en) * | 2003-10-10 | 2006-02-10 | Commissariat Energie Atomique | MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD OF WRITING / READING SUCH A DEVICE |
US7522446B2 (en) * | 2003-10-31 | 2009-04-21 | Samsung Electronics Co., Ltd. | Heating MRAM cells to ease state switching |
JP2005150482A (en) * | 2003-11-18 | 2005-06-09 | Sony Corp | Magnetoresistance effect element and magnetic memory device |
US7602000B2 (en) * | 2003-11-19 | 2009-10-13 | International Business Machines Corporation | Spin-current switched magnetic memory element suitable for circuit integration and method of fabricating the memory element |
US7110287B2 (en) * | 2004-02-13 | 2006-09-19 | Grandis, Inc. | Method and system for providing heat assisted switching of a magnetic element utilizing spin transfer |
FR2866750B1 (en) | 2004-02-23 | 2006-04-21 | Centre Nat Rech Scient | MAGNETIC MEMORY MEMORY WITH MAGNETIC TUNNEL JUNCTION AND METHOD FOR ITS WRITING |
US6992359B2 (en) * | 2004-02-26 | 2006-01-31 | Grandis, Inc. | Spin transfer magnetic element with free layers having high perpendicular anisotropy and in-plane equilibrium magnetization |
FR2867300B1 (en) | 2004-03-05 | 2006-04-28 | Commissariat Energie Atomique | MAGNETORESISTIVE HIGH LIFE MEMORY WITH HIGH CURRENT DENSITY |
US7148531B2 (en) * | 2004-04-29 | 2006-12-12 | Nve Corporation | Magnetoresistive memory SOI cell |
US7102921B2 (en) * | 2004-05-11 | 2006-09-05 | Hewlett-Packard Development Company, L.P. | Magnetic memory device |
US7576956B2 (en) * | 2004-07-26 | 2009-08-18 | Grandis Inc. | Magnetic tunnel junction having diffusion stop layer |
KR100642638B1 (en) * | 2004-10-21 | 2006-11-10 | 삼성전자주식회사 | Methods of operating a magnetic random access memory device with low critical current density |
JP4575136B2 (en) * | 2004-12-20 | 2010-11-04 | 株式会社東芝 | Magnetic recording element, magnetic recording apparatus, and information recording method |
JP4575181B2 (en) * | 2005-01-28 | 2010-11-04 | 株式会社東芝 | Spin injection magnetic random access memory |
JP4528660B2 (en) * | 2005-03-31 | 2010-08-18 | 株式会社東芝 | Spin injection FET |
ES2422455T3 (en) | 2005-08-12 | 2013-09-11 | Modumetal Llc | Compositionally modulated composite materials and methods for manufacturing them |
US7973349B2 (en) | 2005-09-20 | 2011-07-05 | Grandis Inc. | Magnetic device having multilayered free ferromagnetic layer |
US7859034B2 (en) * | 2005-09-20 | 2010-12-28 | Grandis Inc. | Magnetic devices having oxide antiferromagnetic layer next to free ferromagnetic layer |
US7777261B2 (en) * | 2005-09-20 | 2010-08-17 | Grandis Inc. | Magnetic device having stabilized free ferromagnetic layer |
FR2892231B1 (en) * | 2005-10-14 | 2008-06-27 | Commissariat Energie Atomique | MAGNETIC DEVICE WITH MAGNETORESISTIVE TUNNEL JUNCTION AND MAGNETIC MEMORY WITH RANDOM ACCESS |
JP4883982B2 (en) * | 2005-10-19 | 2012-02-22 | ルネサスエレクトロニクス株式会社 | Nonvolatile memory device |
US7486545B2 (en) * | 2005-11-01 | 2009-02-03 | Magic Technologies, Inc. | Thermally assisted integrated MRAM design and process for its manufacture |
JP4779608B2 (en) * | 2005-11-30 | 2011-09-28 | Tdk株式会社 | Magnetic memory |
US7430135B2 (en) * | 2005-12-23 | 2008-09-30 | Grandis Inc. | Current-switched spin-transfer magnetic devices with reduced spin-transfer switching current density |
JP2007266498A (en) * | 2006-03-29 | 2007-10-11 | Toshiba Corp | Magnetic recording element and magnetic memory |
US20070246787A1 (en) * | 2006-03-29 | 2007-10-25 | Lien-Chang Wang | On-plug magnetic tunnel junction devices based on spin torque transfer switching |
US7903452B2 (en) * | 2006-06-23 | 2011-03-08 | Qimonda Ag | Magnetoresistive memory cell |
US7851840B2 (en) * | 2006-09-13 | 2010-12-14 | Grandis Inc. | Devices and circuits based on magnetic tunnel junctions utilizing a multilayer barrier |
TWI449040B (en) | 2006-10-06 | 2014-08-11 | Crocus Technology Sa | System and method for providing content-addressable magnetoresistive random access memory cells |
KR100834811B1 (en) | 2006-11-28 | 2008-06-09 | 고려대학교 산학협력단 | CoFeSiB/Pt multilayers exhibiting perpendicular magnetic anisotropy |
US20090218645A1 (en) * | 2007-02-12 | 2009-09-03 | Yadav Technology Inc. | multi-state spin-torque transfer magnetic random access memory |
US7573736B2 (en) * | 2007-05-22 | 2009-08-11 | Taiwan Semiconductor Manufacturing Company | Spin torque transfer MRAM device |
US7688616B2 (en) * | 2007-06-18 | 2010-03-30 | Taiwan Semicondcutor Manufacturing Company, Ltd. | Device and method of programming a magnetic memory element |
US7957179B2 (en) * | 2007-06-27 | 2011-06-07 | Grandis Inc. | Magnetic shielding in magnetic multilayer structures |
JP5152712B2 (en) * | 2007-07-17 | 2013-02-27 | 独立行政法人理化学研究所 | Magnetization state control device and magnetic information recording device |
US7982275B2 (en) * | 2007-08-22 | 2011-07-19 | Grandis Inc. | Magnetic element having low saturation magnetization |
US8100228B2 (en) * | 2007-10-12 | 2012-01-24 | D B Industries, Inc. | Portable anchorage assembly |
US9812184B2 (en) | 2007-10-31 | 2017-11-07 | New York University | Current induced spin-momentum transfer stack with dual insulating layers |
FR2924851B1 (en) * | 2007-12-05 | 2009-11-20 | Commissariat Energie Atomique | MAGNETIC ELEMENT WITH THERMALLY ASSISTED WRITING. |
WO2009074411A1 (en) | 2007-12-13 | 2009-06-18 | Crocus Technology | Magnetic memory with a thermally assisted writing procedure |
FR2925747B1 (en) * | 2007-12-21 | 2010-04-09 | Commissariat Energie Atomique | MAGNETIC MEMORY WITH THERMALLY ASSISTED WRITING |
FR2929041B1 (en) * | 2008-03-18 | 2012-11-30 | Crocus Technology | MAGNETIC ELEMENT WITH THERMALLY ASSISTED WRITING |
US7936597B2 (en) * | 2008-03-25 | 2011-05-03 | Seagate Technology Llc | Multilevel magnetic storage device |
EP2109111B1 (en) | 2008-04-07 | 2011-12-21 | Crocus Technology S.A. | System and method for writing data to magnetoresistive random access memory cells |
US8659852B2 (en) | 2008-04-21 | 2014-02-25 | Seagate Technology Llc | Write-once magentic junction memory array |
FR2931011B1 (en) | 2008-05-06 | 2010-05-28 | Commissariat Energie Atomique | MAGNETIC ELEMENT WITH THERMALLY ASSISTED WRITING |
EP2124228B1 (en) | 2008-05-20 | 2014-03-05 | Crocus Technology | Magnetic random access memory with an elliptical junction |
US7855911B2 (en) | 2008-05-23 | 2010-12-21 | Seagate Technology Llc | Reconfigurable magnetic logic device using spin torque |
US7852663B2 (en) | 2008-05-23 | 2010-12-14 | Seagate Technology Llc | Nonvolatile programmable logic gates and adders |
US8031519B2 (en) * | 2008-06-18 | 2011-10-04 | Crocus Technology S.A. | Shared line magnetic random access memory cells |
US7804709B2 (en) * | 2008-07-18 | 2010-09-28 | Seagate Technology Llc | Diode assisted switching spin-transfer torque memory unit |
US8223532B2 (en) * | 2008-08-07 | 2012-07-17 | Seagate Technology Llc | Magnetic field assisted STRAM cells |
US8054677B2 (en) | 2008-08-07 | 2011-11-08 | Seagate Technology Llc | Magnetic memory with strain-assisted exchange coupling switch |
US7881098B2 (en) | 2008-08-26 | 2011-02-01 | Seagate Technology Llc | Memory with separate read and write paths |
US7894248B2 (en) | 2008-09-12 | 2011-02-22 | Grandis Inc. | Programmable and redundant circuitry based on magnetic tunnel junction (MTJ) |
US7746687B2 (en) | 2008-09-30 | 2010-06-29 | Seagate Technology, Llc | Thermally assisted multi-bit MRAM |
US8487390B2 (en) * | 2008-10-08 | 2013-07-16 | Seagate Technology Llc | Memory cell with stress-induced anisotropy |
US8169810B2 (en) | 2008-10-08 | 2012-05-01 | Seagate Technology Llc | Magnetic memory with asymmetric energy barrier |
US8039913B2 (en) | 2008-10-09 | 2011-10-18 | Seagate Technology Llc | Magnetic stack with laminated layer |
US8089132B2 (en) | 2008-10-09 | 2012-01-03 | Seagate Technology Llc | Magnetic memory with phonon glass electron crystal material |
US20100091564A1 (en) * | 2008-10-10 | 2010-04-15 | Seagate Technology Llc | Magnetic stack having reduced switching current |
US8217478B2 (en) | 2008-10-10 | 2012-07-10 | Seagate Technology Llc | Magnetic stack with oxide to reduce switching current |
US8228703B2 (en) | 2008-11-04 | 2012-07-24 | Crocus Technology Sa | Ternary Content Addressable Magnetoresistive random access memory cell |
US8045366B2 (en) | 2008-11-05 | 2011-10-25 | Seagate Technology Llc | STRAM with composite free magnetic element |
US8043732B2 (en) | 2008-11-11 | 2011-10-25 | Seagate Technology Llc | Memory cell with radial barrier |
US7826181B2 (en) | 2008-11-12 | 2010-11-02 | Seagate Technology Llc | Magnetic memory with porous non-conductive current confinement layer |
US8289756B2 (en) * | 2008-11-25 | 2012-10-16 | Seagate Technology Llc | Non volatile memory including stabilizing structures |
KR101532752B1 (en) * | 2009-01-21 | 2015-07-02 | 삼성전자주식회사 | Magnetic memory device |
EP2221826A1 (en) * | 2009-02-19 | 2010-08-25 | Crocus Technology S.A. | Active strap magnetic random access memory cells |
US8053255B2 (en) * | 2009-03-03 | 2011-11-08 | Seagate Technology Llc | STRAM with compensation element and method of making the same |
US7916528B2 (en) | 2009-03-30 | 2011-03-29 | Seagate Technology Llc | Predictive thermal preconditioning and timing control for non-volatile memory cells |
EP2249350B1 (en) | 2009-05-08 | 2012-02-01 | Crocus Technology | Magnetic memory with a thermally assisted spin transfer torque writing procedure using a low writing current |
EP2249349B1 (en) | 2009-05-08 | 2012-02-08 | Crocus Technology | Magnetic memory with a thermally assisted writing procedure and reduced writng field |
US8218349B2 (en) | 2009-05-26 | 2012-07-10 | Crocus Technology Sa | Non-volatile logic devices using magnetic tunnel junctions |
FR2946183B1 (en) | 2009-05-27 | 2011-12-23 | Commissariat Energie Atomique | MAGNETIC DEVICE WITH POLARIZATION OF SPIN. |
US8686520B2 (en) * | 2009-05-29 | 2014-04-01 | International Business Machines Corporation | Spin-torque magnetoresistive structures |
EA201792049A1 (en) | 2009-06-08 | 2018-05-31 | Модьюметал, Инк. | ELECTRICALLY DESIGNED NANOLAMINATE COATINGS AND SHELLS FOR PROTECTION AGAINST CORROSION |
US8750028B2 (en) | 2009-07-03 | 2014-06-10 | Fuji Electric Co., Ltd. | Magnetic memory element and driving method for same |
EP2276034B1 (en) | 2009-07-13 | 2016-04-27 | Crocus Technology S.A. | Self-referenced magnetic random access memory cell |
US7999338B2 (en) | 2009-07-13 | 2011-08-16 | Seagate Technology Llc | Magnetic stack having reference layers with orthogonal magnetization orientation directions |
US8102703B2 (en) | 2009-07-14 | 2012-01-24 | Crocus Technology | Magnetic element with a fast spin transfer torque writing procedure |
US8445979B2 (en) * | 2009-09-11 | 2013-05-21 | Samsung Electronics Co., Ltd. | Magnetic memory devices including magnetic layers separated by tunnel barriers |
US8469832B2 (en) * | 2009-11-03 | 2013-06-25 | Wonderland Nurserygoods Company Limited | Swing apparatus with detachable infant holding device |
US8199553B2 (en) * | 2009-12-17 | 2012-06-12 | Hitachi Global Storage Technologies Netherlands B.V. | Multilevel frequency addressable field driven MRAM |
EP2405439B1 (en) | 2010-07-07 | 2013-01-23 | Crocus Technology S.A. | Magnetic device with optimized heat confinement |
FR2964248B1 (en) | 2010-09-01 | 2013-07-19 | Commissariat Energie Atomique | MAGNETIC DEVICE AND READING AND WRITING PROCESS IN SUCH A MAGNETIC DEVICE |
EP2447949B1 (en) | 2010-10-26 | 2016-11-30 | Crocus Technology | Multi level magnetic element |
US8358154B2 (en) | 2010-10-29 | 2013-01-22 | Honeywell International Inc. | Magnetic logic gate |
US8358149B2 (en) | 2010-10-29 | 2013-01-22 | Honeywell International Inc. | Magnetic logic gate |
US8427199B2 (en) | 2010-10-29 | 2013-04-23 | Honeywell International Inc. | Magnetic logic gate |
US8374020B2 (en) | 2010-10-29 | 2013-02-12 | Honeywell International Inc. | Reduced switching-energy magnetic elements |
EP2466586B1 (en) | 2010-12-16 | 2016-03-02 | Crocus Technology | Multibit magnetic random access memory cell with improved read margin |
EP2479759A1 (en) | 2011-01-19 | 2012-07-25 | Crocus Technology S.A. | Low power magnetic random access memory cell |
KR101739952B1 (en) | 2011-02-25 | 2017-05-26 | 삼성전자주식회사 | Magnetic memory device |
EP2523105B1 (en) | 2011-05-10 | 2019-12-04 | Crocus Technology S.A. | Information processing device comprising a read-only memory and a method for patching the read-only memory |
EP2528060B1 (en) | 2011-05-23 | 2016-12-14 | Crocus Technology S.A. | Multibit cell with synthetic storage layer |
FR2976396B1 (en) * | 2011-06-07 | 2013-07-12 | Commissariat Energie Atomique | MAGNETIC STACK AND MEMORY POINT COMPRISING SUCH A STACK |
US8427197B2 (en) | 2011-06-15 | 2013-04-23 | Honeywell International Inc. | Configurable reference circuit for logic gates |
EP2546836A1 (en) | 2011-07-12 | 2013-01-16 | Crocus Technology S.A. | Magnetic random access memory cell with improved dispersion of the switching field |
EP2575135B1 (en) | 2011-09-28 | 2015-08-05 | Crocus Technology S.A. | Magnetic random access memory (MRAM) cell and method for reading the MRAM cell using a self-referenced read operation |
EP2615610B1 (en) * | 2012-01-16 | 2016-11-02 | Crocus Technology S.A. | Mram cell and method for writing to the mram cell using a thermally assisted write operation with a reduced field current |
US8570792B2 (en) * | 2012-01-24 | 2013-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetoresistive random access memory |
US8884386B2 (en) | 2012-02-02 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | MRAM device and fabrication method thereof |
EP2672487B1 (en) * | 2012-06-08 | 2015-08-05 | Crocus Technology S.A. | Method for writing to a Random Access Memory (MRAM) Cell with improved MRAM Cell Lifespan |
US9082950B2 (en) | 2012-10-17 | 2015-07-14 | New York University | Increased magnetoresistance in an inverted orthogonal spin transfer layer stack |
US9082888B2 (en) | 2012-10-17 | 2015-07-14 | New York University | Inverted orthogonal spin transfer layer stack |
EP2725580B1 (en) | 2012-10-25 | 2018-07-18 | Crocus Technology S.A. | Thermally assisted MRAM cell and method for writing a plurality of bits in the MRAM cell |
EP2736045B1 (en) | 2012-11-27 | 2016-09-21 | Crocus Technology S.A. | Magnetic random access memory (MRAM) cell with low power consumption |
EP2760025B1 (en) * | 2013-01-23 | 2019-01-02 | Crocus Technology S.A. | TAS-MRAM element with low writing temperature |
EA201500949A1 (en) | 2013-03-15 | 2016-02-29 | Модьюметл, Инк. | METHOD OF FORMING A MULTILAYER COATING, A COATING FORMED BY THE ABOVE METHOD, AND A MULTILAYER COATING |
WO2014146114A1 (en) | 2013-03-15 | 2014-09-18 | Modumetal, Inc. | Nanolaminate coatings |
WO2014146117A2 (en) | 2013-03-15 | 2014-09-18 | Modumetal, Inc. | A method and apparatus for continuously applying nanolaminate metal coatings |
CN110273167A (en) * | 2013-03-15 | 2019-09-24 | 莫杜美拓有限公司 | Pass through the composition and nanometer layer pressing gold of the electro-deposition of the product of addition manufacturing process preparation |
US8982613B2 (en) | 2013-06-17 | 2015-03-17 | New York University | Scalable orthogonal spin transfer magnetic random access memory devices with reduced write error rates |
US20150129946A1 (en) * | 2013-11-13 | 2015-05-14 | International Business Machines Corporation | Self reference thermally assisted mram with low moment ferromagnet storage layer |
US9406870B2 (en) * | 2014-04-09 | 2016-08-02 | International Business Machines Corporation | Multibit self-reference thermally assisted MRAM |
US9330748B2 (en) | 2014-05-09 | 2016-05-03 | Tower Semiconductor Ltd. | High-speed compare operation using magnetic tunnel junction elements including two different anti-ferromagnetic layers |
US9331123B2 (en) * | 2014-05-09 | 2016-05-03 | Tower Semiconductor Ltd. | Logic unit including magnetic tunnel junction elements having two different anti-ferromagnetic layers |
US9263667B1 (en) | 2014-07-25 | 2016-02-16 | Spin Transfer Technologies, Inc. | Method for manufacturing MTJ memory device |
AR102068A1 (en) | 2014-09-18 | 2017-02-01 | Modumetal Inc | METHODS OF PREPARATION OF ITEMS BY ELECTRODEPOSITION AND ADDITIVE MANUFACTURING PROCESSES |
CN106795645B (en) | 2014-09-18 | 2020-03-27 | 莫杜美拓有限公司 | Method and apparatus for continuous application of nanolaminate metal coatings |
US9337412B2 (en) | 2014-09-22 | 2016-05-10 | Spin Transfer Technologies, Inc. | Magnetic tunnel junction structure for MRAM device |
US9564580B2 (en) * | 2014-12-29 | 2017-02-07 | International Business Machines Corporation | Double synthetic antiferromagnet using rare earth metals and transition metals |
US9728712B2 (en) | 2015-04-21 | 2017-08-08 | Spin Transfer Technologies, Inc. | Spin transfer torque structure for MRAM devices having a spin current injection capping layer |
US10468590B2 (en) | 2015-04-21 | 2019-11-05 | Spin Memory, Inc. | High annealing temperature perpendicular magnetic anisotropy structure for magnetic random access memory |
US9853206B2 (en) | 2015-06-16 | 2017-12-26 | Spin Transfer Technologies, Inc. | Precessional spin current structure for MRAM |
US9773974B2 (en) | 2015-07-30 | 2017-09-26 | Spin Transfer Technologies, Inc. | Polishing stop layer(s) for processing arrays of semiconductor elements |
US10163479B2 (en) | 2015-08-14 | 2018-12-25 | Spin Transfer Technologies, Inc. | Method and apparatus for bipolar memory write-verify |
US10573363B2 (en) | 2015-12-02 | 2020-02-25 | Samsung Electronics Co., Ltd. | Method and apparatus for performing self-referenced read in a magnetoresistive random access memory |
US9741926B1 (en) | 2016-01-28 | 2017-08-22 | Spin Transfer Technologies, Inc. | Memory cell having magnetic tunnel junction and thermal stability enhancement layer |
US10559624B2 (en) * | 2017-02-21 | 2020-02-11 | Avalanche Technology, Inc. | Selector device having asymmetric conductance for memory applications |
KR102306333B1 (en) * | 2016-05-31 | 2021-09-30 | 소니그룹주식회사 | Nonvolatile memory cell, memory cell unit, information writing method, and electronic device |
EA201990655A1 (en) | 2016-09-08 | 2019-09-30 | Модьюметал, Инк. | METHODS FOR PRODUCING MULTI-LAYER COATINGS ON BILLETS AND THE PRODUCTS EXECUTED BY THEM |
JP7051823B2 (en) | 2016-09-14 | 2022-04-11 | モジュメタル インコーポレイテッド | A system for high-reliability, high-throughput complex electric field generation, and methods for thereby forming a film. |
US10546625B2 (en) | 2016-09-27 | 2020-01-28 | Spin Memory, Inc. | Method of optimizing write voltage based on error buffer occupancy |
US10360964B2 (en) | 2016-09-27 | 2019-07-23 | Spin Memory, Inc. | Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device |
US10991410B2 (en) | 2016-09-27 | 2021-04-27 | Spin Memory, Inc. | Bi-polar write scheme |
US10818331B2 (en) | 2016-09-27 | 2020-10-27 | Spin Memory, Inc. | Multi-chip module for MRAM devices with levels of dynamic redundancy registers |
US10628316B2 (en) | 2016-09-27 | 2020-04-21 | Spin Memory, Inc. | Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register |
US11119936B2 (en) | 2016-09-27 | 2021-09-14 | Spin Memory, Inc. | Error cache system with coarse and fine segments for power optimization |
US10366774B2 (en) | 2016-09-27 | 2019-07-30 | Spin Memory, Inc. | Device with dynamic redundancy registers |
US10446210B2 (en) | 2016-09-27 | 2019-10-15 | Spin Memory, Inc. | Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers |
US10460781B2 (en) | 2016-09-27 | 2019-10-29 | Spin Memory, Inc. | Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank |
US11151042B2 (en) | 2016-09-27 | 2021-10-19 | Integrated Silicon Solution, (Cayman) Inc. | Error cache segmentation for power reduction |
US11119910B2 (en) | 2016-09-27 | 2021-09-14 | Spin Memory, Inc. | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments |
US10437723B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device |
US10437491B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register |
EP3535118A1 (en) | 2016-11-02 | 2019-09-11 | Modumetal, Inc. | Topology optimized high interface packing structures |
US10665777B2 (en) | 2017-02-28 | 2020-05-26 | Spin Memory, Inc. | Precessional spin current structure with non-magnetic insertion layer for MRAM |
US10672976B2 (en) | 2017-02-28 | 2020-06-02 | Spin Memory, Inc. | Precessional spin current structure with high in-plane magnetization for MRAM |
EP3601641A1 (en) | 2017-03-24 | 2020-02-05 | Modumetal, Inc. | Lift plungers with electrodeposited coatings, and systems and methods for producing the same |
CN110770372B (en) | 2017-04-21 | 2022-10-11 | 莫杜美拓有限公司 | Tubular article having an electrodeposited coating and system and method for producing same |
US10032978B1 (en) | 2017-06-27 | 2018-07-24 | Spin Transfer Technologies, Inc. | MRAM with reduced stray magnetic fields |
US10529439B2 (en) | 2017-10-24 | 2020-01-07 | Spin Memory, Inc. | On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects |
US10489245B2 (en) | 2017-10-24 | 2019-11-26 | Spin Memory, Inc. | Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them |
US10656994B2 (en) | 2017-10-24 | 2020-05-19 | Spin Memory, Inc. | Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques |
US10481976B2 (en) | 2017-10-24 | 2019-11-19 | Spin Memory, Inc. | Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers |
US10679685B2 (en) | 2017-12-27 | 2020-06-09 | Spin Memory, Inc. | Shared bit line array architecture for magnetoresistive memory |
US10811594B2 (en) | 2017-12-28 | 2020-10-20 | Spin Memory, Inc. | Process for hard mask development for MRAM pillar formation using photolithography |
US10424726B2 (en) | 2017-12-28 | 2019-09-24 | Spin Memory, Inc. | Process for improving photoresist pillar adhesion during MRAM fabrication |
US10395712B2 (en) | 2017-12-28 | 2019-08-27 | Spin Memory, Inc. | Memory array with horizontal source line and sacrificial bitline per virtual source |
US10891997B2 (en) | 2017-12-28 | 2021-01-12 | Spin Memory, Inc. | Memory array with horizontal source line and a virtual source line |
US10236047B1 (en) | 2017-12-29 | 2019-03-19 | Spin Memory, Inc. | Shared oscillator (STNO) for MRAM array write-assist in orthogonal STT-MRAM |
US10840439B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Magnetic tunnel junction (MTJ) fabrication methods and systems |
US10360961B1 (en) | 2017-12-29 | 2019-07-23 | Spin Memory, Inc. | AC current pre-charge write-assist in orthogonal STT-MRAM |
US10199083B1 (en) | 2017-12-29 | 2019-02-05 | Spin Transfer Technologies, Inc. | Three-terminal MRAM with ac write-assist for low read disturb |
US10886330B2 (en) | 2017-12-29 | 2021-01-05 | Spin Memory, Inc. | Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch |
US10424723B2 (en) | 2017-12-29 | 2019-09-24 | Spin Memory, Inc. | Magnetic tunnel junction devices including an optimization layer |
US10367139B2 (en) | 2017-12-29 | 2019-07-30 | Spin Memory, Inc. | Methods of manufacturing magnetic tunnel junction devices |
US10784439B2 (en) | 2017-12-29 | 2020-09-22 | Spin Memory, Inc. | Precessional spin current magnetic tunnel junction devices and methods of manufacture |
US10840436B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Perpendicular magnetic anisotropy interface tunnel junction devices and methods of manufacture |
US10270027B1 (en) | 2017-12-29 | 2019-04-23 | Spin Memory, Inc. | Self-generating AC current assist in orthogonal STT-MRAM |
US10236048B1 (en) | 2017-12-29 | 2019-03-19 | Spin Memory, Inc. | AC current write-assist in orthogonal STT-MRAM |
US10546624B2 (en) | 2017-12-29 | 2020-01-28 | Spin Memory, Inc. | Multi-port random access memory |
US10141499B1 (en) | 2017-12-30 | 2018-11-27 | Spin Transfer Technologies, Inc. | Perpendicular magnetic tunnel junction device with offset precessional spin current layer |
US10255962B1 (en) | 2017-12-30 | 2019-04-09 | Spin Memory, Inc. | Microwave write-assist in orthogonal STT-MRAM |
US10339993B1 (en) | 2017-12-30 | 2019-07-02 | Spin Memory, Inc. | Perpendicular magnetic tunnel junction device with skyrmionic assist layers for free layer switching |
US10236439B1 (en) | 2017-12-30 | 2019-03-19 | Spin Memory, Inc. | Switching and stability control for perpendicular magnetic tunnel junction device |
US10229724B1 (en) | 2017-12-30 | 2019-03-12 | Spin Memory, Inc. | Microwave write-assist in series-interconnected orthogonal STT-MRAM devices |
US10319900B1 (en) | 2017-12-30 | 2019-06-11 | Spin Memory, Inc. | Perpendicular magnetic tunnel junction device with precessional spin current layer having a modulated moment density |
US10468588B2 (en) | 2018-01-05 | 2019-11-05 | Spin Memory, Inc. | Perpendicular magnetic tunnel junction device with skyrmionic enhancement layers for the precessional spin current magnetic layer |
US10438995B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Devices including magnetic tunnel junctions integrated with selectors |
US10438996B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Methods of fabricating magnetic tunnel junctions integrated with selectors |
US10388861B1 (en) | 2018-03-08 | 2019-08-20 | Spin Memory, Inc. | Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same |
US10446744B2 (en) | 2018-03-08 | 2019-10-15 | Spin Memory, Inc. | Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same |
US20190296220A1 (en) | 2018-03-23 | 2019-09-26 | Spin Transfer Technologies, Inc. | Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer |
WO2019210264A1 (en) | 2018-04-27 | 2019-10-31 | Modumetal, Inc. | Apparatuses, systems, and methods for producing a plurality of articles with nanolaminated coatings using rotation |
US10411185B1 (en) | 2018-05-30 | 2019-09-10 | Spin Memory, Inc. | Process for creating a high density magnetic tunnel junction array test platform |
US11081153B2 (en) | 2018-06-29 | 2021-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetic memory device with balancing synthetic anti-ferromagnetic layer |
US10559338B2 (en) | 2018-07-06 | 2020-02-11 | Spin Memory, Inc. | Multi-bit cell read-out techniques |
US10593396B2 (en) | 2018-07-06 | 2020-03-17 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
US10600478B2 (en) | 2018-07-06 | 2020-03-24 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
US10692569B2 (en) | 2018-07-06 | 2020-06-23 | Spin Memory, Inc. | Read-out techniques for multi-bit cells |
US10699761B2 (en) | 2018-09-18 | 2020-06-30 | Spin Memory, Inc. | Word line decoder memory architecture |
US11621293B2 (en) | 2018-10-01 | 2023-04-04 | Integrated Silicon Solution, (Cayman) Inc. | Multi terminal device stack systems and methods |
US10971680B2 (en) | 2018-10-01 | 2021-04-06 | Spin Memory, Inc. | Multi terminal device stack formation methods |
US10580827B1 (en) | 2018-11-16 | 2020-03-03 | Spin Memory, Inc. | Adjustable stabilizer/polarizer method for MRAM with enhanced stability and efficient switching |
US11107979B2 (en) | 2018-12-28 | 2021-08-31 | Spin Memory, Inc. | Patterned silicide structures and methods of manufacture |
US10777248B1 (en) * | 2019-06-24 | 2020-09-15 | Western Digital Technologies, Inc. | Heat assisted perpendicular spin transfer torque MRAM memory cell |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5640343A (en) | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
WO2000079540A1 (en) | 1999-06-18 | 2000-12-28 | Nve Corporation | Magnetic memory coincident thermal pulse data storage |
US6272036B1 (en) | 1999-12-20 | 2001-08-07 | The University Of Chicago | Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage |
US20010019461A1 (en) | 2000-03-03 | 2001-09-06 | Rolf Allenspach | Magnetic millipede for ultra high density magnetic storage |
US6347049B1 (en) * | 2001-07-25 | 2002-02-12 | International Business Machines Corporation | Low resistance magnetic tunnel junction device with bilayer or multilayer tunnel barrier |
US6351410B1 (en) * | 1999-09-17 | 2002-02-26 | Fujitsu Limited | Ferromagnetic tunnel junction random access memory, spin valve random access memory, single ferromagnetic layer random access memory, and memory cell array using the same |
US6376260B1 (en) * | 1999-07-19 | 2002-04-23 | Motorola, Inc. | Magnetic element with improved field response and fabricating method thereof |
US6385082B1 (en) | 2000-11-08 | 2002-05-07 | International Business Machines Corp. | Thermally-assisted magnetic random access memory (MRAM) |
US6473337B1 (en) * | 2001-10-24 | 2002-10-29 | Hewlett-Packard Company | Memory device having memory cells with magnetic tunnel junction and tunnel junction in series |
JP2003060173A (en) | 2001-08-21 | 2003-02-28 | Canon Inc | Method for terminal auxiliary drive of ferromagnetic memory |
US6532164B2 (en) | 2000-12-07 | 2003-03-11 | Commissariat A L'energie Atomique | Magnetic spin polarization and magnetization rotation device with memory and writing process, using such a device |
US6552928B1 (en) * | 2001-02-23 | 2003-04-22 | Read-Rite Corporation | Read-write control circuit for magnetic tunnel junction MRAM |
US6574079B2 (en) * | 2000-11-09 | 2003-06-03 | Tdk Corporation | Magnetic tunnel junction device and method including a tunneling barrier layer formed by oxidations of metallic alloys |
US6603677B2 (en) | 2000-12-07 | 2003-08-05 | Commissariat A L'energie Atomique | Three-layered stacked magnetic spin polarization device with memory |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000285668A (en) * | 1999-03-26 | 2000-10-13 | Univ Nagoya | Magnetic memory device |
FR2829867B1 (en) * | 2001-09-20 | 2003-12-19 | Centre Nat Rech Scient | MAGNETIC MEMORY HAVING SELECTION BY WRITING BY INHIBITION AND METHOD FOR WRITING SAME |
US6649423B2 (en) * | 2001-10-04 | 2003-11-18 | Hewlett-Packard Development Company, L.P. | Method for modifying switching field characteristics of magnetic tunnel junctions |
FR2832542B1 (en) * | 2001-11-16 | 2005-05-06 | Commissariat Energie Atomique | MAGNETIC DEVICE WITH MAGNETIC TUNNEL JUNCTION, MEMORY AND METHODS OF WRITING AND READING USING THE DEVICE |
-
2001
- 2001-11-16 FR FR0114840A patent/FR2832542B1/en not_active Expired - Lifetime
-
2002
- 2002-11-14 JP JP2003544759A patent/JP4777613B2/en not_active Expired - Lifetime
- 2002-11-14 US US11/861,974 patent/USRE42619E1/en not_active Expired - Lifetime
- 2002-11-14 EP EP02796844A patent/EP1466329B1/en not_active Expired - Lifetime
- 2002-11-14 WO PCT/FR2002/003896 patent/WO2003043017A2/en active IP Right Grant
- 2002-11-14 US US10/495,637 patent/US6950335B2/en not_active Ceased
- 2002-11-14 AT AT02796844T patent/ATE359588T1/en not_active IP Right Cessation
- 2002-11-14 DE DE60219526T patent/DE60219526T2/en not_active Expired - Lifetime
- 2002-11-14 EP EP07007334A patent/EP1808862B1/en not_active Expired - Lifetime
-
2011
- 2011-05-25 JP JP2011117042A patent/JP2011193018A/en active Pending
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5640343A (en) | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
WO2000079540A1 (en) | 1999-06-18 | 2000-12-28 | Nve Corporation | Magnetic memory coincident thermal pulse data storage |
US6376260B1 (en) * | 1999-07-19 | 2002-04-23 | Motorola, Inc. | Magnetic element with improved field response and fabricating method thereof |
US6351410B1 (en) * | 1999-09-17 | 2002-02-26 | Fujitsu Limited | Ferromagnetic tunnel junction random access memory, spin valve random access memory, single ferromagnetic layer random access memory, and memory cell array using the same |
US6272036B1 (en) | 1999-12-20 | 2001-08-07 | The University Of Chicago | Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage |
US20010019461A1 (en) | 2000-03-03 | 2001-09-06 | Rolf Allenspach | Magnetic millipede for ultra high density magnetic storage |
US6385082B1 (en) | 2000-11-08 | 2002-05-07 | International Business Machines Corp. | Thermally-assisted magnetic random access memory (MRAM) |
US6574079B2 (en) * | 2000-11-09 | 2003-06-03 | Tdk Corporation | Magnetic tunnel junction device and method including a tunneling barrier layer formed by oxidations of metallic alloys |
US6532164B2 (en) | 2000-12-07 | 2003-03-11 | Commissariat A L'energie Atomique | Magnetic spin polarization and magnetization rotation device with memory and writing process, using such a device |
US6603677B2 (en) | 2000-12-07 | 2003-08-05 | Commissariat A L'energie Atomique | Three-layered stacked magnetic spin polarization device with memory |
US6552928B1 (en) * | 2001-02-23 | 2003-04-22 | Read-Rite Corporation | Read-write control circuit for magnetic tunnel junction MRAM |
US6347049B1 (en) * | 2001-07-25 | 2002-02-12 | International Business Machines Corporation | Low resistance magnetic tunnel junction device with bilayer or multilayer tunnel barrier |
JP2003060173A (en) | 2001-08-21 | 2003-02-28 | Canon Inc | Method for terminal auxiliary drive of ferromagnetic memory |
US6473337B1 (en) * | 2001-10-24 | 2002-10-29 | Hewlett-Packard Company | Memory device having memory cells with magnetic tunnel junction and tunnel junction in series |
Non-Patent Citations (1)
Title |
---|
Parkin et al., "Exchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory (invited)", Apr. 15, 1999, Journal of Applied Physics, vol. 85, No. 8, pp. 5828-5833. |
Also Published As
Publication number | Publication date |
---|---|
DE60219526D1 (en) | 2007-05-24 |
JP2005510047A (en) | 2005-04-14 |
EP1808862A1 (en) | 2007-07-18 |
US6950335B2 (en) | 2005-09-27 |
JP4777613B2 (en) | 2011-09-21 |
FR2832542A1 (en) | 2003-05-23 |
DE60219526T2 (en) | 2007-12-20 |
EP1466329B1 (en) | 2007-04-11 |
ATE359588T1 (en) | 2007-05-15 |
FR2832542B1 (en) | 2005-05-06 |
EP1808862B1 (en) | 2012-10-24 |
EP1466329A2 (en) | 2004-10-13 |
WO2003043017A2 (en) | 2003-05-22 |
US20050002228A1 (en) | 2005-01-06 |
WO2003043017A3 (en) | 2003-12-11 |
JP2011193018A (en) | 2011-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE42619E1 (en) | Magnetic tunnel junction magnetic device, memory and writing and reading methods using said device | |
Apalkov et al. | Magnetoresistive random access memory | |
US5953248A (en) | Low switching field magnetic tunneling junction for high density arrays | |
US7372116B2 (en) | Heat assisted switching in an MRAM cell utilizing the antiferromagnetic to ferromagnetic transition in FeRh | |
KR101085246B1 (en) | Magnetic memory with a magnetic tunnel junction written in a thermally assisted manner, and method for writing the same | |
Tehrani et al. | High density submicron magnetoresistive random access memory | |
US7796428B2 (en) | Thermally assisted magnetic write memory | |
US7190611B2 (en) | Spin-transfer multilayer stack containing magnetic layers with resettable magnetization | |
US7266013B2 (en) | Magnetic memory layers thermal pulse transitions | |
USRE44878E1 (en) | Current switched magnetoresistive memory cell | |
US6958927B1 (en) | Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element | |
US6385082B1 (en) | Thermally-assisted magnetic random access memory (MRAM) | |
US7965543B2 (en) | Method for reducing current density in a magnetoelectronic device | |
Beech et al. | Curie point written magnetoresistive memory | |
US8064245B2 (en) | Magnetic random access memory with an elliptical magnetic tunnel junction | |
US20100246254A1 (en) | Magnetic memory with a thermally assisted writing procedure | |
JP2005535125A (en) | Magnetic element using spin transfer and MRAM device using magnetic element | |
JP2011091429A (en) | Magnetic tunnel junction | |
KR20110112428A (en) | Magnetic memory | |
EP2528060B1 (en) | Multibit cell with synthetic storage layer | |
JP2003188359A (en) | Magneto-resistive device including magnetically soft synthetic ferrimagnet reference layer | |
JP2003197872A (en) | Memory using magneto-resistance effect film | |
Daughton | Magnetoresistive random access memories | |
JP2003197870A (en) | Information storage device and its writing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |