USRE36261E - Stack capacitor DRAM cell having increased capacitor area - Google Patents

Stack capacitor DRAM cell having increased capacitor area Download PDF

Info

Publication number
USRE36261E
USRE36261E US08/761,082 US76108296A USRE36261E US RE36261 E USRE36261 E US RE36261E US 76108296 A US76108296 A US 76108296A US RE36261 E USRE36261 E US RE36261E
Authority
US
United States
Prior art keywords
layer
iaddend
iadd
stacked capacitor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/761,082
Inventor
Dae-Je Chin
Tae-Young Chung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to US08/761,082 priority Critical patent/USRE36261E/en
Application granted granted Critical
Publication of USRE36261E publication Critical patent/USRE36261E/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Definitions

  • This invention relates to DRAM(Dynamic Random Access Memory) cells and a method for manufacturing them, and more particularly to a stacked capacitor DRAM cell which can obtain a high-capacitance without the increment of capacitor area in a semiconductor device.
  • DRAM Dynamic Random Access Memory
  • a .Iaddend.trend the trench capacitor DRAM cell and stacked capacitor DRAM cell . .came on.!. .Iadd.were developed.Iaddend..
  • FIG. 1 shows the vertical cross-sectional view of a stacked capacitor DRAM cell
  • the fabricating processes of the stacked capacitor DRAM cell are as follows.
  • a p-well 32 is formed on a p-type substrate 31.
  • a field oxide 34 is grown on an active region over the p-well, and a p + layer is formed by injecting impurities.
  • a gate poly 35 and a source-drain region for transistors are formed, and a contact is formed to form a storage poly 41, and said storage poly is etched selectively.
  • an insulating layer 46 for a capacitor is formed by oxidizing said storage poly, and a plate poly 48 is deposited.
  • the layers of an oxide 49, a polycide 50, a B-PSG 51 and a metal 52 are formed in sequence. ., now.!. .Iadd.. Now .Iaddend.the series of processes for manufacturing a DRAM cell are completed.
  • the effective area of a capacitor 41 of a DRAM cell manufactured by the above described way is determined by the top and side area of the storage poly. To increase the effective area of the stacked capacitor, the thickness of the storage poly 41 is increased up to now.
  • the magnitude of the capacitance manufactured by way of increasing the side area is not sufficient for high-density memories because the cell area of a 4M DRAM is 10 ⁇ m 2 , but that of a 16M DRAM reduces to 5 ⁇ m 2 .
  • the increment of thickness of the storage poly in the entire area of the cell causes the deterioration of cell topology so that the patterning of the storage poly and the bit-line and the metal is difficult.
  • the manufacturing of the high-density DRAMS beyond 4M DRAM is difficult by the conventional technology. The reason is that the capacitance per unit cell reduces remarkably when the 16M DRAM is manufactured by the prior technology.
  • the object of the invention is to provide a stacked capacitor DRAM cell and a method thereof which makes the manufacturing of a 16M DRAM possible by maximizing the effective area of the stacked capacitor in a confined area.
  • the invention in a first aspect, is a stacked capacitor DRAM in which the effective area of the capacitor is maximized with a storage poly layer for capacitor. There are three factors in increasing the effective area according to the present invention.
  • the storage poly layer . .which.!. is formed thick in a region over the field oxide layer. That is, the region in the storage poly layer over the field oxide layer is twice coated by the polysilicon so that the capacitance increases as much as that.
  • a saddle mask When a first poly layer is removed except the portion over the field oxide layer, it is preferable to use a saddle mask. That is because the etched surface of the storage poly layer is very rough, and this conditions makes the effective area for the capacitor increase in a large scale.
  • the formation of the storage poly layer through two steps leads a topology to be improved as the thickness in the region of a bit line contact is shallow.
  • a spacer controls the magnitude of a capacitance. While the etching process of the storage poly layer employing the oxide layer on the storage poly as an etching mask, the etching pattern of the oxide layer is restricted by the resolution capability of a photoresist. Therefore, since the size of the etching pattern is determined by the resolution capability, the quantity of the storage poly layer to be removed is also effected by the resolution capability. However, the spacers cause the remaining storage poly layer to be large as the portion thereof to be removed is small.
  • An undercut is included as one of three factors.
  • the undercut is carried out in the region just below the boundary region of the storage poly layer. Accordingly the effective area is increased once more.
  • the stacked capacitor according to the invention is increased in a curved surface with the saddle mask, and the oxide layer under the storage poly layer is wrapped by a capacitor dielectric layer.
  • the saddled and wrapped stacked capacitor is increased in a curved surface with the saddle mask, and the oxide layer under the storage poly layer is wrapped by a capacitor dielectric layer.
  • the invention in another aspect, is a method of manufacturing the saddled and wrapped stacked capacitor DRAM.
  • FIG. 1 is a vertical cross-sectional view of a prior DRAM cell.
  • FIG. 2 is a plane layout of a stacked capacitor DRAM cell of this invention.
  • FIG. 3 is a vertical cross-sectional view of FIG. 2 taken along line A-A' thereof.
  • FIG. 4 is a vertical cross-sectional view of FIG. 2 taken along line B-B' thereof.
  • FIGS. 5A to 5L are vertical cross-sectional views of each process showing in sequential order the steps of an embodiment for manufacturing the DRAM cell of this invention.
  • the reference numeral 60 is a gate poly and the numeral 62 is a saddle mask.
  • the reference numerals 64, 66 are a buried contact and a storage poly respectively.
  • the numeral 68 is a plate poly and a bit line contact is indicated by the numeral 70.
  • the characters ML and BL shows a metal line and a bit line, respectively.
  • FIG. 5 is a vertical cross-sectional view showing in sequential order the steps of an embodiment for manufacturing a stacked capacitor DRAM.
  • a p-type well 2 and . .a.!. .Iadd.an .Iaddend.n-type well 3 are formed on a p-type substrate 1.
  • Impurities of p-type are injected into a region of the p-type well 2 which will be a field region in the well 2, and then a field oxide layer 4 is grown. From this resultant, a channel stop region of p + -type is formed (FIG. 5B).
  • a gate oxide layer 4' is grown on regions to be active regions by way of a conventional way, and impurities are injected in order to control a threshold voltage of a transistor.
  • a poly layer 5 is then deposited over the substrate, and a gate poly oxide layer 6 is grown on the poly layer.
  • the layers 4', 5 and 6 are selectively etched out employing a conventional photo-lithographic technique, and the layer 5 results in a gate poly layer.
  • FIG. 5D shows an oxide spacer 7 which is formed in the sidewall of the poly-silicon layer 5. Ion impurities of n-type are then injected into the p-well so as to form the regions which come to be a source S and a drain D of a transistor.
  • an oxide layer 8 (the lower oxide layer), a nitride layer 9 and an oxide layer 10 are formed in sequence.
  • the layers 8,9,10 are formed by the method of Chemical Vapor Deposition, and the thickness of each layer is about 1000 ⁇ .
  • a first poly-silicon layer 11 is then coated with the thickness of about 3000 ⁇ .
  • the layers 8,9 and 10 play the role of the inter-poly (laminated) insulating layer between the gate poly layer 5 and the first poly layer 11.
  • the first poly layer may be formed with the poly doped initially with the n + -type impurities, or n + -type impurities may be doped after depositing the non-doped poly-silicon.
  • the first poly layer 11 is selectively etched out, employing a saddle mask, except the poly-silicon coated over the upper surface side of the field oxide layer 4.
  • the saddle mask causes the etched surface of the storage poly layer to be very rough so that this condition makes the effective area for the capacitor increase in a large scale. That is, the increment of the surface area with the curved surface states increases the quantity of the storage poly with respect to the another deposition of a poly-silicon layer.
  • Buried contacts 12 are then formed and the buried contact leads the source to be connected with a second poly which will be an electrode of a capacitor.
  • the order of forming the first poly layer and the contact can be carried out reversely.
  • the second poly layer 11' is deposited with about 2500 ⁇ thickness over the entire surface of the p-well, and an oxide layer 14 is coated by the thickness of about 1500-3000 ⁇ , by way of CVD technique, on the second poly layer.
  • an oxide layer 14 is coated by the thickness of about 1500-3000 ⁇ , by way of CVD technique, on the second poly layer.
  • the upper surface of the portion of the second poly layer 11' overlying the first poly layer 11 is also rough.
  • FIG. 5H shows the next step.
  • the reference numeral 13 is a poly storage layer consisting of the first and second poly layer 11 and 11', and hereinafter the first and second poly-silicon layer (laminate) 11, 11' will be represented as the poly storage layer and a single hatching.
  • the oxide layer 14 is selectively etched out per unit of a cell.
  • the etching pattern of the oxide layer 14 is restricted by the resolution capability of the photoresist. Accordingly, the size of the etching pattern must be at least equal or large than the resolution capability.
  • an oxide spacer is employed in order to maximize the capacitance. After forming the etching pattern of the storage poly, an oxide layer is coated on the oxide layer 14. The oxide spacer 15 is then formed through the etch back technique. The size of the spacer is determined with the magnitude of the storage layer to be remained, that is, with the capacitance of a capacitor according to a device characteristic.
  • the exposed storage poly layer 13 is removed by employing the remaining oxide layer 14 and oxide spacer 15 as a mask. This etching process exposes the portions of the oxide layer 10 below the removed storage layer. Subsequently, using the isotropic technique the oxide layers 10, 14 are removed. The isotropic etching makes the oxide layer 10 (the uppermost lamina of the laminated insulating layer 8-9-10) have undercut surfaces because the boundary portions of the oxide layer 10 is etched out into apertures by the isotropic properties. Therefore, the exposed portions of the storage poly are increased, and the storage capability for charges is also increased.
  • the degrees of the undercut depend on the magnitude of capacitance to be obtained, and these are controlled by the difference of the thickness between the oxide layer 10 and 14. If the layer 14 is thicker than the layer 10, the degrees of the etching in the layer 10 may increase. The removal of the layer 10, 14 may be carried out separately.
  • the protection by the nitride layer 9 (the lamina exposed by the undercutting of the layer 10) for the oxide layer 8 prevents the short between the gate poly layer 5 and a plate poly layer 17 represented in FIG. 5J from occurring.
  • a dielectric layer 16 for a capacitor is formed along the entire exposed surface of the storage poly layer 13.
  • the plate poly layer 17 is then deposited over the p-well by about 1500 ⁇ , and then the plate poly layer 17 is selectively removed as shown in FIG. 5J.
  • a plate poly oxide layer 18 is grown by oxidizing the plate layer 17 so as to have the thickness of about 1000 ⁇ .
  • the BPSG(Boron Phosphorus Silicate Glass) 19 is deposited on the plate poly oxide layer 18 by the low temperature oxidation technique. A BPSG flow is then carried out for the planarization of the surface. Employing a mask, a bit line contact is formed and a policide layer 20 is filled therein.
  • the BPSG 21 is coated and the glass 21 is flowed.
  • a contact for metal line is then formed using a mask and a metal layer is deposited.
  • the coated metal layer is selectively removed employing a mask.
  • the DRAM cell fabricated through the above-mentioned processes has a wide effective area for the capacitor as shown be in FIG. 2 and FIG. 3, because the storage poly-silicon for capacitor is formed with an enough thickness over the field oxide layer 4, as well as the exposed area of the storage poly layer 13 is increased by . .causing.!. .Iadd.providing .Iaddend.the undercut just below the boundary region of the storage layer . .to bring about;.!. so that the effective area of the capacitor results in wide area. Furthermore, with the employment of the oxide spacer, the magnitude of capacitance is increased and controlled with the dimensions of the oxide spacer.
  • the storage poly layer to be the capacitor electrode is formed not only thick in the region over the field oxide layer but also shallowly in the contact region of the bit line, the effective area of the capacitor increases and the topology of the bit line contact area is improved.
  • the gap between the remaining storage poly layer is narrow as much as possible by using the oxide spacer, so that the remaining area of the storage poly layer is wide and the effective area of the capacitor is increased once more.
  • the third factor which increases the capacitor area is the undercut phenomenon which breaks down in the region just below the boundary region of the storage poly layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a . .plat.!. .Iadd.plate .Iaddend.poly material is coated and wrapped.

Description

BACKGROUND OF THE INVENTION
This invention relates to DRAM(Dynamic Random Access Memory) cells and a method for manufacturing them, and more particularly to a stacked capacitor DRAM cell which can obtain a high-capacitance without the increment of capacitor area in a semiconductor device. Recently, in the field of DRAM technology, the effort of minimizing the chip size has been completed, while the capacitance value needed for each cell has been maintained. According to such .Iadd.a .Iaddend.trend, the trench capacitor DRAM cell and stacked capacitor DRAM cell . .came on.!. .Iadd.were developed.Iaddend.. These techniques contributed largely to the high-density DRAM technology.
To explain the method for manufacturing a stacked capacitor DRAM cell, referring to FIG. 1 which shows the vertical cross-sectional view of a stacked capacitor DRAM cell, the fabricating processes of the stacked capacitor DRAM cell are as follows.
At first, a p-well 32 is formed on a p-type substrate 31. A field oxide 34 is grown on an active region over the p-well, and a p+ layer is formed by injecting impurities. After above processes a gate poly 35 and a source-drain region for transistors are formed, and a contact is formed to form a storage poly 41, and said storage poly is etched selectively.
Thereafter, an insulating layer 46 for a capacitor is formed by oxidizing said storage poly, and a plate poly 48 is deposited. The layers of an oxide 49, a polycide 50, a B-PSG 51 and a metal 52 are formed in sequence. ., now.!. .Iadd.. Now .Iaddend.the series of processes for manufacturing a DRAM cell are completed.
The effective area of a capacitor 41 of a DRAM cell manufactured by the above described way is determined by the top and side area of the storage poly. To increase the effective area of the stacked capacitor, the thickness of the storage poly 41 is increased up to now.
However, the magnitude of the capacitance manufactured by way of increasing the side area is not sufficient for high-density memories because the cell area of a 4M DRAM is 10 μm2, but that of a 16M DRAM reduces to 5 μm2. The increment of thickness of the storage poly in the entire area of the cell causes the deterioration of cell topology so that the patterning of the storage poly and the bit-line and the metal is difficult. The manufacturing of the high-density DRAMS beyond 4M DRAM is difficult by the conventional technology. The reason is that the capacitance per unit cell reduces remarkably when the 16M DRAM is manufactured by the prior technology.
SUMMARY OF THE INVENTION
The object of the invention is to provide a stacked capacitor DRAM cell and a method thereof which makes the manufacturing of a 16M DRAM possible by maximizing the effective area of the stacked capacitor in a confined area.
The invention, in a first aspect, is a stacked capacitor DRAM in which the effective area of the capacitor is maximized with a storage poly layer for capacitor. There are three factors in increasing the effective area according to the present invention.
One factor is that the storage poly layer . .which.!. is formed thick in a region over the field oxide layer. That is, the region in the storage poly layer over the field oxide layer is twice coated by the polysilicon so that the capacitance increases as much as that.
When a first poly layer is removed except the portion over the field oxide layer, it is preferable to use a saddle mask. That is because the etched surface of the storage poly layer is very rough, and this conditions makes the effective area for the capacitor increase in a large scale.
The formation of the storage poly layer through two steps leads a topology to be improved as the thickness in the region of a bit line contact is shallow.
Second, a spacer controls the magnitude of a capacitance. While the etching process of the storage poly layer employing the oxide layer on the storage poly as an etching mask, the etching pattern of the oxide layer is restricted by the resolution capability of a photoresist. Therefore, since the size of the etching pattern is determined by the resolution capability, the quantity of the storage poly layer to be removed is also effected by the resolution capability. However, the spacers cause the remaining storage poly layer to be large as the portion thereof to be removed is small.
An undercut is included as one of three factors. The undercut is carried out in the region just below the boundary region of the storage poly layer. Accordingly the effective area is increased once more.
As depicted in FIG. 4, the stacked capacitor according to the invention is increased in a curved surface with the saddle mask, and the oxide layer under the storage poly layer is wrapped by a capacitor dielectric layer. Now we call this structure the saddled and wrapped stacked capacitor.
The invention, in another aspect, is a method of manufacturing the saddled and wrapped stacked capacitor DRAM.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a vertical cross-sectional view of a prior DRAM cell.
FIG. 2 is a plane layout of a stacked capacitor DRAM cell of this invention.
FIG. 3 is a vertical cross-sectional view of FIG. 2 taken along line A-A' thereof.
FIG. 4 is a vertical cross-sectional view of FIG. 2 taken along line B-B' thereof.
FIGS. 5A to 5L are vertical cross-sectional views of each process showing in sequential order the steps of an embodiment for manufacturing the DRAM cell of this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention will now be described in details with reference to the accompanying drawings.
In FIG. 2, the reference numeral 60 is a gate poly and the numeral 62 is a saddle mask. The reference numerals 64, 66 are a buried contact and a storage poly respectively. The numeral 68 is a plate poly and a bit line contact is indicated by the numeral 70. The characters ML and BL shows a metal line and a bit line, respectively.
FIG. 5 is a vertical cross-sectional view showing in sequential order the steps of an embodiment for manufacturing a stacked capacitor DRAM. Referring now to FIG. 5A, a p-type well 2 and . .a.!. .Iadd.an .Iaddend.n-type well 3 are formed on a p-type substrate 1.
Hereinafter, the preferred embodiment of this invention will now be described by setting the p-well on the basis of describing the embodiment. For the n-well, only the type of impurities is changed.
Impurities of p-type are injected into a region of the p-type well 2 which will be a field region in the well 2, and then a field oxide layer 4 is grown. From this resultant, a channel stop region of p+ -type is formed (FIG. 5B).
As shown in FIG. 5C, a gate oxide layer 4' is grown on regions to be active regions by way of a conventional way, and impurities are injected in order to control a threshold voltage of a transistor. A poly layer 5 is then deposited over the substrate, and a gate poly oxide layer 6 is grown on the poly layer. The layers 4', 5 and 6 are selectively etched out employing a conventional photo-lithographic technique, and the layer 5 results in a gate poly layer.
FIG. 5D shows an oxide spacer 7 which is formed in the sidewall of the poly-silicon layer 5. Ion impurities of n-type are then injected into the p-well so as to form the regions which come to be a source S and a drain D of a transistor.
Thereafter, as shown in FIG. 5E, an oxide layer 8 (the lower oxide layer), a nitride layer 9 and an oxide layer 10 are formed in sequence. The layers 8,9,10 are formed by the method of Chemical Vapor Deposition, and the thickness of each layer is about 1000 Å. A first poly-silicon layer 11 is then coated with the thickness of about 3000 Å.
The layers 8,9 and 10 play the role of the inter-poly (laminated) insulating layer between the gate poly layer 5 and the first poly layer 11. The first poly layer may be formed with the poly doped initially with the n+ -type impurities, or n+ -type impurities may be doped after depositing the non-doped poly-silicon.
Referring now to FIG. 5F, the first poly layer 11 is selectively etched out, employing a saddle mask, except the poly-silicon coated over the upper surface side of the field oxide layer 4. During this process, the saddle mask causes the etched surface of the storage poly layer to be very rough so that this condition makes the effective area for the capacitor increase in a large scale. That is, the increment of the surface area with the curved surface states increases the quantity of the storage poly with respect to the another deposition of a poly-silicon layer.
Buried contacts 12 are then formed and the buried contact leads the source to be connected with a second poly which will be an electrode of a capacitor. The order of forming the first poly layer and the contact can be carried out reversely.
After that, as shown in FIG. 5G, the second poly layer 11' is deposited with about 2500 Å thickness over the entire surface of the p-well, and an oxide layer 14 is coated by the thickness of about 1500-3000 Å, by way of CVD technique, on the second poly layer. As above indicated, owing to the rough, etched surface of the poly layer 11, the upper surface of the portion of the second poly layer 11' overlying the first poly layer 11 is also rough.
FIG. 5H shows the next step. The reference numeral 13 is a poly storage layer consisting of the first and second poly layer 11 and 11', and hereinafter the first and second poly-silicon layer (laminate) 11, 11' will be represented as the poly storage layer and a single hatching.
Employing a photoresist mask, the oxide layer 14 is selectively etched out per unit of a cell. In this etching process, the etching pattern of the oxide layer 14 is restricted by the resolution capability of the photoresist. Accordingly, the size of the etching pattern must be at least equal or large than the resolution capability. According to the present invention an oxide spacer is employed in order to maximize the capacitance. After forming the etching pattern of the storage poly, an oxide layer is coated on the oxide layer 14. The oxide spacer 15 is then formed through the etch back technique. The size of the spacer is determined with the magnitude of the storage layer to be remained, that is, with the capacitance of a capacitor according to a device characteristic.
In FIG. 5I, the exposed storage poly layer 13 is removed by employing the remaining oxide layer 14 and oxide spacer 15 as a mask. This etching process exposes the portions of the oxide layer 10 below the removed storage layer. Subsequently, using the isotropic technique the oxide layers 10, 14 are removed. The isotropic etching makes the oxide layer 10 (the uppermost lamina of the laminated insulating layer 8-9-10) have undercut surfaces because the boundary portions of the oxide layer 10 is etched out into apertures by the isotropic properties. Therefore, the exposed portions of the storage poly are increased, and the storage capability for charges is also increased.
The degrees of the undercut depend on the magnitude of capacitance to be obtained, and these are controlled by the difference of the thickness between the oxide layer 10 and 14. If the layer 14 is thicker than the layer 10, the degrees of the etching in the layer 10 may increase. The removal of the layer 10, 14 may be carried out separately.
The protection by the nitride layer 9 (the lamina exposed by the undercutting of the layer 10) for the oxide layer 8 prevents the short between the gate poly layer 5 and a plate poly layer 17 represented in FIG. 5J from occurring.
Referring now to FIG. 5J, a dielectric layer 16 for a capacitor is formed along the entire exposed surface of the storage poly layer 13. The plate poly layer 17 is then deposited over the p-well by about 1500 Å, and then the plate poly layer 17 is selectively removed as shown in FIG. 5J.
Then a plate poly oxide layer 18 is grown by oxidizing the plate layer 17 so as to have the thickness of about 1000 Å.
As shown in FIG. 5K, the BPSG(Boron Phosphorus Silicate Glass) 19 is deposited on the plate poly oxide layer 18 by the low temperature oxidation technique. A BPSG flow is then carried out for the planarization of the surface. Employing a mask, a bit line contact is formed and a policide layer 20 is filled therein.
After the above processes, in FIG. 5L, the BPSG 21 is coated and the glass 21 is flowed. A contact for metal line is then formed using a mask and a metal layer is deposited. The coated metal layer is selectively removed employing a mask.
The DRAM cell fabricated through the above-mentioned processes has a wide effective area for the capacitor as shown be in FIG. 2 and FIG. 3, because the storage poly-silicon for capacitor is formed with an enough thickness over the field oxide layer 4, as well as the exposed area of the storage poly layer 13 is increased by . .causing.!. .Iadd.providing .Iaddend.the undercut just below the boundary region of the storage layer . .to bring about;.!. so that the effective area of the capacitor results in wide area. Furthermore, with the employment of the oxide spacer, the magnitude of capacitance is increased and controlled with the dimensions of the oxide spacer.
The effects of the DRAM cell manufactured according to the present invention are as follows.
Since the storage poly layer to be the capacitor electrode is formed not only thick in the region over the field oxide layer but also shallowly in the contact region of the bit line, the effective area of the capacitor increases and the topology of the bit line contact area is improved.
When the storage poly is removed, the gap between the remaining storage poly layer is narrow as much as possible by using the oxide spacer, so that the remaining area of the storage poly layer is wide and the effective area of the capacitor is increased once more.
The third factor which increases the capacitor area is the undercut phenomenon which breaks down in the region just below the boundary region of the storage poly layer.
Accordingly, since the effective area for the capacitor is enormously increased through the above-mentioned three factors according to the invention, the area of the DRAM decreases, and this result makes the manufacturing of the VLSI possible.
This invention is in no way limited to the example described hereinabove. Various modifications of the disclosed embodiment, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims (16)

What is claimed is:
1. A stacked capacitor DRAM formed on a substrate comprising a plurality of memory cells on said substrate, each of said cells comprising a charge transfer transistor and a stacked capacitor, said stacked capacitor comprising a laminated insulating layer having a plurality of laminae disposed on a portion of the substrate, said insulating layer terminating in a side edge, a storage polysilicon layer for said capacitor including a first portion disposed on said insulating layer and a second portion extending beyond the side edge thereof, said second portion extending to and overlying a gate of said charge transfer transistor, said first portion having a greater thickness than said second portion, said polysilicon layer terminating in a side edge, and including a conductive layer separated from said polysilicon layer by a dielectric layer, said conductive and dielectric layers extending over an upper surface of said polysilicon layer, along said side edge thereof, and beneath a section of said first portion of said polysilicon layer, an edge of a first, uppermost lamina of said insulating layer being disposed beneath and inwardly of said side edge of said polysilicon layer . .thereby providing a space between a bottom surface portion of said polysilicon layer.!. thereby providing a space between a bottom surface portion of said polysilicon layer and a surface portion of a second lamina of said insulating layer beneath said uppermost lamina, and said space being filled with the portions of said conductive and dielectric layers extending beneath said polysilicon layer whereby said conductive and dielectric layers do not surround said storage polysilicon layer.
2. A stacked capacitor as in claim 1 including a conductive member disposed beneath said polysilicon layer, and wherein said second lamina of said . .insulting.!. .Iadd.insulating .Iaddend.layer insulates the portion of said conductive layer extending beneath said polysilicon layer from said conductive member.
3. The DRAM according to claim 1 wherein said second portion of said storage polysilicon layer is substantially uniform in thickness.
4. The DRAM according to claim 2 wherein said second portion of said storage polysilicon layer is substantially uniform in thickness.
5. The DRAM according to claim 1 wherein said laminated insulating layer comprises 3 laminae, the insulating material of the center lamina being of a different insulating material than . .a.!. .Iadd.an .Iaddend.upper lamina thereof.
6. The DRAM according to claim 2 wherein said laminated insulating layer comprises 3 laminae, the insulating material of the center lamina being of a different insulating material than . .a.!. .Iadd.an .Iaddend.upper lamina thereof.
7. The DRAM according to claim 3 wherein said laminated insulating layer comprises 3 laminae, the insulating material of the center lamina being of a different insulating material than . .a.!. .Iadd.an .Iaddend.upper lamina thereof.
8. The DRAM according to claim 4 wherein said laminated insulating layer comprises 3 laminae, the insulating material of the center lamina being of a different insulating material than . .a.!. .Iadd.an .Iaddend.upper lamina thereof. .Iadd.
9. A semiconductor memory device, comprising:
a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon;
a first capacitive electrode layer formed on said insulating layer, said first capacitive electrode layer having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion;
a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and
a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said dielectric layer and said insulating layer. .Iaddend..Iadd.
10. The semiconductor device of claim 9, wherein said partial lower surface of said first capacitive electrode layer and said insulating layer define an undercut region under said first capacitive electrode layer. .Iaddend..Iadd.11. The semiconductor device of claim 10, wherein said undercut region is of variable size. .Iaddend..Iadd.12. The semiconductor device of claim 9, wherein said partial lower surface defines inner and outer ends of said edge portion extending over said gate electrode. .Iaddend..Iadd.13. The semiconductor device of claim 12, wherein said inner and outer ends of said edge portion terminate within a vertical plane defined by first and second sides of the gate electrode. .Iaddend..Iadd.14. The semiconductor device of claim 13, wherein the outer end of said edge portion extends a first lateral distance over said gate electrode and said inner end of said edge portion extends a second lesser distance over said gate electrode. .Iaddend..Iadd.15. The semiconductor device of claim 12, wherein said inner end of said edge portion terminates within a vertical plane defined by first and second sides of the gate electrode, and said outer end of said edge portion terminates outside of the vertical plane defined by the first and second sides of the gate
electrode. .Iaddend..Iadd.16. A semiconductor memory device, comprising:
a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon, wherein said insulating layer is a laminated insulating layer comprising a plurality of laminae;
a first capacitive electrode layer formed on said insulating layer, said first capacitive electrode layer having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion;
a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and
a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said
dielectric layer and said insulating layer. .Iaddend..Iadd.17. A stacked capacitor as in claim 16, wherein said insulating layer comprises upper, center and lower lamina. .Iaddend..Iadd.18. A stacked capacitor as in claim 17, wherein an insulating material of said center lamina is different than an insulating material of said upper lamina. .Iaddend..Iadd.19. A stacked capacitor as in claim 18, wherein said insulating material of said center lamina is nitride and said insulating material of said upper lamina is oxide. .Iaddend..Iadd.20. A stacked capacitor as in claim 19, wherein said insulating material of said lower lamina is oxide. .Iaddend..Iadd.21. A stacked capacitor as in claim 19, wherein said comprising a conductive member disposed beneath said first capacitive electrode layer, and wherein said center lamina of said insulating layer insulates a portion of said second capacitive electrode layer extending beneath said first capacitive electrode layer from said second capacitive electrode layer. .Iaddend..Iadd.22. A stacked capacitor as in claim 9, wherein said partial lower surface defines an undercut
extending over said gate electrode. .Iaddend..Iadd.23. A stacked capacitor as in claim 9, wherein said partial lower surface defines an undercut extending over a word line. .Iaddend..Iadd.24. A stacked capacitor as in claim 9, having at least one of a partial lower surface defining a first undercut extending over said gate electrode, and a partial lower surface defining a second undercut extending over a word line. .Iaddend..Iadd.25. A stacked capacitor as in claim 9, having a partial lower surface defining a first undercut extending over said gate electrode, and a partial lower surface defining a second undercut extending over a word line. .Iaddend..Iadd.26. A semiconductor memory device, comprising:
a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon;
a first capacitive electrode layer having a first portion formed on said insulating layer and a second portion having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion;
a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and
a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said dielectric layer and said insulating layer. .Iaddend..Iadd.27. A stacked capacitor as in claim 26, wherein said first portion of said first capacitive electrode layer is substantially uniform in thickness.
.Iaddend..Iadd.28. A stacked capacitor as in claim 26, wherein said second portion of said first capacitive electrode layer is substantially uniform in thickness. .Iaddend..Iadd.29. A stacked capacitor as in claim 28, said first portion having a greater thickness than said second portion. .Iaddend..Iadd.30. A stacked capacitor DRAM formed on a substrate comprising a plurality of memory cells on said substrate, each of said cells comprising a charge transfer transistor and a stacked capacitor, said stacked capacitor comprising:
a laminated insulating layer terminating in a side edge;
a storage polysilicon layer for said capacitor including a first portion disposed on said insulating layer and a second portion extending beyond the side edge thereof, said second portion extending to and overlying a gate of said charge transfer transistor,
said polysilicon layer terminating in a side edge, and including a conductive layer separated from said polysilicon layer by a dielectric layer, said conductive and dielectric layers extending over an upper surface of said polysilicon layer, along said side edge thereof, and beneath a section of said polysilicon layer, an edge of said insulating layer being disposed beneath and inwardly of said side edge of said polysilicon layer thereby providing a space between a bottom surface portion of said polysilicon layer and a top surface portion of said insulating layer, and said space being filled with the portions of said conductive and dielectric layers extending beneath said polysilicon layer whereby said conductive and dielectric layers do not surround said storage polysilicon layer. .Iaddend..Iadd.31. A stacked capacitor as in claim 30, said laminated insulating layer comprising a plurality of laminae. .Iaddend..Iadd.32. A stacked capacitor as in claim 31, wherein said insulating layer comprises upper, center and lower lamina.
.Iaddend..Iadd. 3. A stacked capacitor as in claim 32, wherein an insulating material of said center lamina is different than an insulating material of said upper lamina. .Iaddend..Iadd.34. A stacked capacitor as in claim 33, wherein said insulating material of said center lamina is nitride and said insulating material of said upper lamina is oxide. .Iaddend..Iadd.35. A stacked capacitor as in claim 34, wherein said insulating material of said lower lamina is oxide. .Iaddend..Iadd.36. A stacked capacitor as in claim 32, further comprising a conductive member disposed beneath said polysilicon layer, and wherein said center lamina of said insulating layer insulated a portion of said conductive member extending beneath said polysilicon layer from said conductive member. .Iaddend..Iadd.37. A stacked capacitor as in claim 30, wherein said space, between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defines an undercut overlying a word line. .Iaddend..Iadd.38. A stacked capacitor as in claim 30, wherein said space, between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defines an undercut overlying the gate of said charge transfer transistor. .Iaddend..Iadd.39. A stacked capacitor as in claim 30, having at least one of
said space between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defining a first undercut overlying a word line, and
said space between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defining a second undercut overlying the gate of said charge
transfer transistor. .Iaddend..Iadd.40. A stacked capacitor as in claim 30, having said space between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defining a first undercut overlying a word line, and
said space between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defining a second undercut overlying the gate of said charge transfer transistor. .Iaddend..Iadd.41. A stacked capacitor as in claim 30, wherein said first portion of said polysilicon layer is substantially uniform in thickness. .Iaddend..Iadd.42. A stacked capacitor as in claim 41, wherein said second portion of said polysilicon layer is substantially uniform in thickness. .Iaddend..Iadd.43. A stacked capacitor as in claim 42, said first portion having a greater thickness than said second portion. .Iaddend.
US08/761,082 1988-06-07 1996-12-04 Stack capacitor DRAM cell having increased capacitor area Expired - Lifetime USRE36261E (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/761,082 USRE36261E (en) 1988-06-07 1996-12-04 Stack capacitor DRAM cell having increased capacitor area

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR88-6796 1988-06-07
KR1019880006796A KR910010167B1 (en) 1988-06-07 1988-06-07 Stack capacitor dram cell and its manufacturing method
US07/283,968 US5378908A (en) 1988-06-07 1988-12-13 Stack capacitor DRAM cell having increased capacitor area
US08/761,082 USRE36261E (en) 1988-06-07 1996-12-04 Stack capacitor DRAM cell having increased capacitor area

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US07/283,968 Reissue US5378908A (en) 1988-06-07 1988-12-13 Stack capacitor DRAM cell having increased capacitor area

Publications (1)

Publication Number Publication Date
USRE36261E true USRE36261E (en) 1999-08-03

Family

ID=19275004

Family Applications (3)

Application Number Title Priority Date Filing Date
US07/283,968 Ceased US5378908A (en) 1988-06-07 1988-12-13 Stack capacitor DRAM cell having increased capacitor area
US07/431,790 Expired - Lifetime US5120674A (en) 1988-06-07 1989-11-06 Method of making stacked capacitor dram cell
US08/761,082 Expired - Lifetime USRE36261E (en) 1988-06-07 1996-12-04 Stack capacitor DRAM cell having increased capacitor area

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US07/283,968 Ceased US5378908A (en) 1988-06-07 1988-12-13 Stack capacitor DRAM cell having increased capacitor area
US07/431,790 Expired - Lifetime US5120674A (en) 1988-06-07 1989-11-06 Method of making stacked capacitor dram cell

Country Status (7)

Country Link
US (3) US5378908A (en)
JP (1) JP2825245B2 (en)
KR (1) KR910010167B1 (en)
DE (1) DE3842474C2 (en)
FR (1) FR2632453B1 (en)
GB (1) GB2219690B (en)
NL (1) NL193882C (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666437B2 (en) * 1987-11-17 1994-08-24 富士通株式会社 Semiconductor memory device and manufacturing method thereof
US20010008288A1 (en) * 1988-01-08 2001-07-19 Hitachi, Ltd. Semiconductor integrated circuit device having memory cells
JP2838412B2 (en) * 1988-06-10 1998-12-16 三菱電機株式会社 Capacitor for semiconductor memory device and method of manufacturing the same
DE3918924C2 (en) * 1988-06-10 1996-03-21 Mitsubishi Electric Corp Manufacturing method for a semiconductor memory device
US5180683A (en) * 1988-06-10 1993-01-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing stacked capacitor type semiconductor memory device
US5248628A (en) * 1989-09-08 1993-09-28 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor memory device
EP1465248A1 (en) * 1990-03-08 2004-10-06 Fujitsu Limited Layer structure having contact hole and method of producing the same
KR930000581B1 (en) * 1990-04-04 1993-01-25 금성일렉트론 주식회사 Dram cell having a self-aligned capacitor contact and method of fabricating the same
KR930000718B1 (en) * 1990-05-21 1993-01-30 삼성전자 주식회사 Method for fabricating semiconductor device
FR2663786A1 (en) * 1990-06-21 1991-12-27 Samsung Electronics Co Ltd Method of fabricating capacitors in a DRAM cell
KR930007192B1 (en) * 1990-06-29 1993-07-31 삼성전자 주식회사 Stacked capacitor of dram and its manufacturing method
US5219778A (en) * 1990-10-16 1993-06-15 Micron Technology, Inc. Stacked V-cell capacitor
US5237187A (en) * 1990-11-30 1993-08-17 Hitachi, Ltd. Semiconductor memory circuit device and method for fabricating same
JPH04242938A (en) * 1991-01-08 1992-08-31 Mitsubishi Electric Corp Electrode wiring layer of semiconductor device and its manufacture
JPH04342164A (en) * 1991-05-20 1992-11-27 Hitachi Ltd Formation of semiconductor integrated circuit device
US5269895A (en) * 1991-05-21 1993-12-14 North American Philips Corporation Method of making composite structure with single domain magnetic element
US5149668A (en) * 1991-11-19 1992-09-22 Micron Technology, Inc. Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits
JPH05218349A (en) * 1992-02-04 1993-08-27 Sony Corp Semiconductor storage device
US5244826A (en) * 1992-04-16 1993-09-14 Micron Technology, Inc. Method of forming an array of finned memory cell capacitors on a semiconductor substrate
US5326714A (en) * 1993-07-22 1994-07-05 Taiwan Semiconductor Manufacturing Company Method of making a fully used tub DRAM cell
JP3474332B2 (en) * 1994-10-11 2003-12-08 台灣茂▲夕▼電子股▲分▼有限公司 Self-tuning capacitor bottom plate local interconnect method for DRAM
US7705383B2 (en) * 1995-09-20 2010-04-27 Micron Technology, Inc. Integrated circuitry for semiconductor memory
JP3941133B2 (en) * 1996-07-18 2007-07-04 富士通株式会社 Semiconductor device and manufacturing method thereof
US5970340A (en) * 1997-06-24 1999-10-19 Micron Technology, Inc. Method for making semiconductor device incorporating an electrical contact to an internal conductive layer
KR100486197B1 (en) * 1997-06-30 2006-04-21 삼성전자주식회사 Capacitor bottom electrode formation method using halftone mask
US6369432B1 (en) 1998-02-23 2002-04-09 Micron Technology, Inc. Enhanced capacitor shape
TW396545B (en) 1998-12-21 2000-07-01 Vanguard Int Semiconduct Corp DRAM using oxide plug in bitline contacts during fabrication and its methods
US6441483B1 (en) * 2001-03-30 2002-08-27 Micron Technology, Inc. Die stacking scheme
US8169014B2 (en) * 2006-01-09 2012-05-01 Taiwan Semiconductor Manufacturing Co., Ltd. Interdigitated capacitive structure for an integrated circuit
US7842579B2 (en) * 2007-01-22 2010-11-30 Infineon Technologies Ag Method for manufacturing a semiconductor device having doped and undoped polysilicon layers

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58213461A (en) * 1982-06-07 1983-12-12 Nec Corp Semiconductor device
US4635090A (en) * 1980-09-17 1987-01-06 Hitachi, Ltd. Tapered groove IC isolation
US4641166A (en) * 1982-12-20 1987-02-03 Fujitsu Limited Semiconductor memory device having stacked capacitor-type memory cells
US4742018A (en) * 1985-11-29 1988-05-03 Hitachi, Ltd. Process for producing memory cell having stacked capacitor
US4754313A (en) * 1984-04-28 1988-06-28 Fujitsu Limited Semiconductor memory device having stacked-capacitor type memory cells
US4974040A (en) * 1987-06-17 1990-11-27 Fujitsu Limited Dynamic random access memory device and method of producing same
US5047817A (en) * 1988-06-10 1991-09-10 Mitsubishi Denki Kabushiki Kasiha Stacked capacitor for semiconductor memory device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936331A (en) * 1974-04-01 1976-02-03 Fairchild Camera And Instrument Corporation Process for forming sloped topography contact areas between polycrystalline silicon and single-crystal silicon
US4251571A (en) * 1978-05-02 1981-02-17 International Business Machines Corporation Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
US4214946A (en) * 1979-02-21 1980-07-29 International Business Machines Corporation Selective reactive ion etching of polysilicon against SiO2 utilizing SF6 -Cl2 -inert gas etchant
JPS5649553A (en) * 1979-09-28 1981-05-06 Hitachi Ltd Manufacture of semiconductor memory
JPS5824022B2 (en) * 1979-10-17 1983-05-18 沖電気工業株式会社 Manufacturing method of MOS type semiconductor memory device
JPS58134458A (en) * 1982-02-04 1983-08-10 Toshiba Corp Manufacture of capacitor in semiconductor device
JPS61183952A (en) * 1985-02-09 1986-08-16 Fujitsu Ltd Semiconductor memory device and manufacture thereof
US4863849A (en) * 1985-07-18 1989-09-05 New York Medical College Automatable process for sequencing nucleotide
JPS62124766A (en) * 1985-11-25 1987-06-06 Toshiba Corp Semiconductor device and manufacture thereof
US4855801A (en) * 1986-08-22 1989-08-08 Siemens Aktiengesellschaft Transistor varactor for dynamics semiconductor storage means
JPH0734451B2 (en) * 1986-09-03 1995-04-12 日本電気株式会社 Method for manufacturing semiconductor device
JP2627515B2 (en) * 1987-12-10 1997-07-09 富士通株式会社 Semiconductor memory device and method of manufacturing the same
JPH0666437B2 (en) * 1987-11-17 1994-08-24 富士通株式会社 Semiconductor memory device and manufacturing method thereof
JP2755591B2 (en) * 1988-03-25 1998-05-20 株式会社東芝 Semiconductor storage device
US4871688A (en) * 1988-05-02 1989-10-03 Micron Technology, Inc. Sequence of etching polysilicon in semiconductor memory devices
US4951175A (en) * 1988-05-18 1990-08-21 Kabushiki Kaisha Toshiba Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4635090A (en) * 1980-09-17 1987-01-06 Hitachi, Ltd. Tapered groove IC isolation
JPS58213461A (en) * 1982-06-07 1983-12-12 Nec Corp Semiconductor device
US4641166A (en) * 1982-12-20 1987-02-03 Fujitsu Limited Semiconductor memory device having stacked capacitor-type memory cells
US4754313A (en) * 1984-04-28 1988-06-28 Fujitsu Limited Semiconductor memory device having stacked-capacitor type memory cells
US4742018A (en) * 1985-11-29 1988-05-03 Hitachi, Ltd. Process for producing memory cell having stacked capacitor
US4974040A (en) * 1987-06-17 1990-11-27 Fujitsu Limited Dynamic random access memory device and method of producing same
US5047817A (en) * 1988-06-10 1991-09-10 Mitsubishi Denki Kabushiki Kasiha Stacked capacitor for semiconductor memory device

Also Published As

Publication number Publication date
DE3842474A1 (en) 1989-12-14
KR910010167B1 (en) 1991-12-17
GB2219690A (en) 1989-12-13
US5120674A (en) 1992-06-09
JP2825245B2 (en) 1998-11-18
FR2632453A1 (en) 1989-12-08
JPH0226065A (en) 1990-01-29
NL193882B (en) 2000-09-01
FR2632453B1 (en) 1992-07-03
KR900001045A (en) 1990-01-31
GB2219690B (en) 1992-10-07
NL193882C (en) 2001-01-03
GB8829637D0 (en) 1989-02-15
NL8803117A (en) 1990-01-02
DE3842474C2 (en) 1996-12-19
US5378908A (en) 1995-01-03

Similar Documents

Publication Publication Date Title
USRE36261E (en) Stack capacitor DRAM cell having increased capacitor area
US5240871A (en) Corrugated storage contact capacitor and method for forming a corrugated storage contact capacitor
US5192703A (en) Method of making tungsten contact core stack capacitor
US5612559A (en) Semiconductor device having pillar shaped transistor and a method for manufacturing the same
US6620680B2 (en) Method of forming a contact structure and a container capacitor structure
US5065273A (en) High capacity DRAM trench capacitor and methods of fabricating same
US5798544A (en) Semiconductor memory device having trench isolation regions and bit lines formed thereover
US5262662A (en) Storage node capacitor having tungsten and etched tin storage node capacitor plate
US5336629A (en) Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors
US5168073A (en) Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate
US6770527B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
US6573551B1 (en) Semiconductor memory device having self-aligned contact and fabricating method thereof
US5989952A (en) Method for fabricating a crown-type capacitor of a DRAM cell
US6268243B1 (en) Method for fabricating dynamic random access memory cells
KR0151012B1 (en) Dram cell & its producing method
CN100394584C (en) Method for producing semiconductor device with contact extended at bit line direction
US6770928B2 (en) Semiconductor memory with vertical selection transistor
US6054394A (en) Method of fabricating a dynamic random access memory capacitor
US5903024A (en) Stacked and trench type DRAM capacitor
KR100324632B1 (en) Semiconductor device having through-hole of two-layer structure
US7312489B2 (en) Memory cell having bar-shaped storage node contact plugs and methods of fabricating same
US5663093A (en) Method for forming a cylindrical capacitor having a central spine
KR100416607B1 (en) Semiconductor device including transistor and manufacturing methode thereof
US5960280A (en) Method of fabricating a fin/cavity capacitor structure for DRAM cell
US6365928B1 (en) Semiconductor memory storage electrode and method of making

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12