USRE27779E - Numerical data processing system - Google Patents

Numerical data processing system Download PDF

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USRE27779E
USRE27779E US27779DE USRE27779E US RE27779 E USRE27779 E US RE27779E US 27779D E US27779D E US 27779DE US RE27779 E USRE27779 E US RE27779E
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store
access
units
signal
call
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

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  • a numerical data processing system which is comprised of a general large capacity information store and a plurality of processors selectively connectable to as many access channels of said store from the selective activation of as many store access calling lines.
  • Part at least of said processors are provided with additional store access calling lines which are associated with hardware equipment for organizing a hierarchy of priority conicting access calls from said processors to said store.
  • Numerical data processing systems which comprise the association of a large capacity information store with a plurality of processor units which are connectable to said store for two-day information exchanges.
  • processor units which may be said to be a central unit, consists of a program controlled numerical computer and the other processor units consist of data exchange units between the general store and external units, commonly called peripheral units, peripherals for short.
  • peripheral units peripherals for short.
  • an exchange processor unit only connects a single peripheral in the system, it is said to be a direct exchange unit.
  • an exchange processor unit serves several peripherals, through as many secondary exchange units, i.e. peripheral connecting units, it is considered as a peripheral multiplexing unit in the system.
  • two such multiplexing units may be established on the basisV of a party line access to the store which, of course, only presents a iinite number of access channels to the associated processor units.
  • the normal" access calling lines of the processor units are associated with, at least for part of said units, high priority" access calling lines, means are provided in such units responsive to local conditions for activation of said high prority" access calling lines, and a device is provided in the access channel arrangement of the store for interpretation of activations of said second high priority" lines and subsequent connection of a processor unit wherein a high priority line has been activated to a high priority access channel in said access channel arrangement of the store.
  • said access call interpretative device is so designed as lo maintain a hierarchy of the store access channels as well for normal as for high priority calls and to control, when necessary, such a hierarchy during the execution of a store operation cycle which has been initiated under the rst mentioned hierarchy.
  • FIG. l is the general organization of a system in accordance with the present invention.
  • FIG. 2 is an illustrative embodiment of the access all interpretative device of FIG. 1;
  • FIG. 3 is a series of Waveform explanation of the operation of the interpretative device of FIG. 2;
  • FIG. 4 is an example of the circuits which generate the signals of store access channel calls in a peripheral multiplexing unit in the system of FIG. l.
  • the large capacity store is shown at M as including for purposes of illustration eight access channels, A0 to A7.
  • A0 and Al respectively cooperate with central units UC() and UCL
  • A2 to A7 cooperate with exchange units the complexity of which decreases according to their ranks:
  • A2 and A3 each cooperates with one pair of peripheral multiplexing units UEl and UE2 which share a single access channel.
  • A4 to A6 respectively cooperate with single multiplexing units and A7, for the purpose of illustration, is shown cooperating with a direct exchange unit between M and a peripheral equipment P7.
  • the access call interpretative device is shown as a block marked (FIG. 2)," the detailed arrangement thereof being detailed in said FIG. 2.
  • said device is provided with eight outputs, CA! to CA7, each controlling, when activated, the control input of the corresponding access channel, AI] to A7, for establishing the corresponding connection, U0 to U7, between the store M and the processors.
  • CA outputs
  • the very organization of the access channels is conventional and consequently does not necessitate any detailed description. It should be kept in mind that, when an access channel is activated, the normal process is as follows: a store address send by the processor is decoded and a local program is initiated for interconnection of the store to the calling processor.
  • the internal organization of the store M is also conventional as it operates according to exchange cycles and permanently supplies at ML a signal the condition of which indicates that the store is available for a transfer or exchange operation or that the store is not available for such purposes.
  • a signal the condition of which indicates that the store is available for a transfer or exchange operation or that the store is not available for such purposes.
  • the access call interpretative device is provided with eight inputs, DAO to DA7, through which the processors may request an access to the store by activation of their normal access call lines connected to such inputs.
  • the interpretative device is further provided with eight inputs, HPO to HP7, which are connected to second call lines, i.e. high priority call lines from the processors.
  • each one of the inputs HP is associated with a corresponding input DA as will be described hereinafter. Consequently the interpretative device will handle all of the calls in normal as well as in a high priority condition. This minimizes the equipment necessary and further ensures a straight-through coordination of the handling of both kinds of store access calls, consequently enhancing the efficiency of the system by speeding up the completion of the calls.
  • the normal access call inputs DAO with DA7 are respectively associated to the high priority call inputs HPO to HP7.
  • Each one of the inputs DAO to DA7 is connected to one input in each one of two AND-circuits, SNO and SPO for input DAO, 5N] and SP1 for input DA1, and so forth.
  • AND-circuits HP have their second inputs respectively connected to the HP inputs of the device. This means that, in the concerned example, whenever one input HP is activated, the corresponding input DA also will be activated. This is not imperative, however, and call lines HP could be activated independently, in which condition the circuits 5P would not receive the signals on the inputs DA.
  • OR-circuits 60 to 67.
  • the outputs of said OR- circuits 60 to 67 are respectively connected to activation inputs of one-digit stores, MRO to MR7.
  • the outputs of said stores are connected to control lines CAO to CA7 of the access channels All to A7 of FIG. 1.
  • the outputs of the one-digit stores MR are further simultaneously applied to the input of an inverter stage 10 for a purpose which will be hereinbelow described.
  • the outputs from OR-circuits 60 are applied to a further OR-gate 70. The output of 70 will be activated each time a call for a normal access as well as for a high priority access activates one of the inputs of the device.
  • Each circuit 5P has one of its inputs connected to a bus line VHP from a one-digit store BHP.
  • Each circuit 5N has one of its inputs connected to a bus line VPN from a onedigit store BPN.
  • Said bus line VPN is also connected to the output of inverter stage 10.
  • the conditions of the one-digit stores BPN and BHP are controlled from outputs of a delay line DL. Output a of said delay line, n close proximity to its input, is connected to the reset input of BPN. When in reset condition, BPN blocks the input crcuts 5N. Output d of said delay line is connected to the set input of BPN. When in the set condition, BPN unblocks the input circuits 5N.
  • Output c of said delay line is connected to the set input of BHP.
  • BHP unblocks the input circuits 5P.
  • Ihe above mentioned d output of the delay line DL is connected to the reset input of BHP.
  • BHP blocks the input circuits 5P.
  • the condition of a bistable member is controlled from the outputs a and b of said delay line DL.
  • the output from 75 is directed to inputs of the one-digit stores MR so that, from the activation of output a up to the activation of output b, said onedigt stores MR are maintained in their 1 condition.
  • Each one-digit store conventionally includes an amplifier the output of which is connected back to one input of the store through a circuit which, when activated from the shown output of 75, locks the condition of said amplifier to the condition to which it has been controlled from its actuation input, i.e. the input connected to the concerned one of the OR'circuits 60 to 67.
  • the input of the delay line DL receives an activation pulse when one or the other of the following conditions is satisfied: when both the output of the OR-gate 70 and a signal at an input ML are true," the AND-gate 71 is unblocked and the signal is applied through an OR-circuit 73 to the input of the delay line DL; when both the Output of the OR-gate 70 and the output d of the delay line DL are true, the AND-gate 72 is unblocked and applies, through OR-circuit 73, the signal from d to the input of the delay line DL.
  • an AND-gate 74 issues a signal to the store M wherein it will maintain the output ML at a false level whereas the output d of the delay line would have brought said output ML to the true level.
  • the delay line DL may be adapted, through additionally provided taps, for substantially controlling all the operations in the store M. Normally in such a store, an operation controlling delay line exists. Providing taps for selection, transfer and actuation operations in the store on the delay line DL may avoid the necessity of duplicating the delay lines in a system according to the invention.
  • the access organization is provided for a predetermined hierarchy of the normal access calls, in the absence of high priority access calls.
  • Said hierarchy is defined, in the example shown, by means of inverters such as shown from 11 to 17 at the outputs of the one-digit stores MRO to MR7.
  • inverters such as shown from 11 to 17 at the outputs of the one-digit stores MRO to MR7.
  • I1 inverters
  • I2 the outputs of which are respectively connected to lines CA2 to CA7
  • Said circuit CP is of any well-known kind, for instance a threshold circuit receiving the supply voltage from the mains which, when the amplitude of said voltage decreases to a value lower than its threshold unblocks a gate which applies a battery voltage to said high priority line HPO, said gate and battery constituting the said generator GHP.
  • a large capacity store such as M conventionally operates in a continuous sequence of cycles wherein preferably the time intervals devoted to the selection of its access channels preferably partially overlap the store operative cycles.
  • the delay line DL is provided with a transit time equal to 650 nanoseconds
  • tap b is provided at an interval of 140 nanoseconds from the input or, in other words, from tap a which may illustratively be spaced by 7 nanoseconds from the actual input of the delay line.
  • Tap c is spaced by 440 nanoseconds from the input and, for instance, tap d is spaced by 500 nanoseconds from the input of the delay line.
  • the average length of any pulse issuing from the delay line may be equal to about 60 nanoseconds.
  • the high priority access calls will be serviced during the time intervals wherein ML is false, which will shorten the servicing delay for such calls.
  • Group (A) of the diagrams of FIG. 3 illustratively concerns the case of a normal access call appearing for instance on the input DAI) of FIG. 2, none of the other inputs of the device being activated.
  • This call was initiated during the former cycle of operation of the store and is waiting for service.
  • the tap d of the delay line DL was activated and controlled the one-digit store BNP which has reversed its condition.
  • Such a change of condition necessitated about 10 nanoseconds (in order to simplify the diagrams, such times of change of condition of the one-digit stores in FIG. 2 have not been represented).
  • the voltage on the bus line VPN returns to its true level for unblocking the circuits 5N at the time in stant when ML is true on gate 71.
  • MR() is consequently activated through 5N0, which is then unblocked and through circuits 60, 70, 71 and 73, the delay line DL is activated.
  • the circuits 5N are blocked which inhibits the interfering action of a further call to the device, if any.
  • BPN is reset for preserving th'e circuits 5N in their blocked condition up to the time instant of the cycle whereat tap d is activated.
  • MRO has applied a true level on line CAD, which activates the access channel A0 in the store for servicing the call from UCI). This servicing occurs within a time interval slightly lower than the time interval b after the activation of the delay line, and it is at this time instant b that the store will reset signal ML to a false value.
  • the calling unit UCO will thereafter cancel its call for access to the store.
  • the one-digit store BHP is set but this will not have any result since none of the inputs of the device carries a high priority call signal.
  • BHP is reset and BPN is set. The device is then ready to receive a further call.
  • Group (B) of the diagrams in FIG. 3 concerns a typical example of servicing a high priority access call.
  • Three calls for store access are present: normal access calls on the inputs DAI) and DA1, high priority access call on the input HP2 (DA2 is not shown but assumed to exist as said in the embodiment shown in FIG. 2-it will not exist in a circuit arrangement wherein circuits 5P do not receive the signals DA).
  • ML turns true time instant d of the former operative cycle of the store whereat the circuits SN are unblocked, the one-digit stores MR() and MRl, and casually MR2, are set. Only the line CA() is brought to a true condition as the lines CA1 and CA2 are maintained in a false condition through the inverters l1.
  • MR2 maintains a false level on line VPN and the call DA1 is thus inhibited and must wait the next further cycle of the store to be serviced, time interval d of said further cycle in case HP2 ends prior to said time instant d or, more accurately, prior the time instant c of said high priority call servicing cycle.
  • Group (C) of the diagrams of FIG. 3 concerns the case of two simultaneously high priority access calls on two inputs HPO and HP1 for instance.
  • This example is intended to show that, when two high priority access calls are conflicting, the hierarchy for the normal access calls operates for servicing the high priority access call corresponding to the higher rank in said hierarchy to the high priority access call corresponding to a lower rank in said hierarchy (provided HPO disappeared prior to the time instant c of the cycle wherein HPO/DAI) is being serviced).
  • any further condition of conflicting normal and high priority store access calls may be derived any further condition of conflicting normal and high priority store access calls.
  • the activations at HP are not imperatively concurring with corresponding activations at DA, the servicing of any high priority call cannot be initiated in the absence of a normal access call condition but such a normal access call will always be present because in the numerical data processing system for which the present invention is provided, one such normal access call exists at each and any operative cycle of the general large capacity store.
  • the buffer store is of a capacity equal to n addresses, from l to n and for instance consists of a shift register.
  • the transfers of data, or exchanges, are made in a read-in as well as in a read-out operation by filling the buffer up to an address j which may be selected, in an embodiment according to the present invention as a criterium for initiating a high priority access call because, as soon as this level j is exceeded in the buffer store, there is a risk of information loss if the transfer operation cannot be speeded up, as well from the store to the peripheral or from the peripheral to the store M.
  • the high priority access call forming circuit then merely consists of a gate GHP controlled from the j output of the decoder circuit DMTof the buffer store MT for application of a battery voltage to the calling line HP7.
  • a condiiton i.e. the j output to a true level
  • Such a multiplexing unit actually includes two exchange units UEl and UE2 which partake the store access call lines DA2 (normal) and HP2 (high priority).
  • Unit UEl connects the three peripheral equipments P1, P2 and P3 to the general store M and unit UEZ similarly connects the three peripheral equipments P4, P5 and P6 to the said store M.
  • Such connections are made through connecting units UL1, ULZ and ULS for the peripheral equipments P1, P2 and P3, and through connecting units UL4, ULS and UL6 for the peripheral equipment P4, P5 and P6.
  • Each one of the exchange units UEl and UEZ rst includes three channels respectively attributed to the connecting units. These channels are detailed for one of the exchange units in part (A) of FIG. 4.
  • FIG. 4 details the circuit arrangement generating the normal access calls DA and in part (B) of said ligure, it details the circuit arrangement generating the high priority access calls in cooperation with the connecting units UL connected to the exchange unit concerned.
  • In each of the connecting units UL is provided a circuit which is the same kind as the one above described for a direct exchange unit.
  • the three signals are applied, in a logical OR relation, to the actual high priority access generator means of the multiplexing unit, as shown at HPL.
  • the three channels of an exchange unit issue a group of three signals D, FIG. 1, and a further group of three signals applied at Ed on the high priority access call generator (FIG. 4) (B)).
  • the three channels C1, C2 and C3 are only shown in block form.
  • Stich channels issue, when necessary and in a conventional form, signals requesting a normal access to the store, DALI, DAL2, DAL3 to respective one-digit stores MV1, MVZ, MV3.
  • the outputs of said one-digit stores are respectively D1, D2 and D3. They are connected to inputs of a common logical circuit 80 which delivers, inter alia, the normal access call DA when at least one of the one-digit stores MV is activated.
  • a further signal Rz is applied back to the channel from which originated the request of a store access call through a transfer stage controlled to conduction from the onedigit store MV which has been activated.
  • MV1 controls the transfer stage 86, for channel C1
  • MV2 controls the transfer stage 87 for channel C2
  • MV3 controls the transfer stage 88 for channel C3.
  • Application of a signal Rz to a channel turns it to occupation.
  • the outputs of the three stages 86, 87 and 88 are mixed to form a signal AP denoting the occupation of the access call line from UEl to the other exchange unit UEZ.
  • an OR-circuit 81 receives a signal HPL consisting of the addition of the high priority access request signals from the connecting units ULI, UL2 and UL3, and also receives the output signals of four AND- gates 82 to 85 the inputs of which are derived as follows:
  • Three signals D1, D2 and D3 are derived from the outputs of the one-digit stores MV1, MVZ and MV3 from an inversion at ID of the output conditions of said stores.
  • a signal denoting whether or not lines DAZ and (or) HP2 are occupied by the other exchange unit UEZ is applied through input AF2.
  • AND-gate 82 receives the three signals D1, D2 and D3;
  • AND-gate 83 receives the three signals D1, D2 and APZ;
  • AND-gate 84 receives the three signals D1, D3 and AF2;
  • AND gate 85 receives the three signals Dl, D3 and APZ.
  • circuit 82 issues a signal requesting to 81 the generation of a high priority access call signal in order to take such a conflict into due account from an acceleration of the exchange between the ooncerned peripherals and the store M.
  • circuit 83 which applies to 81 a signal requesting a high priority access call, so that the transfer will be accelerated between UEZ and the store M.
  • each one of the channels C1, C2 and C3 may conventionally activate a further ouput Edl, Ed2 and Ed3 respectively. Activation of one of these outputs indicates the necessity of two successive transfers, in or from the store M, for appropriately collecting the data.
  • the outputs Ed are applied to the OR-circuit 81 for generating therefrom a high priority access call signal HP.
  • the system is so provided as to ensure servicing of the high priority access calls without waiting for the clearance of the store M, and whereas further the access channels are available both for normal and for high priority calls, it must be understood that any other embodiment wherein one, or both, of such particular conditions is not satisfied though having recourse to the described high priority access scheme, remains within the field and scope of the invention.
  • high priority access call lines could, if desired, be associated only with part of the processors without departing from the spirit of the invention.
  • each processing unit provides a first access request signal in a first operative condition thereof and a second access request signal in a second operative condition thereof, the combination comprising:
  • each one-digit store of the said first and second pluralities having an output connected to an access activation line to said common apparatus;
  • each one of said two pluralities of one-digit stores for inhibiting from an activated output of a one-digit store the activation of the access activation lines connected to other one-digit stores which are settable from controllable circuits receiving access request signals from processing units of lower priority in said hierarchy than the processing unit from an access request signal of which said one-digit store output is activated;
  • monitoring cycle signal generator means controlling, to signal transmitting condition, the controllable circuits of said first plurality during a first time interval of a monitoring cycle and controlling, to signal transmitting condition, the controllable circuits of said second plurality during a second time interval of a monitoring cycle;
  • each processing unit provides a first access request signal in a first operative condition thereof and a second access request signal in a second operative condition thereof, the combination comprising:
  • each one-digit store having an output connected to an access activation line to said common apparatus
  • monitoring cycle signal generator means controlling, to signal transmitting condition, the controllable circuits of said first plurality during a first time interval of a 10 monitoring cycle and controlling, to signal transmitting condition, the controllable circuits of said second plurality during a second time interval of a monitoring cycle;
  • monitoring cycle signal generator means comprises cycle initiating first and second means respectively actuated during the said rst and second time intervals, said first means being responsive to the coexistence of an activated output condition from the said first plurality of controllable circuits and of an availability signal from the said common apparatus, said second means being responsive to an activated output condition from the said second plurality of controllable circuits, and means resetting the onedigit stores at a time instant intermediate between said first and second time intervals,
  • said monitoring cycle signal generator means comprises first and second bistable members respectively controlling when actuated a signal transmitting condition of the controllable circuits of the said first and second pluralities, means applying to the first bistable member an actuation signal at a time instant near the end of a monitoring cycle and a reset signal at a time instant next to the activation of said cycle initiating first means, and means applying to the second bistable member an actuation signal at a time instant delayed over the said resetting time instant of the one-digit stores and a reset signal at a time instant near the end of a monitoring cycle, and wherein said means inhibiting the controllable circuits of the first plurality comprises inverter means receiving an OR association of the outputs of the one-digit stores and having its output connected to the output of the said first bistable member.
  • monitoring cycle signal generator means comprises a delay line having an input connected to the outputs of said cycle initiating first and second means and distributed tapped outputs along its length.
  • each processing unit when in the said second operative condition provides both the said first and second access request signals and wherein each controllable circuit of the said second plurality comprises an AND-gate circuit for reception of the said first and second access request signals from a processing unit.
  • a numerical data processing system comprising in combination:
  • a large capacity information store including a plurality of information exchange access channels and a plurality of store access calling lines for selective activation of the said channels;
  • first and second groups of controllable circuits having their inputs respectively connected to said first access request signal lines and to said second access request signal lines;
  • a plurality of one-digit stores having their actuation inputs respectively connected to the outputs of the said controllable circuits and having their outputs respectively connected to the said store access calling lines; means inhibiting, from an activation of a one-digit store, the activations of the store access calling lines connected to other one-digit stores of a lower priority in a hierarchy of priorities of the said access channels and calling lines; cyclically operated control means respectively activating said first and second groups of controllable circuits during a rst and a second time interval of an operative cycle thereof and resetting the one-digit stores at a time instant intermediate said tirst and second time intervals; means inhibiting activation of the circuits of the first group in an operative cycle following an operative cycle wherein a one-digit store has been activated from an output of a controllable circuit of said second group during the said second time interval; and
  • one at least of the said processor units is a program-operated numerical computer
  • one at least of the said processor units is an exchange multiplexing unit for a plurality of peripheral equipments
  • one at least of the said processor units is a direct exchange unit for a single peripheral equipment
  • program-operated computer units are connected to access channels of a higher priority than the access channels to which are Connected exchange multiplexing units which, in turn, are connected to access channels of a higher priority than the access channels to which are connected the direct exchange units.
  • each exchange multiplexing unit comprises as many channels as there are peripheral equipments connected thereto, tirst and second access request lines from each channel respectively activated in a first and a second operative condition in said channel and an exchange maintenance request line from each channel activable during an exchange condition of said channel, a priority hierarchy determining arrangement having its inputs connected to the said rst access request lines from said channels and having its output connected to the first access request signal line of the process or unit, means responsive to simultaneous activations of the rst access request lines from said channels, means responsive to an activation of said second access request lines from said channels and means responsive to the OR-combination of said simultaneous activation responsive means, of said second access request line activation responsive means and of activation of an exchangemaintenance request line and having its output connected to the second access request line of the said processor unit.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
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US27779D 1969-07-31 1972-11-09 Numerical data processing system Expired USRE27779E (en)

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FR2465269B1 (fr) * 1979-09-12 1985-12-27 Cii Honeywell Bull Selecteur de demandes asynchrones dans un systeme de traitement de l'information
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
US5341510A (en) * 1987-05-01 1994-08-23 Digital Equipment Corporation Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor
US4980854A (en) * 1987-05-01 1990-12-25 Digital Equipment Corporation Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
US4949239A (en) * 1987-05-01 1990-08-14 Digital Equipment Corporation System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
US4941083A (en) * 1987-05-01 1990-07-10 Digital Equipment Corporation Method and apparatus for initiating interlock read transactions on a multiprocessor computer system
US4858116A (en) * 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
JPS6491261A (en) * 1987-09-23 1989-04-10 Ibm Data processing system and access
US5115507A (en) * 1987-12-23 1992-05-19 U.S. Philips Corp. System for management of the priorities of access to a memory and its application
FR2625341A1 (fr) * 1987-12-23 1989-06-30 Labo Electronique Physique Systeme de gestion des priorites d'acces a une memoire et son application

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DE2037811C3 (de) 1973-09-13
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FR2056894A1 (de) 1971-05-07
GB1269301A (en) 1972-04-06

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