USB422695I5 - - Google Patents

Info

Publication number
USB422695I5
USB422695I5 US422695DD USB422695I5 US B422695 I5 USB422695 I5 US B422695I5 US 422695D D US422695D D US 422695DD US B422695 I5 USB422695 I5 US B422695I5
Authority
US
United States
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication date
Publication of USB422695I5 publication Critical patent/USB422695I5/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
US422695D 1964-12-31 Pending USB422695I5 (nl)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US42269564A 1964-12-31 1964-12-31
US425542A US3468728A (en) 1964-12-31 1965-01-14 Method for forming ohmic contact for a semiconductor device
US660528A US3390025A (en) 1964-12-31 1967-08-14 Method of forming small geometry diffused junction semiconductor devices by diffusion

Publications (1)

Publication Number Publication Date
USB422695I5 true USB422695I5 (nl) 1900-01-01

Family

ID=27411372

Family Applications (4)

Application Number Title Priority Date Filing Date
US422695D Pending USB422695I5 (nl) 1964-12-31
US311264D Pending USB311264I5 (nl) 1964-12-31
US425542A Expired - Lifetime US3468728A (en) 1964-12-31 1965-01-14 Method for forming ohmic contact for a semiconductor device
US660528A Expired - Lifetime US3390025A (en) 1964-12-31 1967-08-14 Method of forming small geometry diffused junction semiconductor devices by diffusion

Family Applications After (3)

Application Number Title Priority Date Filing Date
US311264D Pending USB311264I5 (nl) 1964-12-31
US425542A Expired - Lifetime US3468728A (en) 1964-12-31 1965-01-14 Method for forming ohmic contact for a semiconductor device
US660528A Expired - Lifetime US3390025A (en) 1964-12-31 1967-08-14 Method of forming small geometry diffused junction semiconductor devices by diffusion

Country Status (6)

Country Link
US (4) US3468728A (nl)
DE (1) DE1514915C2 (nl)
FR (1) FR1462032A (nl)
GB (1) GB1124080A (nl)
NL (1) NL6517007A (nl)
SE (1) SE313120B (nl)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1188879A (en) * 1967-12-13 1970-04-22 Matsushita Electronics Corp Planar Transistor
NL161617C (nl) * 1968-06-17 1980-02-15 Nippon Electric Co Halfgeleiderinrichting met vlak oppervlak en werkwijze voor het vervaardigen daarvan.
NL6907227A (nl) * 1969-05-10 1970-11-12
US3634203A (en) * 1969-07-22 1972-01-11 Texas Instruments Inc Thin film metallization processes for microcircuits
US3660157A (en) * 1969-08-18 1972-05-02 Computervision Corp Enhanced contrast semiconductor wafer alignment target
US3766446A (en) * 1969-11-20 1973-10-16 Kogyo Gijutsuin Integrated circuits comprising lateral transistors and process for fabrication thereof
US3653898A (en) * 1969-12-16 1972-04-04 Texas Instruments Inc Formation of small dimensioned apertures
US3713911A (en) * 1970-05-26 1973-01-30 Westinghouse Electric Corp Method of delineating small areas as in microelectronic component fabrication
JPS49100964A (nl) * 1973-01-31 1974-09-24
US3919005A (en) * 1973-05-07 1975-11-11 Fairchild Camera Instr Co Method for fabricating double-diffused, lateral transistor
US3904454A (en) * 1973-12-26 1975-09-09 Ibm Method for fabricating minute openings in insulating layers during the formation of integrated circuits
US4337475A (en) * 1979-06-15 1982-06-29 Gold Star Semiconductor, Ltd. High power transistor with highly doped buried base layer
FR2460037A1 (fr) * 1979-06-22 1981-01-16 Thomson Csf Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur
US4243435A (en) * 1979-06-22 1981-01-06 International Business Machines Corporation Bipolar transistor fabrication process with an ion implanted emitter
JPS56110229A (en) * 1980-02-06 1981-09-01 Nec Corp Manufacture of semiconductor device
US4326332A (en) * 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
US4462041A (en) * 1981-03-20 1984-07-24 Harris Corporation High speed and current gain insulated gate field effect transistors
US4454004A (en) * 1983-02-28 1984-06-12 Hewlett-Packard Company Utilizing controlled illumination for creating or removing a conductive layer from a SiO2 insulator over a PN junction bearing semiconductor
JP2834797B2 (ja) * 1989-10-25 1998-12-14 株式会社リコー 薄膜形成装置
CN102310602B (zh) * 2010-06-30 2014-03-26 鸿富锦精密工业（深圳）有限公司 铝塑复合结构及其制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL121810C (nl) * 1955-11-04
DE1287009C2 (de) * 1957-08-07 1975-01-09 Western Electric Co. Inc., New York, N.Y. (V.St.A.) Verfahren zur herstellung von halbleiterkoerpern
NL253834A (nl) * 1959-07-21 1900-01-01
US3258606A (en) * 1962-10-16 1966-06-28 Integrated circuits using thermal effects
US3245794A (en) * 1962-10-29 1966-04-12 Ihilco Corp Sequential registration scheme
US3300339A (en) * 1962-12-31 1967-01-24 Ibm Method of covering the surfaces of objects with protective glass jackets and the objects produced thereby
US3165430A (en) * 1963-01-21 1965-01-12 Siliconix Inc Method of ultra-fine semiconductor manufacture
US3246214A (en) * 1963-04-22 1966-04-12 Siliconix Inc Horizontally aligned junction transistor structure

Also Published As

Publication number Publication date
US3390025A (en) 1968-06-25
DE1514915C2 (de) 1974-01-03
USB311264I5 (nl) 1900-01-01
NL6517007A (nl) 1966-07-04
GB1124080A (en) 1968-08-21
SE313120B (nl) 1969-08-04
DE1514915B1 (de) 1971-03-25
US3468728A (en) 1969-09-23
FR1462032A (fr) 1966-12-09

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