US9859885B2 - Electronic circuit and semiconductor device - Google Patents
Electronic circuit and semiconductor device Download PDFInfo
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- US9859885B2 US9859885B2 US15/060,660 US201615060660A US9859885B2 US 9859885 B2 US9859885 B2 US 9859885B2 US 201615060660 A US201615060660 A US 201615060660A US 9859885 B2 US9859885 B2 US 9859885B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
- G01S15/88—Sonar systems specially adapted for specific applications
- G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
- G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
- G01S15/8909—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration
- G01S15/8915—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration using a transducer array
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
- G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
- G01S7/52019—Details of transmitters
- G01S7/5202—Details of transmitters for pulse systems
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
- G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
- G01S7/5205—Means for monitoring or calibrating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
Definitions
- the present invention relates to an electronic circuit and a semiconductor device and, more particularly, to an electronic circuit and a semiconductor device that operate by using a plurality of types of power supply voltages.
- Various kinds of digital circuits such as a memory or a microprocessor are integrated on a semiconductor device. Further, the semiconductor device is provided with a power-on reset circuit so as to prevent malfunction from occurring in such digital circuits when a power supply voltage is supplied thereto.
- the power-on reset circuit detects whether or not the power supply voltage supplied to a digital circuit (internal circuit) integrated on the semiconductor device exceeds or not a predetermined voltage value (specified voltage value) suitable for operating the digital circuit.
- a digital circuit internal circuit
- a predetermined voltage value specified voltage value
- the power-on reset circuit resets, e.g., a flip-flop circuit constituting the digital circuit to an initial state to prevent the flip-flop circuit from being in an indefinite state. Thereafter, the power-on reset circuit cancels the reset, and the digital circuit resumes its operation. With this configuration, the digital circuit can be prevented from malfunctioning when the power supply voltage rises.
- a digital circuit that operates using a plurality of types of power supply voltages, i.e., a plurality of different power supply voltages is provided with a plurality of level conversion circuits for signal propagation therein.
- malfunction may occur when any one of the plurality of power supply voltages is lowered.
- the power-on reset circuit cannot sufficiently prevent malfunction of the digital circuit.
- JP- 2005-102086-A describes, as the digital circuit, a level shift circuit.
- a semiconductor device is used for an Diagnostic Ultrasound System.
- the semiconductor device used for Diagnostic Ultrasound System there can be exemplified a so-called “pulser” semiconductor device, which is a semiconductor device that outputs a drive signal to be supplied to an ultrasound oscillator so as to make the ultrasound oscillator generate an ultrasound wave.
- the Diagnostic Ultrasound System is provided with a receiver circuit that receives a reflected wave of the generated ultrasound wave through the ultrasound oscillator.
- a high voltage of, e.g., up to about ⁇ 100 V is applied to the ultrasound oscillator.
- a transmitter signal to be supplied to the pulsar semiconductor device is a low voltage of, e.g., about 3.3 V. That is, the pulser semiconductor voltage is required to form a high voltage drive signal of, e.g., up to about ⁇ 100 V based on the low voltage transmitter signal of about 3.3 V.
- the pulser semiconductor device performs level conversion (hereinafter, referred to also as “level shift”) of the low voltage transmitter signal to form the high voltage drive signal.
- level shift a potential of the high voltage drive signal is changed to a positive (+) side and a negative ( ⁇ ) side with respect to a ground voltage (reference voltage).
- a plurality of types of voltages including positive and negative voltages are supplied to the pulser semiconductor device for the level conversion. That is, the pulse r semiconductor device uses a plurality of types of voltages (including the positive and negative polarities) having different potentials from one another to perform level conversion of the transmitter signal a plurality of times to thereby convert the low voltage transmitter signal to high voltage drive signal.
- the pulsar semiconductor device is further provided. with an internal circuit that performs processing necessary to form the drive signal based on the transmitter signal.
- the processing to be performed by the internal circuit includes, e.g., decoding.
- a minute abnormality occurs in a power supply circuit that supplies a plurality of types of voltages to cause a voltage being supplied to the pulser semiconductor device to be changed, malfunction may occur in the internal circuit. If the malfunction occurs, a high voltage of up to about ⁇ 100 V is applied at an unexpected timing, which may damage the pulser semiconductor device. Further, if the malfunction occurs, a high voltage is applied to a receiver circuit or the like, which may damage it.
- an unintended voltage drop may occur in a power supply voltage to be supplied to the pulser semiconductor device.
- a component constituting the Diagnostic Ultrasound System such as the pulser semiconductor device or peripheral components (receiver circuit, etc.) thereof may be damaged due to the malfunction. If the component is broken, development of the Diagnostic Ultrasound System may be delayed.
- JP-2005-102086-A describes a technology that prevents, in a level shift circuit that performs level conversion between different power supply voltages, a through current in a latch-type level shift circuit under a specific state where an operating power supply voltage for the internal circuit is lowered to thereby prevent a reduction in electric power and occurrence of an indefinite state.
- JP-2005-102086-A it is demanded that a power supply voltage other than the operating power supply voltage for the internal circuit be supplied sufficiently.
- necessity of use of a plurality of operating power supply voltages and prevention of malfunction which may occur due to unintended lowering of the power supply voltage are not taken into consideration.
- An object of the present invention is to provide an electronic circuit and a semiconductor device that operate using a plurality of types of power supply voltages, which. are capable of preventing occurrence of malfunction.
- an electronic circuit includes a first level shift circuit, a second level shift circuit, a third level shift circuit, a fourth level shift circuit, an internal circuit, a high voltage circuit, a first transistor, a second transistor, a first protective circuit, and a second protective circuit.
- the first level shift circuit is supplied with a reference voltage, a first voltage having a first potential on a first polarity side with respect to the reference voltage, and a second voltage having a second potential higher than the first potential, is supplied with an input signal whose voltage is changed between the reference voltage and the first voltage, and outputs a first output signal obtained by level-shifting the input signal.
- the internal circuit is supplied with the reference voltage and the second voltage, receives the first output signal, and outputs second and third output signals according to the first output signal.
- the second level shift circuit is supplied with the reference voltage, the second voltage, and a third voltage having a third potential on a second polarity side with respect to the reference voltage and outputs a fourth output signal obtained by level-converting the third output signal.
- the high voltage circuit is supplied with the reference voltage, the second voltage, the third voltage, the fourth voltage, and the fifth voltage, controls conduction of the first transistor according to the second output signal, and controls conduction of the second transistor according to the fourth output signal.
- the first protective circuit controls the internal circuit such that the internal circuit outputs the second and third output signals having levels that make the respective first and second transistors non-conductive when an absolute value of a potential of at least one of the first, second, and third voltages becomes equal to or less than a predetermined value.
- the second protective circuit controls the second level shift circuit so that the second transistor is made non-conductive by the fourth output signal when the absolute value of the potential of the second voltage becomes equal to or less than a predetermined value.
- the internal circuit forms the second and third output signals having levels that make the respective first and second transistors non-conductive.
- the fourth output signal having a level that makes the second transistor non-conductive is output from the second shift circuit that converts the level of the third output signal.
- the first and second transistors are made non-conductive.
- the first transistor is made non-conductive by the second output signal from the internal circuit, and the second transistor is made non-conductive by the fourth output signal from the second level shift circuit.
- the first and second transistors are made non-conductive, thereby making it possible to prevent the fourth and fifth voltages which are high voltages from being short-circuited through these transistors. Further, it is possible to prevent occurrence of such malfunction that the fourth voltage or fifth voltage which is a high voltage is output from the electronic circuit.
- the second protective circuit controls the second level shift circuit to output the fourth output signal having a level that makes the second transistor non-conductive.
- an electronic circuit operates using, as a power supply voltage, at least a first positive low-voltage power supply, a second positive low-voltage power supply providing a voltage higher than that of the first positive low-voltage power supply, a first negative low-voltage power supply, a first positive high-voltage power supply providing a voltage higher than that of the second positive low-voltage power supply, and a first negative high-voltage power supply providing a voltage lower than that of the first negative low-voltage power supply.
- the electronic circuit includes first and second level shift circuits, an internal circuit, a high voltage driver, first, second, third, and fourth reset circuits, and a logic circuit.
- the first level shift circuit converts an input signal having a voltage level of the first positive low-voltage power supply into an output signal having a voltage level of the second positive low-voltage power supply.
- the internal circuit operates using the second positive low-voltage power supply, supplied with the output signal from the first level shift circuit, and forms first and second output signals according to the supplied output signal.
- the second level shift circuit converts a voltage level of the second output signal from the voltage level of the second positive low-voltage power supply to that of the first negative low-voltage power supply.
- the high voltage driver receives the first output signal and an output signal from the second level shift circuit and outputs a signal having a voltage level of the first positive high-voltage power supply or first negative low-voltage power supply.
- the first reset circuit is supplied with the first positive low-voltage power supply, second positive low-voltage power supply, and ground voltage and outputs a reset signal whose high level corresponds to the voltage level of the second positive low-voltage power supply and whose low level corresponds to the voltage level of the ground voltage when the voltage of the first positive low-voltage power supply becomes equal to or less than a predetermined value.
- the second reset circuit is supplied with the second positive low-voltage power supply and. ground voltage and outputs a reset signal whose high level corresponds to the voltage level of the second positive low-voltage power supply and whose low level corresponds to the voltage level of the ground voltage when the voltage of the second positive low-voltage power supply becomes equal to or less than a predetermined value.
- the third reset circuit is supplied with the second positive low-voltage power supply, first negative low-voltage power supply, and ground voltage and outputs a reset signal whose high level corresponds to the voltage level of the second positive low-voltage power supply and whose low level corresponds to the voltage level of the ground voltage when an absolute value of the voltage of the first negative low-voltage power supply becomes equal to or less than a predetermined value.
- the fourth reset circuit is supplied with the second positive low-voltage power supply, first negative low-voltage power supply, and ground voltage and outputs a reset signal whose high level corresponds to the voltage level of the ground voltage and whose low level corresponds to the voltage level of the first negative low-voltage power supply when the voltage of the second positive low-voltage power supply becomes equal to or less than a predetermined value.
- the logic circuit receives the reset signals from the first, second, and third reset circuits and puts the internal circuit into a predetermined state when one of the first positive low-voltage power supply, second positive low-voltage power supply, and first negative low-voltage power supply becomes equal to or less than a predetermined value.
- the second level shift circuit is put into a predetermined state by the reset signal from the fourth reset circuit.
- the internal circuit When the absolute value of the voltage of at least the first positive low-voltage power supply, second positive low-voltage power supply, and first negative low-voltage power supply becomes equal to or less than a predetermined value, the internal circuit is put into a predetermined state. Further, when the absolute value of the voltage of the second positive low-voltage power supply becomes equal to less than a predetermined value, the second level shift circuit is put into a predetermined state. When the internal circuit is put into a predetermined state, the high voltage driver does not output the voltage levels of the first positive high-voltage power supply and first negative high-voltage power supply.
- an electronic circuit and a semiconductor device that operate using a plurality of types of power supply voltages, which are capable of preventing occurrence of malfunction.
- FIG. 1 is a block diagram illustrating a basic configuration of a transmitter circuit according to a first embodiment
- FIG. 2 is a block diagram illustrating a configuration of the transmitter circuit according to the first embodiment
- FIG. 3 is a circuit diagram illustrating a configuration of a level shift circuit according to the first embodiment
- FIG. 4 is a block diagram illustrating a configuration of a transmitter circuit according to a second embodiment
- FIG. 5 is a block diagram illustrating a configuration of a transmitter circuit according to a third embodiment
- FIG. 6 is a block diagram schematically illustrating a configuration of an Diagnostic Ultrasound System according to the first embodiment.
- FIG. 7 is a block diagram illustrating a decoder according to the first embodiment.
- a pulser semiconductor device is exemplified, but not limited thereto. Further, it can be considered that the pulser semiconductor device is formed by an electronic circuit such as a transmitter circuit which is formed on one semiconductor chip by a known semiconductor manufacturing technology.
- FIG. 6 is an exemplary block diagram illustrating a configuration of an Diagnostic Ultrasound System according to a first embodiment.
- a medical Diagnostic Ultrasound System is taken as an example.
- the Diagnostic Ultrasound System includes a pulser semiconductor device CHP, receiver circuits RCV 1 to RCVn, and ultrasound oscillators HB 1 to HBn.
- the pulser semiconductor device CHP includes a plurality of (1 to n) transmitter units and a plurality of (1 to n) transmitter and receiver separation switches.
- One channel includes one transmitter unit and one transmitter and receiver separation switch, so, the pulser semiconductor device of FIG. 6 includes n channels CH 1 to CHn.
- the plurality of transmitter units and plurality of transmitter and receiver separation switches are formed on one semiconductor chip by a known semiconductor manufacturing technology, although not especially limited. thereto, and are sealed in one package, although not especially limited thereto.
- FIG. 6 illustrates a state where the pulser semiconductor device CHP is sealed in the package. In FIG.
- reference symbols TS, TL, TD, TG, TP, TN, TR 1 to TRn, TI 1 to TIn, and TU 1 to TUn are each an external terminal provided in the package.
- the above external terminals serve as external terminals of the pulser semiconductor device CHP.
- the external terminals TS, TL, TD, TC, TP and TN are each a power supply terminal.
- the external terminals TI 1 to TIn are each an input terminal to which transmitter signals I 1 to In are supplied from a not illustrated processor.
- the external terminals TU 1 to TUn are each an input/output terminal used for output of a drive signal and input of a receiver signal.
- the external terminals TR 1 to TRn are each an output terminal that outputs the receiver signal input to each of the input/output terminals TU 1 to TUn.
- Different types of power supply voltages are supplied from a not illustrated power supply circuit to, respectively.
- the power supply voltages supplied to the power supply terminals TS, TL, TD, TG, TP and TN are supplied in common to the plurality of transmitter units.
- the transmitter units operate using the plurality of different types of power supply voltages supplied thereto as their operating power supply voltages, respectively.
- the input terminals TI 1 to TIn one-to-one correspond to the channels CH 1 to CHn.
- the input/output terminals TU 1 to TUn and output terminals TR 1 to TRn each one-to-one correspond to the channels CH 1 to CHn.
- the channel CH 1 corresponds to the input terminal TI 1 , input/out terminal TU 1 , and output terminal TR 1 .
- the channels CH 1 to CHn have the same configuration, although not limited thereto.
- the channel CH 1 includes the transmitter unit and a transmitter and receiver separation switch RTC 1 , the transmitter unit having a transmitter circuit HDV 1 and a separation circuit DVD 1 .
- the channels CH 2 to CHn are configured similarly.
- FIG. 6 schematically illustrates a channel CHn including a transmitter unit having a transmitter circuit HDVn and a separation circuit DVDn and a transmitter and receiver separation switch RTCn, in addition to the channel CH 1 .
- Inputs of the respective receiver circuits RCV 1 to RCVn serving as peripheral components of the pulser semiconductor device CHP are connected respectively to the output terminals TR 1 to TRn of the pulser semiconductor device CHP.
- the receiver circuits RCV 1 to RCVn amplify the receiver signals from the respective output terminals TR 1 to TRn and supply the resultant receiver signals to a not illustrated processor as output signals O 1 to On.
- the transmitter signal I 1 is supplied from a not illustrated processor to the input terminal TI 1 .
- the transmitter signal I 1 supplied to the input terminal TI 1 is level-converted from a low voltage to a high voltage by the transmitter circuit HDV 1 in the channel CH 1 .
- the level-converted signal is then output, as a drive signal, from the input/output terminal TU 1 through the separation circuit DVD 1 .
- the input/output terminal TU 1 is connected with one terminal of the ultrasound oscillator HB 1 (the other terminal of the ultrasound oscillator HB 1 is connected to a ground voltage GND).
- a voltage of the drive signal to be output from the input/output terminal TU 1 is periodically changed, according to the transmitter signal I 1 , to a positive (first polarity) side and a negative (second polarity) side with respect to the ground voltage GND.
- the ultrasound oscillator HB 1 generates an ultrasound wave.
- the generated ultrasound wave is irradiated to an object to be diagnosed, and a reflected wave from the object to be diagnosed is transmitted to the ultrasound oscillator HB 1 .
- the ultrasound oscillator HB 1 supplies a detection signal corresponding to the received reflected wave to the input/output terminal TU 1 as a receiver signal.
- the transmitter and receiver separation switch RTC 1 is made non-conductive upon generation of the ultrasound. wave to electrically separate the input/output terminal TU 1 and output terminal TR 1 .
- the transmitter and receiver separation switch RTC 1 upon detection of the reflected wave, the transmitter and receiver separation switch RTC 1 is put into a conductive state.
- the receiver signal supplied to the input/output terminal TU 1 is transmitted to the output terminal TR 1 through the transmitter and receiver separation switch RTC 1 .
- the receiver signal transmitted to the output terminal TR 1 is amplified by the receiver circuit RCV 1 and output as the output signal O 1 .
- a not illustrated processor performs diagnosis based on the transmitter signal I 1 supplied to the input terminal TI 1 and output signal O 1 .
- the channels CH 2 to CHn each perform the same operation, and the diagnosis is performed in the same way as in the channel CH 1 .
- the pulser semiconductor device CHP has the transmitter circuits HDV 1 to HDVn each transmitter the drive signal for driving the corresponding ultrasound oscillator HB 1 .
- the drive signal to be transmitted is a voltage pulser generally having an amplitude of up to ⁇ 100 V.
- the reflected wave generated by irradiation of the ultrasound wave generated by each of the ultrasound oscillators HB 1 to HBn is converted into an electrical signal by each of the ultrasound oscillators HB 1 to HBn, and the obtained electrical signal is amplified by each of the receiver circuits RCV 1 to RCVn.
- each of the receiver circuits RCV 1 to RCVn operates using a low voltage power supply as a power supply voltage, receives a receiver signal having a very small voltage amplitude, and amplitudes the receiver signal.
- the transmitter circuits HDV 1 to HDVn each output a drive signal having a voltage as high as ⁇ 100 V and peripheral components which are low voltage components like the receiver circuits RCV 1 to RCVn are connected to each. other through the transmitter and receiver separation switches RTC 1 to RTCn.
- the peripheral components may be damaged, which may lead to a serious problem such as breaking.
- the transmitter circuits HDV 1 to HDVn have the same configuration and, thus, only the transmitter circuit HDV 1 will be described, and descriptions of other transmitter circuits HDV 2 to HDVn will be omitted.
- FIG. 1 is a block diagram illustrating a basic configuration of the transmitter circuit HDV 1 according to the first embodiment.
- the separation circuit DVD 1 is also illustrated in FIG. 1 , so that the configuration illustrated in FIG. 1 can be regarded as the transmitter unit illustrated in FIG. 6 .
- the transmitter circuit HDV 1 includes a high voltage driver block (high voltage driver) 2 that outputs a high voltage drive signal and a high voltage driver control block 1 that controls the high voltage driver 2 based on the transmitter signal supplied to the input terminal TI 1 .
- high voltage driver high voltage driver
- the high voltage driver control block 1 is connected to the power supply terminals TD, TL, TG and TS, and the high voltage driver 2 is connected to the power supply terminals TD, TG, TS, TP and TN.
- the ground voltage GND (reference voltage) is supplied to the power supply terminal TG.
- a positive power supply voltage VLL with respect to the ground voltage GND is supplied to the power supply terminal TL, and a positive power supply voltage VDD with respect to the ground voltage GND is supplied to the power supply terminal TD.
- a negative power supply voltage VSS with respect to the ground voltage GND is supplied to the power supply terminal TS.
- a positive power supply voltage VPP with respect to the ground voltage GND is supplied to the power supply terminal TP, and a negative power supply voltage VNN with respect to the ground voltage GND is supplied to the power supply terminal TN.
- a voltage (potential) of the positive power supply voltage VDD is higher than a voltage of the positive power supply voltage VLL, and a voltage of the positive power supply voltage VPP is higher than a voltage of the positive power supply voltage VDD.
- An absolute value of a voltage (potential) of the negative power supply voltage VNN is larger than an absolute value of a voltage of the negative power supply voltage VSS.
- the power supply voltages assume the following values. Assuming that the ground voltage GND is 0 V, a voltage value of the power supply voltage VLL is +2.5 V to +3.3 V, a voltage value of the power supply voltage VDD is +5 V, a voltage value of the power supply voltage VSS is ⁇ 5 V, a voltage value of the power supply voltage VPP is 0 V to +100 V, and a voltage value of the power supply voltage VNN is ⁇ 100 V to 0 V.
- the absolute values of the power supply voltages VPP and VNN are larger than the absolute values of the power supply voltages VLL, VDD, and VSS.
- the power supply voltage VLL is sometimes referred to as a first positive low voltage power supply
- power supply voltage VDD is as a second positive low voltage power supply
- power supply voltage VSS is as a first negative low voltage power supply
- power supply voltage VPP is as a first positive high voltage power supply
- power supply voltage VNN is as a first negative high voltage power supply.
- the ground voltage GND is sometimes referred to as a reference voltage.
- the power supply voltage VLL is sometime referred to as a first voltage having a first potential on the positive (first polarity) side with respect to the reference voltage (ground voltage GND)
- power supply voltage VDD is as a second voltage having a second potential on the positive side with respect to the reference voltage
- power supply voltage VSS is as a third voltage having a third potential on the negative side with respect to the reference voltage.
- the power supply voltage VPP is sometimes referred to as a fourth voltage having a fourth potential on the positive side with respect to the reference voltage
- power supply voltage VNN is as a fifth voltage having a fifth potential on the negative side with respect to the reference voltage.
- FIG. 1 corresponds to FIG. 6 , only one input terminal TI 1 is illustrated in FIG. 1 .
- two input terminals are provided.
- the two input terminals are referred to as input terminals TI 1 - 1 and TI 1 - 2 , respectively.
- transmitter signal Din 1 and Din 2 are supplied to the input terminals TI 1 - 1 and TI 1 - 2 , respectively.
- the high voltage driver control block 1 includes an input circuit 3 , a level shift circuit 4 (first level shift circuit), a decoder 5 , and a level shift circuit 6 (second level shift circuit).
- the low power voltages VLL, VDD, and VSS are supplied to the high voltage driver control block 1 having the above circuits through the power supply terminals TL, TD, and TS, and the high voltage driver control block 1 operates using these low power supply voltages as the power supply voltages.
- the input circuit 3 is connected to the power supply terminals TG and TL through power supply lines, supplied with the ground voltage GND and power supply voltage VLL, and operates using the power supply voltage VLL as the operating voltage.
- the input circuit 3 is supplied with the transmitter signals Din 1 and Din 2 through the external terminals TI 1 - 1 and TI 1 - 2 , respectively.
- the input circuit 3 shapes waveforms of the supplied transmitter signals Din 1 and Din 2 and outputs the resultant signals as signals SS 1 - 1 and SS 1 - 2 .
- the voltages of the transmitter signals Din 1 and Din 2 are changed between voltage levels of, e.g., the ground voltage GND and power supply voltage VLL. According to information to be transmitted, the transmitter signals Din 1 and Din 2 are each changed with the voltage levels of power supply voltage VLL and ground voltage GND as high level and low level, respectively. Further, since the input circuit 3 operates using the power supply voltage VLL as the operating voltage, the signals SS 1 - 1 and SS 1 - 2 output from the input circuit 3 are each changed with the voltage levels of power supply voltage VLL and ground voltage GND as high level and low level, respectively.
- the signals SS 1 - 1 and SS 1 - 2 output from the input circuit 3 are supplied to the level shift circuit 4 .
- the level shift circuit 4 receives the signals SS 1 - 1 and SS 1 - 2 as input signals and converts levels of the respective input signals SS 1 - 1 and SS 1 - 2 .
- the level shift circuit 4 is connected to the power supply terminals TG, TL, and TD through power supply lines and supplied with the ground voltage GND, power supply voltage VLL, and power supply voltage VDD.
- the level shift circuit 4 operates using the power supply voltages VLL and VDD as the operating voltage. That is, the level shift circuit 4 uses these power supply voltages to convert the levels of the input signals SS 1 - 1 and SS 1 - 2 and outputs the resultant signals as signals SS 2 - 1 and SS 2 - 2 , respectively.
- the signals SS 2 - 1 and SS 2 - 2 output from the level shift circuit 4 are each changed between the voltage levels of the ground voltage GND and power supply voltage VDD.
- the level shift circuit 4 converts high level into the voltage level of the power supply voltage VDD and output the resultant signals as high levels of the signals SS 2 - 1 and SS 2 - 2 .
- the level shift circuit 4 outputs low level as low levels of the signals SS 2 - 1 and SS 2 - 2 . That is, the signals SS 2 - 1 and SS 2 - 2 output from the level shift circuit 4 are each changed with the voltage levels of power supply voltage VDD and ground voltage GND as high level and low level, respectively.
- the output signals SS 2 - 1 and SS 2 - 2 (first output signals) output from the level shift circuit 4 are supplied to the decoder 5 as input signals.
- the decoder 5 is connected to the power supply terminals TG and TD through power supply lines and is supplied with the ground voltage GND and power supply voltage VDD. That is, the decoder 5 performs decoding using the power supply voltage VDD as the operating voltage.
- the decoder 5 is supplied with the two input signals SS 2 - 1 and SS 2 - 2 , so that four output signals are formed by the decoding.
- the decoder 5 uses the power supply voltage VDD as the operating voltage, so that high level of the output.
- signal output from the decoder 5 corresponds to a voltage level of the power supply voltage VDD, and low level of the output signal corresponds to a voltage level of the ground voltage GND.
- the high voltage driver 2 includes two high breakdown voltage transistors P 1 and N 1 . Based on one of the two output signals output from the decoder 5 to high voltage driver 2 , conduction of the high breakdown voltage transistor P 1 (first transistor) is controlled, and based on one of the two output signals output from the decoder 5 to level shift circuit 6 , conduction of the high breakdown voltage transistor N 1 (second transistor) is controlled. In FIG.
- the output signal for controlling the high breakdown voltage transistor P 1 is represented as an output signal SS 3 - 1 (first output signal or second output signal)
- output signal for controlling the high breakdown voltage transistor N 1 is represented as an output signal SS 3 - 2 (second output signal or third output signal).
- the output signals of the decoder 5 other than the output signals SS 3 - 1 and SS 3 - 2 are used for, for example, controlling conduction of a transistor (not illustrated) included in the high voltage driver 2 and controlling the transmitter and receiver separation switch RTC 1 .
- the level shift circuit 6 is connected to the power supply terminals TG, TD, and TS through power supply lines and is supplied with the ground voltage GND, power supply voltage VDD, and power supply voltage VSS through the above power supply terminals.
- the level shift circuit 6 operates using the power supply voltages VDD and VSS as the operating voltage. That is, the level shift circuit 6 receives from the decoder 5 the output signal SS 3 - 2 as an input signal and uses the power supply voltages GND, VDD, and VSS to convert a level of the input signal SS 3 - 2 .
- High levels of the output signals SS 3 - 1 and SS 3 - 2 output from the decoder 5 correspond to the voltage level of the power supply voltage VDD, and low levels thereof correspond to the voltage level of the ground voltage GND.
- the level shift circuit 6 converts high level (voltage level of the power supply voltage VDD) of the output signal (input signal) SS 3 - 2 into the voltage level (high level) of the ground voltage GND and converts low level (voltage level of the ground voltage GND) of the output signal SS 3 - 2 into the voltage level (low level) of the power supply voltage VSS.
- the level shift circuit 6 converts the output signal SS 3 - 2 whose voltage (potential) is changed between the voltage levels of the ground voltage GND and positive power supply voltage VDD into a signal whose high level corresponds to the voltage level of the ground voltage GND and whose low level corresponds to the voltage level of the negative power supply voltage VSS, to thereby form an output signal SS 4 (fourth output signal) whose voltage is changed between the above high and low levels.
- the output signal SS 4 obtained by the level shift operation is supplied from the level shift circuit 6 to high voltage driver 2 as a control signal.
- the high voltage driver 2 includes a high voltage level shift circuit 7 (high voltage circuit) and a set of high breakdown voltage transistors P 1 and N 1 .
- the high breakdown voltage transistors P 1 and N 1 are each constituted of a field effect type transistor.
- the high breakdown voltage transistor P 1 (first transistor) is constituted of a P-channel type field effect transistor (hereinafter, referred to also as a P-channel type transistor or a P-type FET), and high breakdown voltage transistor N 1 (second transistor) is constituted of an N-channel type field effect transistor (hereinafter, referred to also as an N-channel type transistor or an N-type FET).
- the high voltage level shift circuit 7 is connected to the power supply terminals TG, TD, TS, TP, and TN through power supply lines.
- the high voltage level shift circuit 7 is supplied with the ground voltage GND and power supply voltages VDD, VSS, VPP, and VNN through the above power supply terminals.
- the high voltage level shift circuit 7 also operates using the supplied voltages as the operating voltage.
- the high voltage level shift circuit 7 inverts a phase of the output signal SS 3 - 1 output from the decoder 5 and shifts a level of an output signal obtained by the phase inversion to form a gate drive signal SP 1 . Further, the high voltage level shift circuit 7 shifts a level of the output signal SS 3 - 2 output from the level shift circuit 6 and outputs the resultant signal as a gate drive signal SN 1 .
- the high voltage level shift circuit 7 phase-inverts the output signal SS 3 - 1 whose high level corresponds to the voltage level of the power supply voltage VDD and whose low level corresponds to the voltage level of the ground voltage GND.
- Low level (voltage level of the ground voltage GND) of the output signal obtained by the phase inversion is converted into the voltage level of the power supply voltage VPP, and high level (voltage level of the power supply voltage VDD) of the output signal obtained by the phase inversion is converted into the voltage level of the ground voltage GND.
- the high voltage level shift circuit 7 converts a voltage of the gate drive signal SN 1 into the voltage level of the ground voltage GND when the output signal SS 4 from the level shift circuit 6 is at high level (voltage level of the ground voltage GND) and converts the voltage of the gate drive signal SN 1 into the voltage level of the power supply voltage VNN when the output signal SS 4 is at low level (voltage level of the power supply voltage VSS).
- the gate drive signal SN 1 corresponds to the voltage level of the ground voltage GND
- the gate drive signal SN 1 corresponds to the voltage level of the power supply voltage VNN.
- a source of the P-type FET P 1 is connected to the power supply terminal TP through a power supply line, and a source of the N-type FET N 1 is connected to the power supply terminal TN through a power supply line. Drains of the P-type FET P 1 and N-type FET N 1 are connected to a node nd.
- a gate of the P-type FET P 1 is supplied with the gate drive signal SP 1 from the high voltage level shift circuit 7
- a gate of the N-type FET N 1 is supplied with the gate drive signal SN 1 from the high voltage level shift circuit 7 .
- the voltage of the gate drive signal SP 1 is made to correspond to the voltage level of the ground voltage GND, with the result that the P-type FET P 1 is made conductive, causing current to be supplied from the power supply voltage VPP to node nd through the P-type FET P 1 .
- the voltage of the gate drive signal SP 1 is made to correspond to the voltage level of the power supply voltage VPP, with the result that the P-type FET P 1 is made non-conductive, and current does not flow from the power supply voltage VPP to node nd.
- the voltage of the gate drive signal SN 1 is made to correspond to the voltage level of the ground voltage GND, with the result that the N-type FET N 1 is made conductive, causing current to be supplied from the node nd to power supply voltage VNN.
- the voltage of the gate drive signal SN 1 is made to correspond to the voltage level of the power supply voltage VNN, with the result that the N-type FET N 1 is made non-conductive, and current does not flow from the node nd to power supply voltage VNN.
- the high voltage driver 2 selectively outputs the high voltage power supply voltage VPP and high voltage power supply voltage VNN according to the output signals SS 3 - 1 and SS 4 .
- a processor not illustrated changes the voltages of the transmitter signals Din 1 and Din 2 with a lapse of time and, accordingly, the output signals SS 1 - 1 and SS 1 - 2 are also each changed between high and low levels with a lapse of time. Accordingly, the output signals SS 2 - 1 and SS 2 - 2 obtained by level shift of the output signals SS 1 - 1 and SS 1 - 2 are also each changed between high and low levels with a lapse of time. The change of the each of the output signals SS 2 - 1 and SS 2 - 2 between high and low levels with a lapse of time causes the output signals SS 3 - 1 and SS 3 - 2 output from the decoder 5 to alternately become high level.
- the level shift circuit 6 level-shits the output signal SS 3 - 2 from the decoder 5 and outputs the resultant signal as the output signal SS 4 .
- the output signals SS 3 - 1 and SS 4 alternately becoming high level are supplied also to the high voltage level shift circuit 7 .
- the separation circuit DVD 1 includes a pair of diode elements D 1 and D 2 .
- Anodes and cathodes of the diode elements D 1 and D 2 are cross-connected so as to constitute a bidirectional switch.
- the high voltage of the node nd is applied to the ultrasound oscillator HB 1 illustrated in FIG. 6 .
- Alternate conduction of the P-type FET P 1 and N-type FET N 1 causes the voltage of the node nd to become a voltage that is changed according to the high voltage power supply voltage VPP or VNN, so that the high voltage (power supply voltage VPP or VNN) from the high voltage driver 2 is applied to the ultrasound oscillator HB 1 through the separation circuit DVD 1 to generate an ultrasound wave.
- the high voltage driver 2 may be provided with a not illustrated transistor so as to make the voltage of the node nd be a predetermined voltage value upon receiver of the reflected wave.
- This transistor may be connected between, for example, the node nd and a predetermined voltage, and conduction thereof may be controlled by an output signal from the decoder 5 . Since the four output signals are output from the decoder 5 as described above, an output signal other than the output signals SS 3 - 1 and SS 3 - 2 may be used to control conduction of the transistor.
- the voltages of the gate drive signals SP 1 and SN 1 are converted into the ground voltage GND and power supply voltage VPP, and ground voltage GND and power supply voltage VNN, respectively; however, the present invention is not limited to this.
- the voltages of the gate drive signals SP 1 and SP 2 may be converted into the voltage levels of the power supply voltages VPP and VNN, respectively.
- the output signal SS 3 - 1 is phase-inverted, and then level shift. is performed; however, the present invention is not limited to this.
- two transmitter signals (Din 1 and Din 2 ) are used; however, the present invention is not limited to this.
- FIG. 2 is a block diagram illustrating a configuration of the transmitter circuit HDV 1 according to the first embodiment.
- the transmitter circuit of the embodiment includes a plurality of power-on reset circuits and a logic circuit so as to prevent the P-type FET P 1 and/or N-type FET N 1 which is an output transistor from being made conductive when an absolute value of the voltage (amplitude with respect to the ground voltage GND) of the power supply voltage of at least one of the power supply voltages VLL, VDD, and VSS becomes small.
- the configuration of the transmitter circuit HDV 1 illustrated in FIG. 2 is similar to the basic configuration of the transmitter circuit illustrated in FIG. 1 .
- a reference numeral 2 denotes a high voltage driver block
- DVD 1 denotes a separation circuit.
- Configurations and operations of the high voltage driver block 2 and separation circuit DVD 1 illustrated in FIG. 2 are the same as those of the high voltage driver block 2 and separation circuit DVD 1 illustrated in FIG. 1 .
- descriptions of the high voltage driver block 2 and separation circuit DVD 1 will be omitted in principle.
- a reference numeral 9 denotes a high voltage driver control block.
- the high voltage driver control block 9 is similar to the high voltage driver control block 1 . That is, the input circuit 3 , level shift circuit 4 , input terminal TI 1 , and power supply terminals TD, TL, TG, and TS included in the high voltage driver control block 1 of FIG. 1 are the same as those included in the high voltage driver control block 9 of FIG. 2 .
- the transmitter circuit HDV 1 of FIG. 2 differs from that of FIG. 1 in that first to fourth power-on reset circuits 10 to 13 and a logic circuit 14 are added to the high voltage driver control block 9 and that configurations of decoder 5 and level shift circuit 6 are changed. Thus, hereinafter, descriptions will be made mainly on the first to fourth. power-on reset circuits 10 to 13 , logic circuit 14 , decoder 5 , and level shift circuit 6 .
- the first power-on reset circuit 10 is connected to the power supply terminals TG, TD, and TL through power supply lines. That is, the first power-on reset circuit 10 is supplied with the ground voltage GND, power supply voltage VDD, and power supply voltage VLL.
- the first power-on reset circuit 10 detects whether or not the voltage of the power supply voltage VLL has been reduced to equal to or less than a predetermined value (first value). In other words, the first power-on reset circuit 10 detects whether or not an absolute value of the voltage (potential) of the power supply voltage VLL has been reduced to equal to or less than a predetermined value (first value).
- the first power-on reset circuit 10 outputs a detection result on a reset signal PR 1 (first reset signal).
- High level of the reset signal PR 1 corresponds to the voltage level of the power supply voltage VDD, and low level thereof corresponds to the voltage level of the ground voltage GND.
- the first power-on reset circuit 10 sets the reset signal PR 1 to high level when the voltage of the power supply voltage VLL is reduced to equal to or less than a predetermined value and sets the same to low level when the voltage of the power supply voltage VLL is larger than the predetermined value.
- the second power-on reset circuit 11 is connected to the power supply terminals TG and TD through power supply lines. That is, the second power-on reset circuit 11 is supplied with the ground voltage GND and power supply voltage VDD.
- the second power-on reset circuit 11 detects whether or not the voltage of the power supply voltage VDD has been reduced to equal to or less than a predetermined value (second value). In other words, the second power-on reset circuit 11 detects whether or not an absolute value of the voltage (potential) of the power supply voltage VDD has been reduced to equal to or less than a predetermined value (second value).
- the second power-on reset circuit 11 outputs a detection result on a reset signal PR 2 (second reset signal).
- High level of the reset signal PR 2 corresponds to the voltage level of the power supply voltage VDD, and low level thereof corresponds to the voltage level of the ground voltage GND.
- the second power-on reset circuit 11 sets the reset signal PR 2 to high level when the voltage of the power supply voltage VDD is reduced to equal to or less than a predetermined value and sets the same to low level when the voltage of the power supply voltage VDD is larger than the predetermined value.
- the third power-on reset circuit 12 is connected to the power supply terminals TG, TD and TS through power supply lines. That is, the third power-on reset circuit 12 is supplied with the ground voltage GND, power supply voltage VDD, and power supply voltage VSS.
- the third power-on reset circuit 12 detects whether or not the voltage of the power supply voltage VSS has been increased to a predetermined value (third value) or more.
- the power supply voltage VSS has a negative potential with respect to the ground voltage GND. Therefore, when the power supply voltage is represented by an absolute value, the third power-on reset circuit 12 detects also whether or not an absolute value of the voltage (potential) of the power supply voltage VSS has been reduced to equal to or less than a predetermined value (third value).
- the third power-on reset circuit 12 outputs a detection result on a reset signal PR 3 (third reset signal).
- High level of the reset signal PR 3 corresponds to the voltage level of the power supply voltage VDD, and low level thereof corresponds to the voltage level of the ground voltage GND.
- the third power-on reset circuit 12 sets the reset signal PR 3 to high level when the absolute value of the voltage of the power supply voltage VSS is reduced to equal to or less than a predetermined value and sets the same to low level when the absolute value of the voltage of the power supply voltage VSS is larger than the predetermined value.
- the fourth power-on reset circuit 13 is connected to the power supply terminals TG, TD, and TS through power supply lines. That is, the fourth power-on reset circuit 13 is supplied with the ground voltage GND, power supply voltage VDD, and power supply voltage VSS.
- the fourth power-on reset circuit 13 detects whether or not the voltage of the power supply voltage VDD has been reduced to equal to or less than a predetermined value (fourth value). In other words, the fourth power-on reset circuit 13 detects whether or not an absolute value of the voltage (potential) of the power supply voltage VDD has been reduced to equal to or less than a predetermined value (fourth value).
- the fourth power-on reset circuit 13 outputs a detection result on a reset signal PR 4 (fourth reset signal).
- High level of the reset signal PR 4 corresponds to the voltage level of the ground voltage GND, and low level thereof corresponds to the voltage level of the power supply voltage VSS.
- the fourth power-on reset circuit 13 sets the reset signal PR 4 to low level when the voltage of the power supply voltage VDD is reduced to equal to or less than a predetermined value and sets the same to high level when the voltage of the power supply voltage VDD is larger than the predetermined value.
- the reset signals PR 1 , PR 2 , and PR 3 output, respectively, from the first power-on reset circuit 10 , second power-on reset circuit 11 , and third power-on reset circuit 12 are input to the logic circuit 14 that performs OR operation.
- the logic circuit 14 outputs a high level synthesized reset signal PCM. That is, when the absolute value of at least one of the power supply voltages VLL, VDD, and VSS becomes equal to or less than a predetermined value (first, second, or third value), the synthesized reset signal PCM becomes high level.
- the logic circuit 14 is connected to the power supply terminals TD and TG and operates using the power supply voltage VDD as the operating voltage.
- High level of the synthesized reset signal PCM corresponds to, e.g., the voltage level of the power supply voltage VDD, and low level thereof corresponds to the voltage level of the ground voltage GND.
- the synthesized reset signal PCM becomes low level.
- the synthesized reset signal PCM is supplied to the decoder 5 .
- the decoder 5 When the synthesized reset signal PCM is at low level, the decoder 5 performs the same operation as the decoder 5 illustrated in FIG. 1 does. That is, the decoder 5 decodes the output signals SS 2 - 1 and SS 2 - 2 from the level shift circuit 4 and outputs a result of the decoding.
- the synthesized reset signal PCM is at high level, the decoder 5 assumes a predetermined state in response to the high level synthesized reset signal PCM.
- the decoder 5 is controlled to a state where it outputs the output signals SS 3 - 1 and SS 3 - 2 that make the respective P-type FET P 1 and N-type FET N 1 non-conductive. In the first embodiment, the decoder 5 is put into a state where it sets both the output signals SS 3 - 1 and SS 3 - 2 to low level.
- FIG. 7 is a block diagram illustrating a configuration of the decoder 5 according to the first embodiment.
- the decoder 5 includes a decoder circuit DEC and flip-flop circuits FF 1 to FF 4 .
- the decoder circuit DEC decodes the output signals SS 2 - 1 and SS 2 - 2 from the level shift circuit 4 .
- the flip-flop circuits FF 1 to FF 4 each include a data input terminal I, a clear terminal C, and a data output terminal O.
- the decoding results obtained by the decoder circuit DEC are supplied to the data input terminals I of the corresponding flip-flop circuits FF 1 to FF 4 . Further, the clear terminals C of the respective flip-flop circuits FF 1 to FF 4 are supplied with the synthesized reset signal PCM.
- each of the flip-flop circuits FF 1 to FF 4 When the synthesized reset signal PCM supplied to the clear terminal C is at low level, each of the flip-flop circuits FF 1 to FF 4 outputs, from the data output terminal O, the output of the decoder circuit DEC supplied to the data input terminal I. On the other hand, when the synthesized reset signal PCM supplied to the clear terminal C is at high level, each of the flip-flop circuits FF 1 to FF 4 outputs low level from the data output terminal O, irrespective of the output of the decoder circuit DEC.
- the synthesized reset signal PCM when the synthesized reset signal PCM is at low level, the output signal SS 3 - 1 at high level or low level and output signal SS 3 - 2 at high level or low level are output from the data output terminals O of the flip-flop circuits FF 1 and FF 4 , respectively, in accordance with results of decoding of the output signals SS 2 - 1 and SS 2 - 2 .
- the synthesized reset signal PCM is at high level
- the output signals SS 3 - 1 and SS 3 - 2 at low level are output from the output terminals O of the respective flip-flop circuits FF 1 and FF 4 .
- the decoder 5 when the synthesized reset signal PCM is at high level, the decoder 5 is put into a predetermined state.
- the decoder circuit DEC and flip-flop circuits FF 1 to FF 4 operate using the power supply voltage VDD as the operating voltage, and high level thereof corresponds to the voltage level of the power supply voltage VDD and low level thereof corresponds to the voltage level of the ground voltage GND.
- the flip-flop circuits FF 1 to FF 4 are configured to receive the outputs of the decoder circuit DEC in FIG. 7 , the present invention is not limited to this.
- the flip-flop circuits FF 1 and FF 2 may be provided on the input side of the decoder circuit DEC.
- the flip-flop circuits FF 1 and FF 2 are cleared by the synthesized reset signal PCM, and the output signals SS 3 - 1 and SS 3 - 2 are set to low level.
- the flip-flop circuit need not be provided in the decoder 5 .
- a clear terminal is provided in the decoder circuit DEC, and the synthesized reset signal PCM is supplied to the decoder circuit DEC through the clear terminal.
- the decoder circuit DEC sets the output signals SS 3 - 1 and SS 3 - 2 to low level.
- the output signals SS 3 - 1 and SS 3 - 2 of the decoder 5 becomes low level (ground voltage GND).
- the high voltage level shift circuit 7 makes the voltage of the gate drive signal SP 1 correspond to the voltage level of the power supply voltage VPP, as described using FIG. 1 .
- the P-type FET P 1 is made non-conductive.
- the level shift circuit 6 level-shifts the output signal SS 3 - 2 and outputs a low level signal as the output signal SS 4 having a voltage level of the power supply voltage VSS.
- the source of the N-type FET N 1 is supplied with a voltage of up to ⁇ 100 V as the power supply voltage VNN. Therefore, in order to make the N-type FET N 1 non-conductive, it is necessary to make the voltage of the gate drive signal SN 1 negative.
- the ground voltage GND corresponding to low level of the output signal SS 3 - 2 which is output from the decoder 5 , is level-converted into a voltage level of the negative power supply voltage VSS by the level shift circuit 6 , and the low level output from the level shift circuit 6 is level-converted into up to a voltage level of the negative power supply voltage VNN by the high voltage level shift circuit 7 . That is, the gate drive signal SN 1 is converted into a negative high voltage in a plurality of steps. This can reduce a burden involved in the level conversion.
- a configuration example of the level shift circuit 6 will be described later using FIG. 3 .
- operation of the level shift circuit 6 may become unstable, which may cause malfunction.
- the level shift circuit 6 is put into a predetermined state by the reset signal PR 4 from the fourth power-on reset circuit 13 , thereby preventing occurrence of malfunction associated with unstable operation of the level shift circuit 6 .
- the level shift circuit 6 When the absolute values of both the power supply voltage VLL and power supply voltage VSS become equal to or less than a predetermined value or when the absolute value of the power supply voltage VLL or power supply voltage VSS becomes equal to or less than a predetermined value, the level shift circuit 6 operates stably.
- the low level output signal SS 3 - 2 from the decoder 5 is subjected to level conversion by the level shift circuit 6 .
- the output signal SS 4 having a voltage level of the power supply voltage VSS is supplied to the high voltage level shift circuit 7 from the level shift circuit 6 .
- the high voltage level shift circuit 7 outputs the gate drive signal SN 1 having a voltage of the power supply voltage VNN.
- the N-type FET N 1 is also made non-conductive.
- both the P-type FET P 1 and N-type FET N 1 are made non-conductive, thereby making it possible to prevent a short-circuit or erroneous output of a high voltage.
- FIG. 3 is a circuit diagram illustrating a configuration of the level shift circuit 6 .
- the level shift circuit. 6 includes P-type FETs p 1 to p 6 , N-type FETs n 1 to n 6 , and a two-input AND circuit AD.
- VDD-L denotes a power supply line connecting the level shift circuit 6 and power supply terminal TD
- VSS-L denotes a power supply line connecting the level shift circuit 6 and power supply terminal TS
- GND-L denotes a power supply line connecting the level shift circuit 6 and power supply terminal TG. Accordingly, the power supply line VDD-L is supplied with the power supply voltage VDD
- power supply line VSS-L is supplied with the power supply voltage VSS
- power supply line GND-L is supplied with the ground voltage GND.
- Sources of the P-type FETs p 1 and p 2 are connected to the power supply line VDD-L, sources of the N-type FETs n 1 and n 2 are connected to the power supply line GND-L, and drains of the P-type FETs p 1 and p 2 are connected, respectively, to drains of the N-type FETs n 1 and n 2 .
- Gates of the P-type FET p 1 and N-type FET n 1 are connected in common and are supplied with the output signal SS 3 - 2 from the decoder 5 .
- Gates of the P-type FET p 2 and N-type FET n 2 are also connected in common and are supplied with an inversion signal /SS 3 - 2 obtained by inverting a phase of the output signal SS 3 - 2 .
- Sources of the P-type FETs p 3 and p 4 are connected to the power supply line GND-L, and sources of the N-type FETs n 3 and n 4 are connected to the power supply line VSS-L.
- Drains of the P-type FETs p 3 and p 4 are connected, respectively, to drains of the N-type FETs n 3 and n 4 .
- Gates of the P-type FET p 3 and N-type FET n 3 are connected in common to the drains of the P-type FET p 4 and N-type FET n 4 .
- Gates of the P-type FET p 4 and N-type FET n 4 are connected in common to the drains of the P-type FET p 3 and N-type FET n 3 .
- the P-type FET p 3 and N-type FET n 3 constitute a first inverter circuit
- the P-type FET p 4 and N-type FET n 4 constitute a second inverter circuit.
- An input of the first inverter circuit (p 3 , n 3 ) is connected to an output of the second inverter circuit (p 4 , n 4 ), and an input of the second inverter circuit is connected to an output of the first inverter circuit.
- a latch circuit is constituted by the first and. second inverter circuits.
- the input (gates of p 3 and n 3 ) of the first inverter circuit is connected to a source of the N-type FET n 6 whose gate is connected to the power supply line GND-L.
- a drain of the N-type FET n 6 is connected to a drain of the P-type FET p 6 whose gate is connected to the power supply line GND-L.
- a source of the P-type FET p 6 is connected to the drains of the P-type FET p 2 and N-type FET n 2 .
- the input (gates of p 4 and n 4 ) of the second inverter circuit is connected to a source of the N-type FET n 5 whose gate is connected to the power supply line GND-L.
- a drain of the N-type FET n 5 is connected to a drain of the P-type FET p 5 whose gate is connected to the power supply line GND-L.
- a source of the P-type FET p 5 is connected to the drains of the P-type FET p 1 and N-type FET n 1 .
- the P-type FET p 1 and N-type FET n 1 constitute a third inverter circuit that operates using the power supply voltage VDD and ground voltage GND as the operating voltage.
- the P-type FET p 2 and N-type FET n 2 constitute a fourth inverter circuit that operates using the power supply voltage VDD and ground voltage GND as the operating voltage.
- the third inverter circuit (p 1 , n 1 ) phase-inverts the output signal SS 3 - 2 and outputs the voltage level of the power supply voltage VDD or ground voltage GND.
- the output voltage of the third inverter circuit is supplied to the input of the second inverter circuit (p 4 , n 4 ) through.
- the fourth inverter circuit (p 2 , n 2 ) phase-inverts the inversion signal /SS 3 - 2 and outputs the voltage level of the power supply voltage VDD or ground voltage GND.
- the output voltage of the fourth inverter circuit is supplied to the input of the first inverter circuit (p 3 , n 3 ) through the P-type FET p 6 and N-type FET n 6 .
- a voltage changed between the voltage levels of the power supply voltage VDD and ground voltage GND is supplied to the input of the latch circuit through the P-type FET and N-type FET whose gates are supplied with the ground voltage GND.
- the latch circuit holds a state according to the supplied voltage, and a voltage of a node LS 2 out is made to correspond to the voltage level of the power supply voltage VSS or ground voltage GND according to the voltage of the output signal SS 3 - 2 .
- the N-type FET n 1 and P-type FET p 2 are made conductive, causing the voltage level of the power supply voltage VDD to be supplied to the input of the first inverter circuit through the P-type FET p 6 and N-type FET n 6 .
- the voltage level of the ground voltage GND is supplied to the input of the second inverter circuit through the P-type FET p 5 and N-type FET n 5 .
- the output of the first inverter circuit is made to correspond to the voltage level of the power supply voltage VSS, and output of the second inverter circuit is made to correspond to the voltage level of the ground voltage GND.
- This state is retained in the latch circuit, making the voltage of the node LS 2 out correspond to the ground voltage GND (high level).
- the N-type FET n 2 and P-type FET p 1 are made conductive, causing the voltage level of the power supply voltage VDD to be supplied to the input of the second inverter circuit through the P-type FET p 5 and N-type FET n 5 .
- the voltage level of the ground voltage GND is supplied to the input of the first inverter circuit through the P-type FET p 6 and N-type FET n 6 .
- the output of the second inverter circuit is made to correspond to the voltage level of the power supply voltage VSS
- output of the first inverter circuit is made to correspond to the voltage level of the ground voltage GND. This state is retained in the latch circuit, making the voltage of the node LS 2 out correspond to the voltage level of the power supply voltage VSS (low level).
- the output signal SS 3 - 2 whose high level corresponds to the power supply voltage VDD and whose low level corresponds to the ground voltage GND is level-converted into a signal whose high level corresponds to the ground voltage GND and whose low level corresponds to the voltage level of the negative power supply voltage VSS.
- the synthesized reset signal PCM from the logic circuit 14 becomes high level and, accordingly, the decoder 5 is put into a predetermined state, as described above.
- the decoder 5 put into a predetermined state makes the output signals SS 3 - 1 and SS 3 - 2 low level.
- the P-type FET p 1 When the output signal SS 3 - 2 becomes low level, the P-type FET p 1 is made conductive; however, since the voltage of the power supply voltage VDD is equal to or less than a predetermined value, the level of the voltage to be supplied to the input of the second inverter circuit is reduced. This may made the latch circuit unstable. This may cause, for example, a state where the voltage of the node LS 2 out is being at the ground voltage GND to be continued. That is, it may be impossible to change the state of the latch circuit.
- the N-type FET N 1 in the high voltage driver 2 continues its conductive state even though the voltage of the power supply voltage VDD becomes equal to or less than a predetermined value, with the result that the power supply voltage VNN which is a negative high voltage is output from the transmitter circuit HDV 1 .
- the two-input AND circuit AD is provided in the level shift circuit 6 .
- One output of the AND circuit AD is connected to the node LS 2 out, and the other output thereof is supplied with the reset signal PR 4 .
- An output of the AND circuit AD is supplied to the high voltage level shift circuit 7 as the above-mentioned output signal SS 4 .
- the AND circuit AD is supplied with the ground voltage GND and power supply voltage VES and operates using these voltages as the operating voltage. That is, the output signal SS 4 output from the AND circuit AD is a signal whose high level corresponds to the voltage level of the ground voltage GND and whose low level corresponds to the voltage level of the power supply voltage VSS.
- the fourth power-on reset circuit 13 when the voltage of the power supply voltage VDD becomes equal to or less than a predetermined value, the fourth power-on reset circuit 13 outputs the low level reset signal PR 4 having a voltage level of the power supply voltage VSS.
- the voltage of the power supply voltage VDD becomes equal to or less than a predetermined value
- low level is supplied to the other input of the AND circuit AD, with the result that the output signal SS 4 of the AND circuit.
- AD becomes low level (voltage level of the power supply voltage VSS).
- the N-type FET N 1 is made non-conductive.
- the power supply voltage VNN which is a negative high voltage can be prevented from being output through the N-type FET N 1 .
- the level shift circuit 6 when the absolute value of the voltage of the power supply voltage VDD becomes equal to or less than a predetermined value, the level shift circuit 6 is forced into a predetermined state by the fourth power-on reset circuit 13 , where it outputs the output signal SS 4 having a level that makes the N-type FET N 1 in the high voltage driver 2 non-conductive irrespective of the output. of the decoder 5 . That is, even being in an unstable state, the latch circuit in the level shift circuit 6 allows the output signal SS 4 having a level that makes the transistor in the high voltage driver 2 non-conductive to be output from the level shift circuit 6 .
- the AND circuit AD can be regarded as a limiting circuit that forcibly limits the potential of the output signal SS 4 to low level (voltage level of the power supply voltage VSS) according to the reset signal PR 4 .
- the high voltage driver 2 it is possible to prevent a short circuit between the positive high voltage (VPP) and negative high voltage (VNN) which may occur when the absolute value of at least one of the plurality of types of power supply voltages (VDD, VSS, and VLL) including positive and negative voltages supplied to the transmitter circuit HDV 1 as the operating voltage becomes equal to or less than a predetermined value. Further, it is possible to prevent the positive or negative high voltage from being erroneously output from the high voltage driver 2 .
- the pulser semiconductor device CHP Upon application of a plurality of power supply voltages to the pulser semiconductor device CHP, they are applied in the ascending order of the absolute value so as to prevent the malfunction, damage, or the like. Specifically, the power supply voltages are applied in the order of the ground voltage GND, power supply voltage VLL, power supply voltages VDD and VSS, and power supply voltages VPP and VNN which are high voltages.
- the high voltage driver 2 i.e., pulser semiconductor device when the absolute value of at least one of the plurality of types of power supply voltages (VDD, VSS, and VLL) becomes equal to or less than a predetermined value. This can enhance a degree of freedom in the application order of the power supplies.
- the low level output signals SS 3 - 1 , SS 3 - 2 , and SS 4 are output from the decoder 5 and level shift circuit 6 in order to make the N-type FET N 1 and P-type FET P 1 in the high voltage driver 2 non-conductive; however, the present invention is not limited to this.
- a configuration may be possible, in which the N-type FET N 1 and P-type FET P 1 are made non-conductive when the output signals SS 3 - 1 , SS 3 - 2 , and SS 4 are at high level.
- the configuration of the high voltage level shift circuit 7 may be changed so as to make the N-type FET N 1 and P-type FET P 1 non-conductive when the output signals SS 3 - 1 , SS 3 - 2 , and SS 4 are at high level.
- the logic circuit constituting the synthesized reset signal PCM is not limited to a logic circuit that performs OR operation.
- the first to fourth power-on reset circuits 10 to 13 may each have various configurations as long as they can detect whether or not the absolute value of the voltage of the power supply voltage is equal to or less than a predetermined value and output a detection signal (reset)signal.
- the predetermined value serving as a reference when the first to third power-on reset circuits 10 to 12 perform the detection are different from each other since the polarity and voltage value of the power supply voltage to be detected by the power-on reset circuits are different.
- the fourth power-on reset circuit 13 and second power-on reset circuit 11 detect the same power supply voltage (VDD).
- the fourth power-on reset circuit 13 and second power-on reset circuit 11 may use the same value as the predetermined value to detect whether or not the voltage of the power supply voltage VDD is equal to or less than the predetermined value.
- the fourth power-on reset circuit 13 and second power-on reset circuit 11 may use different values as the predetermined value to be used as a reference.
- the level shift circuit 4 may have various configurations as long as it can perform the level conversion.
- the configuration of the level shift circuit 6 is also not limited to that illustrated in FIG. 3 and may have various configurations as long as it has the latch circuit.
- the output signal SS 3 - 2 form the decoder 5 is level-converted by the level shift circuit 6 and, based on the output signal SS 4 obtained by the level conversion, conduction of the N-type FET N 1 is controlled.
- a level shift circuit having the same configuration as that of the level shift circuit 6 may be provided for the output signal SS 3 - 1 from the decoder 5 .
- conduction of the P-type FET P 1 is controlled based on an output signal obtained through the level conversion performed by the newly provided level shift circuit.
- the transmitter circuit or peripheral components can be prevented from being damaged or broken by the first to fourth power-on reset circuits 10 to 13 and logic circuit 14 , so that it can be considered that the first to fourth power-on reset circuits 10 to 13 and logic circuit constitute a protective circuit. Further, from a viewpoint that the damage or breaking is prevented by the level shift circuit provided with the latch circuit, it can be considered that a first protective circuit is constituted. by the first to third power-on reset circuits 10 to 12 and logic circuit 14 , and a second protective circuit is constituted by the fourth power-on reset circuit 13 .
- the decoder 5 is controlled by the first protective circuit so as to output the output signals SS 3 - 1 and SS 3 - 2 having levels that make the respective transistors P 1 and N 1 non-conductive.
- the level shift circuit 6 is controlled by the second protective circuit so as to output the output signal SS 4 having a level that makes the transistor Ni non-conductive.
- FIG. 4 is a block diagram illustrating a configuration of a transmitter circuit according to a second embodiment.
- the configuration of a transmitter circuit HDV 1 illustrated in FIG. 4 is similar to that of the transmitter circuit illustrated in FIG. 2 and differs therefrom only in that a temperature detection circuit 15 is newly added, and the logic circuit 14 that performs OR operation is changed to a logic circuit 14 A.
- the input circuit 3 , level shift circuit 4 , decoder 5 , and level shift circuit 6 are put together as one circuit block 1 A. That is, in FIG. 4 , the circuit block 1 A includes the input circuit 3 , level shift circuit 4 , decoder 5 , and level shift circuit 6 described using FIG. 2 . Further, in FIG.
- the transmitter circuit HDV 1 includes a temperature detection circuit 15 that detects a temperature.
- the temperature detection circuit 15 is formed on a semiconductor chip, connected to the power supply terminals TG and TD through power supply lines, and operates using the power supply voltage VDD as the operating voltage. That is, the temperature detection circuit 15 detects whether or not a temperature is equal to or higher than a predetermined temperature and supplies a detection result to the logic circuit 14 A as a detection signal (reset signal) TDT.
- the detection signal TDT is a signal whose high level corresponds to the voltage level of the power supply voltage VDD and whose low level corresponds to the ground voltage GND.
- the temperature detection circuit 15 makes the detection signal TDT high level when the temperature is equal to or higher than a predetermined temperature, and makes the detection signal TDT low level when the temperature is lower than a predetermined temperature.
- the logic circuit 14 performs OR operation among three inputs.
- the three-input logic circuit 14 is changed to the four-input logic circuit 14 A. That is, the logic circuit 14 A is supplied further with the detection signal TDT in addition to the reset signals PR 1 to PR 3 as with the logic circuit 14 . That is, the logic circuit 14 A performs OR operation among the reset signals PR 1 , PR 2 , and PR 3 , and detection signal TDT.
- a result of the OR operation is supplied to the decoder 5 ( FIG. 2 ) as the synthesized reset signal PCM as in the transmitter circuit of FIG. 2 .
- a reset signal among the reset signals PR 1 to PR 3 corresponding to the power supply voltage whose value has become equal to or less than a predetermined value becomes high level.
- the detection signal TDT becomes high level.
- the synthesized reset signal PCM output from the logic circuit 14 A becomes high level when the absolute value of the voltage of at least one of the power supply voltages VDD, VSS, and VLL becomes equal to less than a predetermined value or when the temperature becomes equal to or higher than a predetermined temperature.
- the N-type FET N 1 and P-type FET P 1 in the high voltage driver 2 are made non-conductive. That is, unlike the first embodiment, the N-type FET N 1 and P-type FET P 1 are made non-conductive also when the temperature becomes equal to or higher than a predetermined temperature.
- the N-type FET N 1 and P-type FET P 1 that constitute the high voltage driver 2 output the high voltage power supply voltages VPP and VNN, respectively. Therefore, the transistors (N 1 , P 1 ) are likely to increase in temperature and have thus a risk of damage due to heat. If the transistors are damaged, a leak current flows between the power supply voltage VPP and/or power supply voltage VNN and the node nd through the transistors. When the leak current flows, the peripheral components such as the pulser semiconductor device CHP and/or receiver circuit are disadvantageously damaged.
- the temperature detection circuit 15 is provided on the same semiconductor chip on which the transistors (N 1 , P 1 ) are provided. Therefore, for example, a temperature lower than a temperature of the semiconductor chip at which the transistors may be broken is set as the predetermined temperature. Thus, it is possible to prevent temperature rise by making the transistors non-conductive before breaking of the transistors to disconnect current paths of the transistors.
- FIG. 5 is a block diagram illustrating a configuration of a transmitter circuit according to a third embodiment.
- the configuration of a transmitter circuit HDV 1 illustrated in FIG. 5 is similar to that illustrated in FIG. 4 .
- the transmitter circuit HDV 1 of FIG. 5 newly includes a transmitter and receiver separation switch control circuit 16 compared to the transmitter circuit of FIG. 4 .
- the transmitter and receiver separation switch control circuit 16 is a circuit that controls the transmitter and receiver separation switch RTC 1 described using FIG. 6 .
- FIG. 5 the input/output terminal TU 1 and output terminal TR 1 of the pulser semiconductor device CHP, separation circuit DVD 1 , and transmitter and receiver separation switch RTC 1 are illustrated, compared to the components illustrated in FIG. 4 .
- the input/output terminal TU 1 of the pulser semiconductor device CHP is connected to the ultrasound oscillator HB 1
- the output terminal TR 1 is connected to the input of the receiver circuit RCV 1 .
- the configuration of the separation circuit DVD 1 has been described using FIG. 1 , so the description thereof will be omitted.
- the transmitter and receiver separation switch control circuit 16 is connected to the power supply terminals TD and TG through power supply lines and operates using the power supply voltage VDD as the operating voltage.
- the transmitter and receiver separation switch control circuit 16 outputs, to the transmitter and receiver separation switch RTC 1 , a switch control signal TTC whose high level corresponds to the voltage level of the power supply voltage VDD and whose low level corresponds to the voltage level of the ground voltage GND.
- the transmitter and receiver separation switch control circuit 16 receives an output signal RTCC from the decoder 5 ( FIG. 1 , FIG. 2 ) in the circuit block 1 A and the synthesized reset signal PCM, and forms and outputs the switch control signal TTC.
- the decoder 5 forms four output signals based on the transmitter signals Din 1 and Din 2 .
- Two of the four output signals output i.e., output signals SS 3 - 1 and SS 3 - 2 are used for controlling conduction of the N-type FET N 1 and P-type FET P 1 , respectively.
- one of the remaining two output signals is used as the above-mentioned output signal RTCC.
- the decoder 5 makes the output signal RTCC, for example, high level by combination of the transmitter signals Din 1 and Din 2 .
- the transmitter and receiver separation switch control circuit 16 makes the switch control signal TTC high level in response to high level of the output signal RTCC.
- the switch control signal TTC becomes high level
- the transmitter and receiver separation switch RTC 1 is made conductive.
- the input/output terminal TU 1 is electrically connected to the output terminal TR 1 through the transmitter and receiver separation switch RTC 1 .
- a minute detection signal from the ultrasound oscillator HB 1 is input to the receiver circuit RCV 1 and then amplified.
- the low level output signal RTCC is output from the decoder 5 .
- the transmitter and receiver separation switch control circuit 16 makes the switch control signal TTC low level.
- the transmitter and receiver separation switch RTC 1 is made non-conductive. That is, the input/output terminal TU 1 and output terminal TR 1 are electrically separated.
- the transmitter and receiver separation switch is made conductive when the absolute value of the voltage of at least one of the power supply voltages VDD, VSS, and VLL becomes equal to or less than a predetermined value to cause erroneous output of a high voltage from the transmitter circuit HDV 1 , the high voltage is disadvantageously supplied to the receiver circuit RCV 1 through the transmitter and receiver separation switch RTC 1 . In this case, the receiver circuit may be damaged or broken by the high voltage.
- the transmitter and receiver separation switch control circuit 16 when the synthesized reset signal PCM becomes high level, the transmitter and receiver separation switch control circuit 16 makes the switch control signal TTC low level irrespective of the level of the output signal RTCC. As a result, the transmitter and receiver separation switch RTC 1 is made non-conductive. That is, when the absolute value of the voltage of the power supply voltages VDD, VSS, and VLL becomes equal to or less than a predetermined value, the transmitter and receiver separation switch RTC 1 is forcibly made non-conductive.
- the transmitter and receiver separation switch RTC 1 is controlled to be made non-conductive. As a result, it is possible to more reliably prevent the peripheral components such as the receiver circuit from being damaged or broken.
- the output signal of the decoder 5 is used to control conduction/non-conduction of the transmitter and receiver separation switch RTC 1 ; however, the present invention is not limited to this. Further, in the third embodiment, when the switch control signal TTC is at high level, the transmitter and receiver separation switch RTC 1 is made conductive; however, as a matter of course, the transmitter and receiver separation switch RTC 1 may be made conductive when the switch control signal TTC is at low level.
- the output signals SS 3 - 1 and SS 3 - 2 that control conduction of the transistors in the high voltage driver 2 are formed by the decoder 5 ; however, a circuit that forms the output signals SS 3 - 1 and SS 3 - 2 is not limited to the decoder, but may be any circuit as long as it is an internal circuit.
- a circuit that forms the output signals SS 3 - 1 and SS 3 - 2 is not limited to the decoder, but may be any circuit as long as it is an internal circuit.
- these output signals are retained by the respective flip-flop circuits FF 1 to FF 4 illustrated in FIG. 7 .
- the synthesized reset signal PCM is supplied to the clear terminal C. This eliminates the need to provide the decoder circuit DEC in the internal circuit.
- the present invention has been described taking the transmitter circuit as an example; however, the present invention may be applied to an electronic circuit that operates using a plurality of types of power supply voltages including the positive and negative polarities as the operating voltage. Further, in the first to third embodiments, the field effect type transistors are used; however, the present invention is not limited to this.
Abstract
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US10637462B1 (en) * | 2019-05-30 | 2020-04-28 | Xilinx, Inc. | System and method for SoC power-up sequencing |
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EP3941078A4 (en) | 2019-03-13 | 2022-12-07 | Hisense Visual Technology Co., Ltd. | Reset device and display equipment |
CN109982147B (en) * | 2019-03-13 | 2020-09-29 | 海信视像科技股份有限公司 | Reset device, reset processing method and display equipment |
US11444611B2 (en) * | 2020-10-06 | 2022-09-13 | Mediatek Inc. | Chip having a receiver including a hysteresis circuit |
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JP2005102086A (en) | 2003-09-26 | 2005-04-14 | Renesas Technology Corp | Semiconductor device and level conversion circuit |
US20080068369A1 (en) * | 2006-09-15 | 2008-03-20 | Fuji Electric Device Technology Co., Ltd. | Display driving apparatus |
US20110050322A1 (en) * | 2009-08-31 | 2011-03-03 | Thierry Sicard | Switching circuit with gate driver having precharge period and method therefor |
US20110068851A1 (en) * | 2009-09-21 | 2011-03-24 | Freescale Semiconductor, Inc | Power switch circuit |
US20170033710A1 (en) * | 2015-07-31 | 2017-02-02 | Renesas Electronics Corporation | Semiconductor device |
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US5628322A (en) * | 1995-05-15 | 1997-05-13 | Kabushiki Kaisha Toshiba | Method of ultrasound imaging and diagnostic ultrasound system |
JP2005102086A (en) | 2003-09-26 | 2005-04-14 | Renesas Technology Corp | Semiconductor device and level conversion circuit |
US7161387B2 (en) | 2003-09-26 | 2007-01-09 | Renesas Technology Corp. | Semiconductor device and level conversion circuit |
US20080068369A1 (en) * | 2006-09-15 | 2008-03-20 | Fuji Electric Device Technology Co., Ltd. | Display driving apparatus |
US20110050322A1 (en) * | 2009-08-31 | 2011-03-03 | Thierry Sicard | Switching circuit with gate driver having precharge period and method therefor |
US20110068851A1 (en) * | 2009-09-21 | 2011-03-24 | Freescale Semiconductor, Inc | Power switch circuit |
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US10637462B1 (en) * | 2019-05-30 | 2020-04-28 | Xilinx, Inc. | System and method for SoC power-up sequencing |
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US20170047921A1 (en) | 2017-02-16 |
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