US9837484B2 - Semiconductor device and method of forming substrate including embedded component with symmetrical structure - Google Patents

Semiconductor device and method of forming substrate including embedded component with symmetrical structure Download PDF

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US9837484B2
US9837484B2 US14/722,872 US201514722872A US9837484B2 US 9837484 B2 US9837484 B2 US 9837484B2 US 201514722872 A US201514722872 A US 201514722872A US 9837484 B2 US9837484 B2 US 9837484B2
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conductive layer
insulating layer
semiconductor component
semiconductor
forming
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US20160351486A1 (en
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JinHee Jung
Hyungsang PARK
Sungsoo Kim
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Stats Chippac Management Pte Ltd
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Stats Chippac Pte Ltd
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    • H01L28/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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Definitions

  • the present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a substrate including an embedded component with a symmetrical structure.
  • Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, and various signal processing circuits.
  • LED light emitting diode
  • MOSFET power metal oxide semiconductor field effect transistor
  • Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays.
  • Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
  • Semiconductor devices exploit the electrical properties of semiconductor materials.
  • the structure of semiconductor material allows the material's electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
  • a semiconductor device contains active and passive electrical structures.
  • Active structures including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current.
  • Passive structures including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions.
  • the passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.
  • Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components.
  • Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support, electrical interconnect, and environmental isolation.
  • semiconductor die refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
  • One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products.
  • a smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components.
  • Back-end processes may result in semiconductor device packages with a thinner profile or a smaller footprint by improvements in electrical interconnection and packaging materials.
  • IPDs integrated passive devices
  • RF radio frequency
  • IPDs integrated passive devices
  • Examples of IPDs include resistors, capacitors, and inductors.
  • a typical RF system requires multiple IPDs in one or more semiconductor packages to perform the necessary electrical functions.
  • One method of incorporating IPDs into a system is to embed the IPDs in a substrate to form an embedded passive substrate (EPS).
  • EPS embedded passive substrate
  • one metal layer is formed directly over the passive component and the other metal layer is formed under the passive component, between stacked thick insulating layers.
  • the multiple levels of metal layers and insulating layers cause uneven heat management and long signal loop lengths. Accordingly, conventional EPSs are prone to warpage and electrical noise issues.
  • the present invention is a semiconductor device comprising a first conductive layer.
  • a second conductive layer is formed over the first conductive layer.
  • a semiconductor component is disposed over the first conductive layer.
  • the second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component.
  • a third conductive layer is formed over the semiconductor component opposite the first conductive layer.
  • the semiconductor device includes a symmetrical structure.
  • the present invention is a semiconductor device comprising a first insulating layer.
  • a first conductive layer is formed over the first insulating layer.
  • a semiconductor component is disposed over the first insulating layer.
  • the first conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component.
  • the present invention is a method of making a semiconductor device comprising the steps of providing a substrate including a first conductive layer, forming a second conductive layer over the first conductive layer, and disposing a semiconductor component over the first conductive layer.
  • the second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component.
  • the method further includes the step of forming a third conductive layer over the semiconductor component opposite the first conductive layer.
  • the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, forming a first conductive layer over the substrate, and disposing a semiconductor component over the substrate.
  • the first conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component.
  • FIG. 1 illustrates a printed circuit board (PCB) with different types of packages mounted to its surface
  • FIGS. 2 a -2 d illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street
  • FIGS. 3 a -3 o illustrate a process of forming a substrate with an embedded passive device and a symmetrical structure
  • FIGS. 4 a -4 c illustrate other substrates with an embedded passive device and a symmetrical structure.
  • Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer.
  • Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits.
  • Active electrical components such as transistors and diodes, have the ability to control the flow of electrical current.
  • Passive electrical components such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.
  • Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization.
  • Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion.
  • the doping process modifies the electrical conductivity of semiconductor material in active devices by dynamically changing the semiconductor material conductivity in response to an electric field or base current.
  • Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
  • Active and passive components are formed by layers of materials with different electrical properties.
  • the layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • electrolytic plating electroless plating processes.
  • Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
  • Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation.
  • the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes.
  • the wafer is singulated using a laser cutting tool or saw blade.
  • the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components.
  • Contact pads formed over the semiconductor die are then connected to contact pads within the package.
  • the electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds.
  • An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation.
  • the finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
  • FIG. 1 illustrates electronic device 50 having a chip carrier substrate or PCB 52 with a plurality of semiconductor packages mounted on a surface of PCB 52 .
  • Electronic device 50 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in FIG. 1 for purposes of illustration.
  • Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions.
  • electronic device 50 can be a subcomponent of a larger system.
  • electronic device 50 can be part of a tablet, cellular phone, digital camera, or other electronic device.
  • electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer.
  • the semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), microelectromechanical systems (MEMS), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.
  • PCB 52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB.
  • Conductive signal traces 54 are formed over a surface or within layers of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 54 also provide power and ground connections to each of the semiconductor packages.
  • a semiconductor device has two packaging levels.
  • First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate.
  • Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB.
  • a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
  • first level packaging including bond wire package 56 and flipchip 58
  • second level packaging including ball grid array (BGA) 60 , bump chip carrier (BCC) 62 , land grid array (LGA) 66 , multi-chip module (MCM) 68 , quad flat non-leaded package (QFN) 70 , quad flat package 72 , embedded wafer level ball grid array (eWLB) 74 , and wafer level chip scale package (WLCSP) 76 are shown mounted on PCB 52 .
  • BGA ball grid array
  • BCC bump chip carrier
  • LGA land grid array
  • MCM multi-chip module
  • QFN quad flat non-leaded package
  • eWLB embedded wafer level ball grid array
  • WLCSP wafer level chip scale package
  • eWLB 74 is a fan-out wafer level package (Fo-WLP) and WLCSP 76 is a fan-in wafer level package (Fi-WLP).
  • Fo-WLP fan-out wafer level package
  • WLCSP 76 is a fan-in wafer level package
  • any combination of semiconductor packages configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52 .
  • electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages.
  • manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
  • FIG. 2 a shows a semiconductor wafer 80 with a base substrate material 82 , such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material for structural support.
  • a plurality of semiconductor die or components 84 is formed on wafer 80 separated by a non-active, inter-die wafer area or saw street 86 as described above.
  • Saw street 86 provides cutting areas to singulate semiconductor wafer 80 into individual semiconductor die 84 .
  • semiconductor wafer 80 has a width or diameter of 100-450 millimeters (mm).
  • FIG. 2 b shows a cross-sectional view of a portion of semiconductor wafer 80 .
  • Each semiconductor die 84 has a back or non-active surface 88 and an active surface 90 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
  • the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 90 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuit.
  • active surface 90 contains a MEMS, such as an accelerometer, gyroscope, strain gauge, microphone, or other sensor responsive to various external stimuli.
  • MEMS such as an accelerometer, gyroscope, strain gauge, microphone, or other sensor responsive to various external stimuli.
  • Semiconductor die 84 may contain baseband circuits that are susceptible to EMI, RFI, and other interference generated by other devices.
  • semiconductor die 84 may contain one or more IPDs that generate EMI or RFI. Therefore, each of these passive circuit elements has the potential to interfere with adjacent devices.
  • An electrically conductive layer 92 is formed over active surface 90 of semiconductor die 84 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • Conductive layer 92 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material or combination thereof.
  • Conductive layer 92 operates as contact pads electrically connected to the circuits on active surface 90 .
  • Conductive layer 92 is formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die 84 , as shown in FIG. 2 b .
  • conductive layer 92 is formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die.
  • back surface 88 of semiconductor wafer 80 undergoes an optional backgrinding operation with a grinder or other suitable mechanical or etching process to remove a portion of base substrate material 82 and reduce the thickness of semiconductor wafer 80 including semiconductor die 84 .
  • Semiconductor wafer 80 undergoes electrical testing and inspection as part of a quality control process.
  • Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 80 .
  • Software can be used in the automated optical analysis of semiconductor wafer 80 .
  • Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, or metallurgical microscope.
  • Semiconductor wafer 80 is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, and discoloration.
  • the active and passive components within semiconductor die 84 undergo testing at the wafer level for electrical performance and circuit function.
  • Each semiconductor die 84 is tested for functionality and electrical parameters, as shown in FIG. 2 c , using a test probe head 94 including a plurality of probes or test leads 96 , or other testing device.
  • Probes 96 are used to make electrical contact with nodes or conductive layer 92 on each semiconductor die 84 and provide electrical stimuli to the contact pads.
  • Semiconductor die 84 responds to the electrical stimuli, which is measured by computer test system 98 and compared to an expected response to test functionality of the semiconductor die.
  • the electrical tests may include circuit functionality, lead integrity, resistivity, continuity, reliability, junction depth, electro-static discharge (ESD), RF performance, drive current, threshold current, leakage current, and operational parameters specific to the component type.
  • ESD electro-static discharge
  • RF performance drive current, threshold current, leakage current, and operational parameters specific to the component type.
  • the inspection and electrical testing of semiconductor wafer 80 enables semiconductor die 84 that pass to be designated as known good die (KGD) for use in a semiconductor package.
  • KGD known good die
  • semiconductor wafer 80 is singulated through saw street 86 using a saw blade or laser cutting tool 100 into individual semiconductor die 84 .
  • Individual semiconductor die 84 can be inspected and electrically tested for identification of KGD post singulation.
  • FIG. 3 a shows a copper clad laminate (CCL) 110 with base material 112 such as metal, silicon, polymer, polymer composite, ceramic, glass, glass epoxy, beryllium oxide, or other suitable low-cost, rigid material or bulk semiconductor material for structural support.
  • base material 112 can be one or more laminated layers of polytetrafluoroethylene pre-impregnated (prepreg), FR-4, FR-1, CEM-1, or CEM-3 with a combination of phenolic cotton paper, epoxy, resin, woven glass, matte glass, polyester, inorganic fillers, and other reinforcement fibers or fabrics.
  • An electrically conductive sheet or layer 114 is formed over a top surface of base material 112 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process.
  • An electrically conductive sheet or layer 116 is formed over a bottom surface of base material 112 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process.
  • Conductive layers 114 and 116 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layers 114 and 116 are Cu foil.
  • FIG. 3 b shows a first metal layer or electrically conductive layer 118 formed over conductive layer 114 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process.
  • a first metal layer or electrically conductive layer 120 is formed over conductive layer 116 .
  • Conductive layers 118 and 120 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • insulating layer 122 is conformally applied to, and has a first surface that follows the contours of, conductive layer 118 , openings including sidewalls of conductive layer 118 and conductive layer 114 .
  • Insulating layer 122 has a second planar surface opposite the first surface.
  • insulating layer 124 is conformally applied to, and has a first surface that follows the contours of, conductive layer 120 , openings including sidewalls of conductive layer 120 and conductive layer 116 .
  • Insulating layer 124 has a second planar surface opposite the first surface.
  • Insulating layers 122 and 124 contain one or more layers of prepreg, photosensitive low curing temperature dielectric resist, photosensitive composite resist, liquid crystal polymer (LCP), laminate compound film, insulation paste with filler, solder mask resist film, liquid molding compound, granular molding compound, polyimide, BCB, PBO, SiO 2 , Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Insulating layers 122 and 124 are deposited using printing, spin coating, spray coating, lamination, or other suitable process.
  • LCP liquid crystal polymer
  • Insulating layers 122 and 124 are deposited using printing, spin coating, spray coating, lamination, or other suitable process.
  • an electrically conductive layer 126 is formed over insulating layer 122 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process.
  • an electrically conductive layer 128 is formed over insulating layer 124 .
  • Conductive layers 126 and 128 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • conductive layers 126 and 128 are patterned to form component attach areas 130 and 132 , respectively. Component attach areas 130 and 132 may be larger, smaller, or identical in size to patterned conductive layer 126 and 128 , respectively.
  • insulating layer 140 is conformally applied to, and has a first surface that follows the contours of, insulating layer 122 and conductive layer 126 .
  • Insulating layer 140 has a second planar surface opposite the first surface.
  • insulating layer 142 is conformally applied to, and has a first surface that follows the contours of, insulating layer 124 and conductive layer 128 .
  • Insulating layer 142 has a second planar surface opposite the first surface.
  • Insulating layers 140 and 142 contain one or more layers of prepreg, photosensitive low curing temperature dielectric resist, photosensitive composite resist, LCP, laminate compound film, insulation paste with filler, solder mask resist film, liquid molding compound, granular molding compound, polyimide, BCB, PBO, SiO 2 , Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Insulating layers 140 and 142 are deposited using printing, spin coating, spray coating, lamination, or other suitable process.
  • a second metal layer or electrically conductive layer 144 is formed over insulating layer 140 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process.
  • a second metal layer or electrically conductive layer 146 is formed over insulating layer 142 .
  • Conductive layers 144 and 146 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • conductive layer 144 is patterned to expose a portion of insulating layer 140 .
  • Insulating layer 140 is patterned and cured using ultraviolet (UV) exposure followed by developing, or other suitable process, or a portion of insulating layer 140 is removed by etching or other suitable process to expose conductive layer 126 at component attach area 130 .
  • a portion of insulating layer 140 is removed by laser direct ablation (LDA) using laser 148 to expose conductive layer 126 at component attach area 130 .
  • conductive layer 146 is patterned to expose a portion of insulating layer 142 .
  • Insulating layer 142 is patterned to expose conductive layer 128 at component attach area 132 .
  • conductive layers 126 and 128 and act as etch stop layers. In one embodiment, a portion of insulating layer 140 exposed by conductive layer 144 remains and is not removed and a portion of insulating layer 142 exposed by conductive layer 146 remains and is not removed.
  • FIG. 3 g shows conductive layers 126 and 128 removed by LDA using laser 148 , etching, or other suitable process to expose portions of insulating layers 122 and 124 , respectively. Insulating layers 122 and 124 are exposed at component attach areas 130 and 132 , respectively.
  • Adhesive layers 150 and 152 can be thermal epoxy, epoxy resin, B-stage epoxy laminating film, UV B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, wire-in-film (WIF) encapsulant material, a suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, or a PI-based adhesive.
  • Adhesive layers 150 and 152 are generally only minimally conductive. In some embodiments, however, adhesive layers 150 and 152 include a non-conductive material.
  • components 154 and 156 are mounted to adhesive layers 150 and 152 at component attach areas 130 and 132 , respectively, using, for example, a pick and place operation.
  • Components 154 and 156 may be semiconductor die 84 from FIG. 2 d and may contain one or more IPDs.
  • Components 154 and 156 may also be discrete passive devices.
  • components 154 and 156 are capacitors.
  • Conductive layers 144 and 146 are disposed on planes, which intersect components 154 and 156 , respectively.
  • conductive layers 144 and 146 are disposed at a midpoint of components 154 and 156 , respectively. In other words, a plane aligned with conductive layer 144 bisects component 154 , and a plane aligned with conductive layer 146 bisects component 156 .
  • insulating layer 160 is conformally applied to, and has a first surface that follows the contours of, insulating layer 140 , conductive layer 144 , adhesive layer 150 , and component 154 .
  • Insulating layer 160 has a second planar surface opposite the first surface.
  • a thickness of insulating layer 160 over a top surface of component 154 is approximately equal to a thickness of insulating layer 122 between adhesive layer 150 and conductive layer 118 , creating a symmetrical substrate.
  • insulating layer 162 is conformally applied to, and has a first surface that follows the contours of, insulating layer 142 , conductive layer 146 , adhesive layer 152 , and component 156 .
  • Insulating layer 162 has a second planar surface opposite the first surface.
  • a thickness of insulating layer 162 under a bottom surface of component 156 is approximately equal to a thickness of insulating layer 124 between adhesive layer 152 and conductive layer 120 , creating a symmetrical substrate.
  • Insulating layers 160 and 162 contain one or more layers of prepreg, photosensitive low curing temperature dielectric resist, photosensitive composite resist, LCP, laminate compound film, insulation paste with filler, solder mask resist film, liquid molding compound, granular molding compound, polyimide, BCB, PBO, SiO 2 , Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.
  • Insulating layers 160 and 162 are deposited using printing, spin coating, spray coating, lamination, or other suitable process.
  • Conductive layer 144 forms an embedded trace structure (ETS) between insulating layers 140 and 160 .
  • conductive layer 146 forms an ETS between insulating layers 142 and 162 .
  • ETS 144 resides in a plane located between a top surface of component 154 and a bottom surface of component 154 .
  • ETS 146 resides in a plane located between a top surface of component 156 and a bottom surface of component 156 .
  • ETS 144 resides in a plane that bisects component 154 .
  • ETS 146 resides in a plane that bisects component 156 .
  • a third metal layer or electrically conductive layer 164 is formed over insulating layer 160 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process.
  • a third metal layer or electrically conductive layer 166 is formed over insulating layer 162 .
  • Conductive layers 164 and 166 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • FIG. 3 k the top and bottom symmetrical EPSs are separated.
  • Base material 112 is removed from symmetrical three layer EPS 170 to expose conductive layer 116 .
  • FIG. 3 l shows a plurality of vias 172 formed through conductive layers 116 , 120 , and 166 , and insulating layers 124 , 142 , and 162 using laser drilling, mechanical drilling, deep reactive ion etching (DRIE), or other suitable process.
  • Vias 172 extend to both a top and a bottom surface of conductive layer or ETS 146 .
  • Vias 172 expose both surfaces of conductive layer or ETS 146 .
  • the plurality of vias 172 is formed using wet/dry etching.
  • the plurality of vias 172 is formed by LDA using laser 148 .
  • vias 172 are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), or other suitable electrically conductive material or combination thereof using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect structures or conductive vias 174 .
  • a conductive layer is formed over the sidewalls of vias 172 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process, and a center portion of vias 172 is filled with a conductive filler material, e.g., Cu paste, or an insulating filler material, e.g., a polymer plug.
  • FIG. 3 n shows conductive layer 116 removed by chemical etching or LDA to expose a surface of conductive layer 120 , insulating layer 124 , and conductive vias 174 .
  • FIG. 3 o shows a symmetrical three layer embedded passive substrate 170 .
  • solder resist or mask 180 is formed over a first side of symmetrical EPS 170 including conductive layer 120 , insulating layer 124 , and conductive vias 174 .
  • Solder resist or mask 180 is also formed over a second side of symmetrical EPS 170 including conductive layer 166 , insulating layer 162 , and conductive vias 174 .
  • Symmetrical EPS 170 of FIG. 3 o includes a symmetrical structure.
  • a thickness of insulating layer 162 over a surface of component 156 is approximately equal to a thickness of insulating layer 124 between adhesive layer 152 and conductive layer 120 and therefore EPS 170 is a symmetrical substrate. Warpage of symmetrical EPS 170 is reduced because a thickness of insulating layer 162 over a surface of component 156 is approximately equal to a thickness of insulating layer 124 between adhesive layer 152 and conductive layer 120 .
  • ETS 146 resides in a plane located between a top surface of component 156 and a bottom surface of component 156 .
  • Second metal layer or ETS 146 of symmetrical EPS 170 resides in a plane, which intersects component 156 . Accordingly, only one conductive layer, conductive layer 120 , is located above component 156 , and only one conductive layer, conductive layer 166 , is located below component 156 of symmetrical three layer EPS 170 . Signal loop length is reduced compared to traditional three layer EPSs because only one conductive layer is located above and below component 156 in symmetrical EPS 170 . Symmetrical EPS 170 is subject to reduced electrical noise as a result of the reduced signal loop length.
  • Symmetrical EPS 170 includes no additional material between insulating layer 124 and conductive layer 120 .
  • Conventional EPS's often have additional material, such as dry film, between the insulating and conductive layers, which can degrade reliability.
  • the reliability of symmetrical EPS 170 is more stable than the reliability of conventional EPS's because symmetrical EPS 170 includes no additional material between insulating layer 124 and conductive layer 120 .
  • FIGS. 4 a -4 c show other symmetrical three layer embedded passive substrates, similar to symmetrical EPS 170 of FIG. 3 o and made by the process described in FIGS. 3 a -3 o .
  • FIG. 4 a shows a portion of a cross-sectional view of symmetrical EPS 190 , similar to symmetrical EPS 170 of FIG. 3 o .
  • Component 156 has a top surface 192 and a bottom surface 194 , opposite the top surface. The height of component 156 is represented as h 1 .
  • Reference plane 196 located at a midpoint of component 156 , bisects component 156 . The distance between bottom surface 194 and reference plane 196 is h 1 / 2 .
  • the height or thickness of insulating layer 124 disposed between first metal layer or conductive layer 120 and adhesive layer 152 is represented as h 2 .
  • the height or thickness of insulating layer 162 disposed between third metal layer or conductive layer 166 and bottom surface 194 of component 156 is represented as h 3 .
  • Height h 2 is approximately equal to height h 3 , meaning that height h 2 has a value between 90% and 110% of the value of height h 3 and therefore EPS 170 is a symmetrical substrate.
  • h 2 equals h 3 .
  • the total height or thickness of the substrate is represented as h 4 .
  • Conductive layer 146 forms an ETS between insulating layers 142 and 162 ; ETS 146 resides in a plane located between top surface 192 of component 156 and bottom surface 194 of component 156 . Second metal layer or ETS 146 of EPS 190 resides in a plane, which intersects component 156 .
  • Warpage of symmetrical EPS 190 is reduced because the value of height h 2 is between 90% and 110% of the value of height h 3 .
  • ETS 146 resides in a plane located between top surface 192 of component 156 and bottom surface 194 of component 156 . Accordingly, only one conductive layer, conductive layer 120 , is located above component 156 , and only one conductive layer, conductive layer 166 , is located below component 156 of symmetrical three layer EPS 190 .
  • Signal loop length is reduced compared to traditional non-symmetrical three layer EPSs because only one conductive layer is located above and below component 156 in symmetrical EPS 190 .
  • Symmetrical EPS 190 is subject to reduced electrical noise as a result of the reduced signal loop length.
  • FIG. 4 a shows a portion of a cross-sectional view of symmetrical EPS 190 .
  • ETS 146 of symmetrical EPS 190 intersects reference plane 196 , which bisects component 156 .
  • Reference plane 196 located at a height of h 1 / 2 , bisects component 156 and passes through ETS or conductive layer 146 .
  • FIG. 4 b shows a portion of a cross-sectional view of symmetrical EPS 198 .
  • ETS 146 of symmetrical EPS 198 resides in a plane located above reference plane 196 , which bisects component 156 .
  • Reference plane 196 located at a height of h 1 / 2 , bisects component 156 and passes below ETS or conductive layer 146 .
  • ETS 146 of EPS 198 resides in a plane located below top surface 192 of component 156 .
  • ETS 146 of EPS 198 resides in a plane located below top surface 192 of component 156 and above reference plane 196 , which bisects component 156 .
  • FIG. 4 c shows a portion of a cross-sectional view of symmetrical EPS 200 .
  • ETS 146 of symmetrical EPS 200 resides in a plane located below reference plane 196 , which bisects component 156 .
  • Reference plane 196 located at a height of h 1 / 2 , bisects component 156 and passes above ETS or conductive layer 146 .
  • ETS 146 of EPS 200 resides in a plane located above bottom surface 194 of component 156 .
  • ETS 146 of EPS 198 resides in a plane located above bottom surface 194 of component 156 and below reference plane 196 , which bisects component 156 .

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Abstract

A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.

Description

FIELD OF THE INVENTION
The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a substrate including an embedded component with a symmetrical structure.
BACKGROUND OF THE INVENTION
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, and various signal processing circuits.
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows the material's electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support, electrical interconnect, and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a thinner profile or a smaller footprint by improvements in electrical interconnection and packaging materials.
Another goal of semiconductor manufacturing is to produce higher performance semiconductor devices. Increases in device performance can be accomplished by forming active components that are capable of operating at higher speeds. In high frequency applications, such as radio frequency (RF) wireless communications, integrated passive devices (IPDs) are often contained within the semiconductor device. Examples of IPDs include resistors, capacitors, and inductors. A typical RF system requires multiple IPDs in one or more semiconductor packages to perform the necessary electrical functions. One method of incorporating IPDs into a system is to embed the IPDs in a substrate to form an embedded passive substrate (EPS). In a conventional EPS one metal layer is formed directly over the passive component and the other metal layer is formed under the passive component, between stacked thick insulating layers. The multiple levels of metal layers and insulating layers cause uneven heat management and long signal loop lengths. Accordingly, conventional EPSs are prone to warpage and electrical noise issues.
SUMMARY OF THE INVENTION
A need exists to embed semiconductor components into a substrate with reduced substrate warpage and shorter signal loop length. Accordingly, in one embodiment, the present invention is a semiconductor device comprising a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure.
In another embodiment, the present invention is a semiconductor device comprising a first insulating layer. A first conductive layer is formed over the first insulating layer. A semiconductor component is disposed over the first insulating layer. The first conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate including a first conductive layer, forming a second conductive layer over the first conductive layer, and disposing a semiconductor component over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. The method further includes the step of forming a third conductive layer over the semiconductor component opposite the first conductive layer.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, forming a first conductive layer over the substrate, and disposing a semiconductor component over the substrate. The first conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a printed circuit board (PCB) with different types of packages mounted to its surface;
FIGS. 2a-2d illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;
FIGS. 3a-3o illustrate a process of forming a substrate with an embedded passive device and a symmetrical structure; and
FIGS. 4a-4c illustrate other substrates with an embedded passive device and a symmetrical structure.
 DETAILED DESCRIPTION OF THE DRAWINGS
The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving objectives of the invention, those skilled in the art will appreciate that the disclosure is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and claims equivalents as supported by the following disclosure and drawings.
Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.
Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices by dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
FIG. 1 illustrates electronic device 50 having a chip carrier substrate or PCB 52 with a plurality of semiconductor packages mounted on a surface of PCB 52. Electronic device 50 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in FIG. 1 for purposes of illustration.
Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 can be a subcomponent of a larger system. For example, electronic device 50 can be part of a tablet, cellular phone, digital camera, or other electronic device. Alternatively, electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), microelectromechanical systems (MEMS), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.
In FIG. 1, PCB 52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces 54 are formed over a surface or within layers of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 54 also provide power and ground connections to each of the semiconductor packages.
In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
For the purpose of illustration, several types of first level packaging, including bond wire package 56 and flipchip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, quad flat package 72, embedded wafer level ball grid array (eWLB) 74, and wafer level chip scale package (WLCSP) 76 are shown mounted on PCB 52. In one embodiment, eWLB 74 is a fan-out wafer level package (Fo-WLP) and WLCSP 76 is a fan-in wafer level package (Fi-WLP). Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
FIG. 2a shows a semiconductor wafer 80 with a base substrate material 82, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material for structural support. A plurality of semiconductor die or components 84 is formed on wafer 80 separated by a non-active, inter-die wafer area or saw street 86 as described above. Saw street 86 provides cutting areas to singulate semiconductor wafer 80 into individual semiconductor die 84. In one embodiment, semiconductor wafer 80 has a width or diameter of 100-450 millimeters (mm).
FIG. 2b shows a cross-sectional view of a portion of semiconductor wafer 80. Each semiconductor die 84 has a back or non-active surface 88 and an active surface 90 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 90 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuit. In one embodiment, active surface 90 contains a MEMS, such as an accelerometer, gyroscope, strain gauge, microphone, or other sensor responsive to various external stimuli.
Semiconductor die 84 may contain baseband circuits that are susceptible to EMI, RFI, and other interference generated by other devices. In one embodiment, semiconductor die 84 may contain one or more IPDs that generate EMI or RFI. Therefore, each of these passive circuit elements has the potential to interfere with adjacent devices.
An electrically conductive layer 92 is formed over active surface 90 of semiconductor die 84 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 92 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material or combination thereof. Conductive layer 92 operates as contact pads electrically connected to the circuits on active surface 90. Conductive layer 92 is formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die 84, as shown in FIG. 2b . Alternatively, conductive layer 92 is formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die. In one embodiment, back surface 88 of semiconductor wafer 80 undergoes an optional backgrinding operation with a grinder or other suitable mechanical or etching process to remove a portion of base substrate material 82 and reduce the thickness of semiconductor wafer 80 including semiconductor die 84.
Semiconductor wafer 80 undergoes electrical testing and inspection as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 80. Software can be used in the automated optical analysis of semiconductor wafer 80. Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, or metallurgical microscope. Semiconductor wafer 80 is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, and discoloration.
The active and passive components within semiconductor die 84 undergo testing at the wafer level for electrical performance and circuit function. Each semiconductor die 84 is tested for functionality and electrical parameters, as shown in FIG. 2c , using a test probe head 94 including a plurality of probes or test leads 96, or other testing device. Probes 96 are used to make electrical contact with nodes or conductive layer 92 on each semiconductor die 84 and provide electrical stimuli to the contact pads. Semiconductor die 84 responds to the electrical stimuli, which is measured by computer test system 98 and compared to an expected response to test functionality of the semiconductor die. The electrical tests may include circuit functionality, lead integrity, resistivity, continuity, reliability, junction depth, electro-static discharge (ESD), RF performance, drive current, threshold current, leakage current, and operational parameters specific to the component type. The inspection and electrical testing of semiconductor wafer 80 enables semiconductor die 84 that pass to be designated as known good die (KGD) for use in a semiconductor package.
In FIG. 2d , semiconductor wafer 80 is singulated through saw street 86 using a saw blade or laser cutting tool 100 into individual semiconductor die 84. Individual semiconductor die 84 can be inspected and electrically tested for identification of KGD post singulation.
FIG. 3a shows a copper clad laminate (CCL) 110 with base material 112 such as metal, silicon, polymer, polymer composite, ceramic, glass, glass epoxy, beryllium oxide, or other suitable low-cost, rigid material or bulk semiconductor material for structural support. Alternatively, base material 112 can be one or more laminated layers of polytetrafluoroethylene pre-impregnated (prepreg), FR-4, FR-1, CEM-1, or CEM-3 with a combination of phenolic cotton paper, epoxy, resin, woven glass, matte glass, polyester, inorganic fillers, and other reinforcement fibers or fabrics.
An electrically conductive sheet or layer 114 is formed over a top surface of base material 112 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. An electrically conductive sheet or layer 116 is formed over a bottom surface of base material 112 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Conductive layers 114 and 116 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layers 114 and 116 are Cu foil.
FIG. 3b shows a first metal layer or electrically conductive layer 118 formed over conductive layer 114 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Similarly, a first metal layer or electrically conductive layer 120 is formed over conductive layer 116. Conductive layers 118 and 120 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
In FIG. 3c , insulating layer 122 is conformally applied to, and has a first surface that follows the contours of, conductive layer 118, openings including sidewalls of conductive layer 118 and conductive layer 114. Insulating layer 122 has a second planar surface opposite the first surface. Similarly, insulating layer 124 is conformally applied to, and has a first surface that follows the contours of, conductive layer 120, openings including sidewalls of conductive layer 120 and conductive layer 116. Insulating layer 124 has a second planar surface opposite the first surface. Insulating layers 122 and 124 contain one or more layers of prepreg, photosensitive low curing temperature dielectric resist, photosensitive composite resist, liquid crystal polymer (LCP), laminate compound film, insulation paste with filler, solder mask resist film, liquid molding compound, granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Insulating layers 122 and 124 are deposited using printing, spin coating, spray coating, lamination, or other suitable process.
In FIG. 3d , an electrically conductive layer 126 is formed over insulating layer 122 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Similarly, an electrically conductive layer 128 is formed over insulating layer 124. Conductive layers 126 and 128 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layers 126 and 128 are patterned to form component attach areas 130 and 132, respectively. Component attach areas 130 and 132 may be larger, smaller, or identical in size to patterned conductive layer 126 and 128, respectively.
In FIG. 3e , insulating layer 140 is conformally applied to, and has a first surface that follows the contours of, insulating layer 122 and conductive layer 126. Insulating layer 140 has a second planar surface opposite the first surface. Similarly, insulating layer 142 is conformally applied to, and has a first surface that follows the contours of, insulating layer 124 and conductive layer 128. Insulating layer 142 has a second planar surface opposite the first surface. Insulating layers 140 and 142 contain one or more layers of prepreg, photosensitive low curing temperature dielectric resist, photosensitive composite resist, LCP, laminate compound film, insulation paste with filler, solder mask resist film, liquid molding compound, granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Insulating layers 140 and 142 are deposited using printing, spin coating, spray coating, lamination, or other suitable process.
A second metal layer or electrically conductive layer 144 is formed over insulating layer 140 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Similarly, a second metal layer or electrically conductive layer 146 is formed over insulating layer 142. Conductive layers 144 and 146 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
In FIG. 3f , conductive layer 144 is patterned to expose a portion of insulating layer 140. Insulating layer 140 is patterned and cured using ultraviolet (UV) exposure followed by developing, or other suitable process, or a portion of insulating layer 140 is removed by etching or other suitable process to expose conductive layer 126 at component attach area 130. In one embodiment, a portion of insulating layer 140 is removed by laser direct ablation (LDA) using laser 148 to expose conductive layer 126 at component attach area 130. Similarly, conductive layer 146 is patterned to expose a portion of insulating layer 142. Insulating layer 142 is patterned to expose conductive layer 128 at component attach area 132. In one embodiment, conductive layers 126 and 128 and act as etch stop layers. In one embodiment, a portion of insulating layer 140 exposed by conductive layer 144 remains and is not removed and a portion of insulating layer 142 exposed by conductive layer 146 remains and is not removed.
FIG. 3g shows conductive layers 126 and 128 removed by LDA using laser 148, etching, or other suitable process to expose portions of insulating layers 122 and 124, respectively. Insulating layers 122 and 124 are exposed at component attach areas 130 and 132, respectively.
In FIG. 3h , an adhesive layer 150 is formed over insulating layer 122 at component attach area 130. Similarly, an adhesive layer 152 is formed over insulating layer 124 at component attach area 132. Adhesive layers 150 and 152 can be thermal epoxy, epoxy resin, B-stage epoxy laminating film, UV B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, wire-in-film (WIF) encapsulant material, a suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, or a PI-based adhesive. Adhesive layers 150 and 152 are generally only minimally conductive. In some embodiments, however, adhesive layers 150 and 152 include a non-conductive material.
In FIG. 3i , components 154 and 156 are mounted to adhesive layers 150 and 152 at component attach areas 130 and 132, respectively, using, for example, a pick and place operation. Components 154 and 156 may be semiconductor die 84 from FIG. 2d and may contain one or more IPDs. Components 154 and 156 may also be discrete passive devices. In one embodiment, components 154 and 156 are capacitors. Conductive layers 144 and 146 are disposed on planes, which intersect components 154 and 156, respectively. In one embodiment, conductive layers 144 and 146 are disposed at a midpoint of components 154 and 156, respectively. In other words, a plane aligned with conductive layer 144 bisects component 154, and a plane aligned with conductive layer 146 bisects component 156.
In FIG. 3j , insulating layer 160 is conformally applied to, and has a first surface that follows the contours of, insulating layer 140, conductive layer 144, adhesive layer 150, and component 154. Insulating layer 160 has a second planar surface opposite the first surface. A thickness of insulating layer 160 over a top surface of component 154 is approximately equal to a thickness of insulating layer 122 between adhesive layer 150 and conductive layer 118, creating a symmetrical substrate. Similarly, insulating layer 162 is conformally applied to, and has a first surface that follows the contours of, insulating layer 142, conductive layer 146, adhesive layer 152, and component 156. Insulating layer 162 has a second planar surface opposite the first surface. A thickness of insulating layer 162 under a bottom surface of component 156 is approximately equal to a thickness of insulating layer 124 between adhesive layer 152 and conductive layer 120, creating a symmetrical substrate. Insulating layers 160 and 162 contain one or more layers of prepreg, photosensitive low curing temperature dielectric resist, photosensitive composite resist, LCP, laminate compound film, insulation paste with filler, solder mask resist film, liquid molding compound, granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Insulating layers 160 and 162 are deposited using printing, spin coating, spray coating, lamination, or other suitable process.
Conductive layer 144 forms an embedded trace structure (ETS) between insulating layers 140 and 160. Similarly, conductive layer 146 forms an ETS between insulating layers 142 and 162. ETS 144 resides in a plane located between a top surface of component 154 and a bottom surface of component 154. ETS 146 resides in a plane located between a top surface of component 156 and a bottom surface of component 156. In one embodiment, ETS 144 resides in a plane that bisects component 154. In one embodiment, ETS 146 resides in a plane that bisects component 156.
A third metal layer or electrically conductive layer 164 is formed over insulating layer 160 using a patterning and metal deposition process such as silk screen printing, photoengraving, PCB milling, printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Similarly, a third metal layer or electrically conductive layer 166 is formed over insulating layer 162. Conductive layers 164 and 166 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
In FIG. 3k , the top and bottom symmetrical EPSs are separated. Base material 112 is removed from symmetrical three layer EPS 170 to expose conductive layer 116.
FIG. 3l shows a plurality of vias 172 formed through conductive layers 116, 120, and 166, and insulating layers 124, 142, and 162 using laser drilling, mechanical drilling, deep reactive ion etching (DRIE), or other suitable process. Vias 172 extend to both a top and a bottom surface of conductive layer or ETS 146. Vias 172 expose both surfaces of conductive layer or ETS 146. In one embodiment, the plurality of vias 172 is formed using wet/dry etching. In one embodiment, the plurality of vias 172 is formed by LDA using laser 148.
In FIG. 3m , vias 172 are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), or other suitable electrically conductive material or combination thereof using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect structures or conductive vias 174. Alternatively, a conductive layer is formed over the sidewalls of vias 172 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process, and a center portion of vias 172 is filled with a conductive filler material, e.g., Cu paste, or an insulating filler material, e.g., a polymer plug.
FIG. 3n shows conductive layer 116 removed by chemical etching or LDA to expose a surface of conductive layer 120, insulating layer 124, and conductive vias 174.
FIG. 3o shows a symmetrical three layer embedded passive substrate 170. In FIG. 3o , solder resist or mask 180 is formed over a first side of symmetrical EPS 170 including conductive layer 120, insulating layer 124, and conductive vias 174. Solder resist or mask 180 is also formed over a second side of symmetrical EPS 170 including conductive layer 166, insulating layer 162, and conductive vias 174.
Symmetrical EPS 170 of FIG. 3o includes a symmetrical structure. A thickness of insulating layer 162 over a surface of component 156 is approximately equal to a thickness of insulating layer 124 between adhesive layer 152 and conductive layer 120 and therefore EPS 170 is a symmetrical substrate. Warpage of symmetrical EPS 170 is reduced because a thickness of insulating layer 162 over a surface of component 156 is approximately equal to a thickness of insulating layer 124 between adhesive layer 152 and conductive layer 120. ETS 146 resides in a plane located between a top surface of component 156 and a bottom surface of component 156. Second metal layer or ETS 146 of symmetrical EPS 170 resides in a plane, which intersects component 156. Accordingly, only one conductive layer, conductive layer 120, is located above component 156, and only one conductive layer, conductive layer 166, is located below component 156 of symmetrical three layer EPS 170. Signal loop length is reduced compared to traditional three layer EPSs because only one conductive layer is located above and below component 156 in symmetrical EPS 170. Symmetrical EPS 170 is subject to reduced electrical noise as a result of the reduced signal loop length. Because ETS 146 resides in a plane located between a top surface of component 156 and a bottom surface of component 156, rather than below component 156, the total substrate thickness of symmetrical EPS 170 is reduced compared to a conventional three layer EPS. Symmetrical EPS 170 includes no additional material between insulating layer 124 and conductive layer 120. Conventional EPS's often have additional material, such as dry film, between the insulating and conductive layers, which can degrade reliability. The reliability of symmetrical EPS 170 is more stable than the reliability of conventional EPS's because symmetrical EPS 170 includes no additional material between insulating layer 124 and conductive layer 120.
FIGS. 4a-4c show other symmetrical three layer embedded passive substrates, similar to symmetrical EPS 170 of FIG. 3o and made by the process described in FIGS. 3a-3o . FIG. 4a shows a portion of a cross-sectional view of symmetrical EPS 190, similar to symmetrical EPS 170 of FIG. 3o . Component 156 has a top surface 192 and a bottom surface 194, opposite the top surface. The height of component 156 is represented as h1. Reference plane 196, located at a midpoint of component 156, bisects component 156. The distance between bottom surface 194 and reference plane 196 is h1/2. The height or thickness of insulating layer 124 disposed between first metal layer or conductive layer 120 and adhesive layer 152 is represented as h2. The height or thickness of insulating layer 162 disposed between third metal layer or conductive layer 166 and bottom surface 194 of component 156 is represented as h3. Height h2 is approximately equal to height h3, meaning that height h2 has a value between 90% and 110% of the value of height h3 and therefore EPS 170 is a symmetrical substrate. In one embodiment, h2 equals h3. The total height or thickness of the substrate is represented as h4. Conductive layer 146 forms an ETS between insulating layers 142 and 162; ETS 146 resides in a plane located between top surface 192 of component 156 and bottom surface 194 of component 156. Second metal layer or ETS 146 of EPS 190 resides in a plane, which intersects component 156.
Warpage of symmetrical EPS 190 is reduced because the value of height h2 is between 90% and 110% of the value of height h3. ETS 146 resides in a plane located between top surface 192 of component 156 and bottom surface 194 of component 156. Accordingly, only one conductive layer, conductive layer 120, is located above component 156, and only one conductive layer, conductive layer 166, is located below component 156 of symmetrical three layer EPS 190. Signal loop length is reduced compared to traditional non-symmetrical three layer EPSs because only one conductive layer is located above and below component 156 in symmetrical EPS 190. Symmetrical EPS 190 is subject to reduced electrical noise as a result of the reduced signal loop length. Because ETS 146 resides in a plane located between a top surface of component 156 and a bottom surface of component 156, rather than below component 156, total substrate thickness h4 of symmetrical EPS 190 is reduced compared to a conventional three layer EPS. The reliability of symmetrical EPS 190 is more stable than the reliability of conventional EPS's because symmetrical EPS 190 includes no additional material between insulating layer 124 and conductive layer 120.
FIG. 4a shows a portion of a cross-sectional view of symmetrical EPS 190. ETS 146 of symmetrical EPS 190 intersects reference plane 196, which bisects component 156. Reference plane 196, located at a height of h1/2, bisects component 156 and passes through ETS or conductive layer 146.
FIG. 4b shows a portion of a cross-sectional view of symmetrical EPS 198. ETS 146 of symmetrical EPS 198 resides in a plane located above reference plane 196, which bisects component 156. Reference plane 196, located at a height of h1/2, bisects component 156 and passes below ETS or conductive layer 146. ETS 146 of EPS 198 resides in a plane located below top surface 192 of component 156. ETS 146 of EPS 198 resides in a plane located below top surface 192 of component 156 and above reference plane 196, which bisects component 156.
FIG. 4c shows a portion of a cross-sectional view of symmetrical EPS 200. ETS 146 of symmetrical EPS 200 resides in a plane located below reference plane 196, which bisects component 156. Reference plane 196, located at a height of h1/2, bisects component 156 and passes above ETS or conductive layer 146. ETS 146 of EPS 200 resides in a plane located above bottom surface 194 of component 156. ETS 146 of EPS 198 resides in a plane located above bottom surface 194 of component 156 and below reference plane 196, which bisects component 156.
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (24)

What is claimed:
1. A method of making a semiconductor device, comprising:
providing a substrate including a first conductive layer;
forming a first insulating layer over the first conductive layer;
forming a fourth conductive layer over the first insulating layer;
forming a third insulating layer over the first insulating layer and fourth conductive layer;
forming a second conductive layer over the first conductive layer and third insulating layer;
forming an opening through the third insulating layer over the fourth conductive layer;
removing the fourth conductive layer;
disposing a semiconductor component in the opening of the third insulating layer such that the second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component;
forming a second insulating layer over the semiconductor component; and
forming a third conductive layer over the second insulating layer.
2. The method of claim 1, wherein the semiconductor component includes a capacitor.
3. The method of claim 1, further including forming a conductive via through the first insulating layer and third insulating layer by forming a first opening through the first conductive layer, first insulating layer, and third insulating layer to expose the second conductive layer.
4. The method of claim 3, further including forming a second opening through the second insulating layer to expose the second conductive layer directly opposite the first opening.
5. The method of claim 1, further including forming a first opening through the first insulating layer to expose a terminal of the semiconductor component.
6. The method of claim 5, further including forming a second opening through the second insulating layer to expose the terminal of the semiconductor component directly opposite the first opening.
7. A method of making a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
forming a first insulating layer including an opening through the first insulating layer over the first conductive layer;
forming a second conductive layer over the first insulating layer;
removing the first conductive layer within the opening; and
disposing a semiconductor component over the substrate in the opening of the first insulating layer such that the second conductive layer is approximately centered between a top surface of the semiconductor component and a bottom surface of the semiconductor component.
8. The method of claim 7, further including forming a second insulating layer over the semiconductor component.
9. The method of claim 8, wherein the semiconductor device includes a vertically symmetrical structure.
10. The method of claim 8 further including forming a third conductive layer over the second insulating layer opposite the semiconductor component.
11. The method of claim 7, wherein the second conductive layer lies in a plane that bisects the semiconductor component.
12. The method of claim 7, wherein the semiconductor component includes a passive device.
13. A method of making a semiconductor device, comprising:
providing a first conductive layer;
forming a first insulating layer over the first conductive layer;
forming a second conductive layer over the first insulating layer;
disposing a semiconductor component over the first conductive layer with the second conductive layer within a height of the semiconductor component;
forming a second insulating layer over the semiconductor component, wherein a height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer; and
forming a third conductive layer over the second insulating layer.
14. The method of claim 13, further including forming the semiconductor device to include a symmetrical structure.
15. The method of claim 13, wherein disposing a semiconductor component over the first conductive layer includes disposing the semiconductor component with the second conductive layer lying in a plane that bisects the semiconductor component.
16. The method of claim 13, further including providing the semiconductor component to include a capacitor.
17. The method of claim 13, further including providing the semiconductor component to include a passive device.
18. The method of claim 13, further including forming an opening through the first insulating layer or second insulating layer to expose a terminal of the semiconductor component.
19. The method of claim 13, further including forming an opening through the first insulating layer or second insulating layer to expose the second conductive layer.
20. A method of making a semiconductor device, comprising:
providing a first insulating layer;
forming a first conductive layer over the first insulating layer;
disposing a semiconductor component over the first insulating layer with the first conductive layer approximately centered within a height of the semiconductor component; and
forming a second insulating layer over the semiconductor component, wherein a height of the first insulating layer under a first surface of the semiconductor component is between 90% and 110% of a height of the second insulating layer over a second surface of the semiconductor component opposite the first surface.
21. The method of claim 20, further including forming the semiconductor device to include a vertically symmetrical structure.
22. The method of claim 20, further including:
providing a second conductive layer;
disposing the first insulating layer over the second conductive layer; and
forming a third conductive layer over the second insulating layer.
23. The method of claim 20, wherein disposing the semiconductor component over the first insulating layer includes disposing the semiconductor component over the first insulating layer with the first conductive layer in a plane that bisects the semiconductor component.
24. The method of claim 20, further including providing the semiconductor component to include a passive device.
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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
US20190172902A1 (en) * 2015-05-27 2019-06-06 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
US11264331B2 (en) * 2019-05-10 2022-03-01 Applied Materials, Inc. Package structure and fabrication methods
US11362235B2 (en) 2019-05-10 2022-06-14 Applied Materials, Inc. Substrate structuring methods
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US11742330B2 (en) 2020-03-10 2023-08-29 Applied Materials, Inc. High connectivity device stacking
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US12183684B2 (en) 2021-10-26 2024-12-31 Applied Materials, Inc. Semiconductor device packaging methods
US12358073B2 (en) 2020-07-14 2025-07-15 Applied Materials, Inc. Method and apparatus for laser drilling blind vias

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017105520A1 (en) * 2015-12-18 2017-06-22 Intel Corporation Transmissive composite film for application to the backside of a microelectronic device
EP3355667A1 (en) * 2017-01-30 2018-08-01 Siemens Aktiengesellschaft Method for producing an electrical circuit and electrical circuit
US10440828B2 (en) * 2017-04-14 2019-10-08 The Diller Corporation Integrated electrical component within laminate
US11277917B2 (en) * 2019-03-12 2022-03-15 Advanced Semiconductor Engineering, Inc. Embedded component package structure, embedded type panel substrate and manufacturing method thereof
KR20200133072A (en) * 2019-05-16 2020-11-26 삼성전자주식회사 Image Sensor Package
TWI780876B (en) * 2021-08-25 2022-10-11 旭德科技股份有限公司 Package carrier and package structure

Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5491362A (en) * 1992-04-30 1996-02-13 Vlsi Technology, Inc. Package structure having accessible chip
US6214525B1 (en) * 1996-09-06 2001-04-10 International Business Machines Corp. Printed circuit board with circuitized cavity and methods of producing same
US20040183192A1 (en) * 2003-01-31 2004-09-23 Masashi Otsuka Semiconductor device assembled into a chip size package
US20050230835A1 (en) * 2004-04-20 2005-10-20 Shinko Electric Industries Co., Ltd. Semiconductor device
US20060003495A1 (en) * 2004-06-30 2006-01-05 Masahiro Sunohara Method for fabricating an electronic component embedded substrate
US20060145331A1 (en) * 2004-12-30 2006-07-06 Samsung Electro-Mechanics Co., Ltd. Printed circuit board including embedded chips and method of fabricating the same using plating
US20060191711A1 (en) * 2005-02-28 2006-08-31 Samsung Electro-Mechanics Co., Ltd. Embedded chip printed circuit board and method of manufacturing the same
US20070052086A1 (en) * 2004-05-17 2007-03-08 Shinko Electric Industries Co., Ltd. Electronic parts and method of manufacturing electronic parts packaging structure
US20070069363A1 (en) * 2005-09-28 2007-03-29 Tdk Corporation Semiconductor IC-embedded substrate and method for manufacturing same
US20070141759A1 (en) * 2005-12-19 2007-06-21 Tdk Corporation Method for manufacturing ic-embedded substrate
US20070155060A1 (en) * 2002-09-30 2007-07-05 Sony Corporation Method for manufacturing high-frequency module device
US7341890B2 (en) * 2003-07-09 2008-03-11 Matsushita Industrial Co., Ltd. Circuit board with built-in electronic component and method for manufacturing the same
US20080196931A1 (en) * 2007-02-15 2008-08-21 Samsung Electro-Mechanics Co., Ltd. Printed circuit board having embedded components and method for manufacturing thereof
US20080211086A1 (en) * 2006-12-22 2008-09-04 Tdk Corporation Mounting method of electronic components, manufacturing method of electronic component-embedded substrate, and electronic component-embedded substrate
US20090224378A1 (en) * 2008-03-04 2009-09-10 Advanced Semiconductor Engineering, Inc. Package structure with embedded die and method of fabricating the same
US20100019368A1 (en) * 2008-07-25 2010-01-28 Samsung Electronics Co., Ltd. Semiconductor chip package, stacked package comprising semiconductor chips and methods of fabricating chip and stacked packages
US20110100689A1 (en) * 2009-10-29 2011-05-05 Byun Jung-Soo Electronics component embedded pcb
US20110176246A1 (en) * 2010-01-19 2011-07-21 Samsung Electro-Mechanics Co., Ltd. Pcb strip and manufacturing method for electronic component embedded pcb
US20110216515A1 (en) * 2010-03-05 2011-09-08 Samsung Electro-Mechanics Co., Ltd. Electro device embedded printed circuit board and manufacturing method thereof
US20110214913A1 (en) * 2010-03-05 2011-09-08 Samsung Electro-Machanics Co., Ltd. Electro device embedded printed circuit board and manufacturng method thereof
US20110228464A1 (en) * 2010-03-17 2011-09-22 Guzek John S System-in-package using embedded-die coreless substrates, and processes of forming same
US20110290546A1 (en) * 2010-05-28 2011-12-01 Samsung Electro-Mechanics Co., Ltd. Printed circuit board having electronic component and method for manufacturing thereof
US20120037404A1 (en) * 2010-08-13 2012-02-16 Unimicron Technology Corporation Packaging substrate having a passive element embedded therein and method of fabricating the same
US20120037411A1 (en) 2010-08-13 2012-02-16 Unimicron Technology Corporation Packaging substrate having embedded passive component and fabrication method thereof
US20120199971A1 (en) * 2008-07-14 2012-08-09 Stats Chippac, Ltd. Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier
US20120293973A1 (en) * 2005-08-29 2012-11-22 Shinko Electric Industries Co., Ltd. Multilayered wiring board and method for fabricating the same
US20130140683A1 (en) * 2009-08-07 2013-06-06 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die
US20130285254A1 (en) * 2012-04-26 2013-10-31 Shinko Electric Industries Co., Ltd. Wiring substrate and method for manufacturing wiring subtrate
US20140070396A1 (en) * 2012-09-12 2014-03-13 Shinko Electric Industries Co., Ltd. Semiconductor package and manufacturing method
US20140097009A1 (en) * 2012-10-05 2014-04-10 Shinko Electric Industries Co., Ltd. Wiring substrate
US20140182897A1 (en) * 2012-12-31 2014-07-03 Samsung Electro-Mechanics Co., Ltd. Circuit board and method of manufacturing the same
US8772924B2 (en) * 2010-04-06 2014-07-08 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US20140321084A1 (en) * 2013-04-26 2014-10-30 Samsung Electro-Mechanics Co., Ltd. Printed circuit board including electronic component embedded therein and method for manufacturing the same
US20150001708A1 (en) * 2013-06-28 2015-01-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package
US20150014861A1 (en) * 2012-09-29 2015-01-15 Intel Corporation Embedded structures for package-on-package architecture
US20150091176A1 (en) * 2013-10-01 2015-04-02 Infineon Technologies Austria Ag Electronic Component, Arrangement and Method
US20150171002A1 (en) * 2013-12-16 2015-06-18 Dong Ju Jeon Integrated circuit packaging system with embedded component and method of manufacture thereof
US20150245473A1 (en) * 2014-02-27 2015-08-27 Shinko Electric Industries Co., Ltd. Wiring Substrate, Semiconductor Device, and Method of Manufacturing Wiring Substrate
US9627227B2 (en) * 2011-06-30 2017-04-18 Intel Corporation Bumpless build-up layer package warpage reduction

Family Cites Families (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5344592A (en) * 1993-02-16 1994-09-06 E. I. Du Pont De Nemours And Company Organic vehicle for electronic composition
DE69626747T2 (en) * 1995-11-16 2003-09-04 Matsushita Electric Industrial Co., Ltd. Printed circuit board and its arrangement
EP1895586A3 (en) * 1997-10-17 2013-04-03 Ibiden Co., Ltd. Semiconductor package substrate
JP3659167B2 (en) * 1999-04-16 2005-06-15 松下電器産業株式会社 Module parts and manufacturing method thereof
JP4646370B2 (en) * 1999-09-02 2011-03-09 イビデン株式会社 Printed wiring board and printed wiring board manufacturing method
JP4103549B2 (en) * 2002-10-31 2008-06-18 株式会社デンソー Multilayer wiring board manufacturing method and multilayer wiring board
JP4354227B2 (en) * 2003-07-23 2009-10-28 Ｔｄｋ株式会社 Solid electrolytic capacitor
KR100645643B1 (en) * 2004-07-14 2006-11-15 삼성전기주식회사 Manufacturing Method of Printed Circuit Board with Passive Device Chip
KR100598275B1 (en) * 2004-09-15 2006-07-10 삼성전기주식회사 Passive element embedded printed circuit board and its manufacturing method
JP2006165175A (en) * 2004-12-06 2006-06-22 Alps Electric Co Ltd Circuit component module, electronic circuit device, and circuit component module manufacturing method
TWI245388B (en) * 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
TWI255518B (en) * 2005-01-19 2006-05-21 Via Tech Inc Chip package
TWI336608B (en) * 2006-01-31 2011-01-21 Sony Corp Printed circuit board assembly and method of manufacturing the same
JP2008091357A (en) * 2006-09-29 2008-04-17 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US7982135B2 (en) * 2006-10-30 2011-07-19 Ibiden Co., Ltd. Flex-rigid wiring board and method of manufacturing the same
US8093506B2 (en) * 2006-12-21 2012-01-10 Ngk Spark Plug Co., Ltd. Multilayer wiring board and power supply structure to be embedded in multilayer wiring board
JP5395360B2 (en) * 2008-02-25 2014-01-22 新光電気工業株式会社 Manufacturing method of electronic component built-in substrate
KR100966638B1 (en) * 2008-03-25 2010-06-29 삼성전기주식회사 Capacitor embedded printed circuit board and its manufacturing method
JP2009290124A (en) * 2008-05-30 2009-12-10 Fujitsu Ltd Printed wiring board
TWI363411B (en) * 2008-07-22 2012-05-01 Advanced Semiconductor Eng Embedded chip substrate and fabrication method thereof
US8261435B2 (en) * 2008-12-29 2012-09-11 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP4973761B2 (en) * 2009-05-25 2012-07-11 株式会社デンソー Semiconductor device
JP2011014728A (en) * 2009-07-02 2011-01-20 Casio Computer Co Ltd Semiconductor device and method of manufacturing semiconductor device
AT12319U1 (en) * 2009-07-10 2012-03-15 Austria Tech & System Tech METHOD FOR PRODUCING A PCB CONTAINING AT LEAST TWO PCB SURFACES AND PCB
JP5632479B2 (en) * 2009-10-08 2014-11-26 エルジー イノテック カンパニー リミテッド Optical printed circuit board and manufacturing method thereof
TW201127246A (en) * 2010-01-22 2011-08-01 Ibiden Co Ltd Flex-rigid wiring board and method for manufacturing the same
TW201127228A (en) * 2010-01-22 2011-08-01 Ibiden Co Ltd Flex-rigid wiring board and method for manufacturing the same
US20130003314A1 (en) * 2010-02-22 2013-01-03 Sanyo Electronic Co., Ltd. Multilayer printed circuit board and manufacturing method therefor
US8586875B2 (en) * 2010-02-26 2013-11-19 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US8558392B2 (en) * 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US9406658B2 (en) * 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8736065B2 (en) * 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
JP2013038374A (en) * 2011-01-20 2013-02-21 Ibiden Co Ltd Wiring board and manufacturing method of the same
JP2012151372A (en) * 2011-01-20 2012-08-09 Ibiden Co Ltd Wiring board and manufacturing method of the same
JP2012164952A (en) * 2011-01-20 2012-08-30 Ibiden Co Ltd Wiring board with built-in electronic component and method of manufacturing the same
JP5146627B2 (en) * 2011-02-15 2013-02-20 株式会社村田製作所 Multilayer wiring board and manufacturing method thereof
JP2012186440A (en) * 2011-02-18 2012-09-27 Ibiden Co Ltd Inductor component, printed circuit board incorporating the component, and manufacturing method of the inductor component
US8923008B2 (en) * 2011-03-08 2014-12-30 Ibiden Co., Ltd. Circuit board and method for manufacturing circuit board
US8745860B2 (en) * 2011-03-11 2014-06-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board
JP2012204831A (en) * 2011-03-23 2012-10-22 Ibiden Co Ltd Electronic component built-in wiring board and manufacturing method of the same
WO2012157426A1 (en) * 2011-05-13 2012-11-22 イビデン株式会社 Circuit board and manufacturing method thereof
KR20130014122A (en) * 2011-07-29 2013-02-07 삼성전기주식회사 Electronic components embedded pcb and method for manufacturing thereof
US8908387B2 (en) * 2011-10-31 2014-12-09 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
DE102012112327A1 (en) * 2011-12-15 2013-06-20 Infineon Technologies Ag Packaging integrated circuit by fabricating package module from successive build-up layers having circuit interconnections, and forming cavity on top-side of package module
KR20130080294A (en) * 2012-01-04 2013-07-12 삼성전기주식회사 Printed circuit board having embedded capacitor and method for manufacturing the same
US9439289B2 (en) * 2012-01-12 2016-09-06 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9215805B2 (en) * 2012-04-27 2015-12-15 Ibiden Co., Ltd. Wiring board with built-in electronic component and method for manufacturing the same
US9113574B2 (en) * 2012-10-25 2015-08-18 Ibiden Co., Ltd. Wiring board with built-in electronic component and method for manufacturing the same
KR101420526B1 (en) * 2012-11-29 2014-07-17 삼성전기주식회사 Substrate embedding electronic component and manufacturing mehtod thereof
JP2014130962A (en) * 2012-12-28 2014-07-10 Ibiden Co Ltd Formation method for cavity, formation device for cavity, program, manufacturing method for wiring board, and wiring board
US9202782B2 (en) * 2013-01-07 2015-12-01 Intel Corporation Embedded package in PCB build up
JP6200178B2 (en) * 2013-03-28 2017-09-20 新光電気工業株式会社 Electronic component built-in substrate and manufacturing method thereof
KR102186148B1 (en) * 2014-02-28 2020-12-03 삼성전기주식회사 Embedded board and method of manufacturing the same
JP6682741B2 (en) * 2014-06-23 2020-04-15 サムソン エレクトロ−メカニックス カンパニーリミテッド． Circuit board and circuit board assembly
KR20160004157A (en) * 2014-07-02 2016-01-12 삼성전기주식회사 Chip embedded substrate and method of manufacturing the same
TWI624018B (en) * 2014-08-04 2018-05-11 恆勁科技股份有限公司 Package structure and its manufacturing method
US20160055976A1 (en) * 2014-08-25 2016-02-25 Qualcomm Incorporated Package substrates including embedded capacitors
TWI572267B (en) * 2014-09-29 2017-02-21 旭德科技股份有限公司 Multi-layer circuit board with cavity and method of manufacturing the same
US9337135B2 (en) * 2014-10-08 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pop joint through interposer
US9198296B1 (en) * 2015-01-06 2015-11-24 Kinsus Interconnect Technology Corp. Double sided board with buried element and method for manufacturing the same
US9627311B2 (en) * 2015-01-22 2017-04-18 Mediatek Inc. Chip package, package substrate and manufacturing method thereof
JP2016207940A (en) * 2015-04-27 2016-12-08 イビデン株式会社 Electronic component built-in wiring board and manufacturing method thereof
JP6752553B2 (en) * 2015-04-28 2020-09-09 新光電気工業株式会社 Wiring board
US9837484B2 (en) * 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
KR102425753B1 (en) * 2015-06-01 2022-07-28 삼성전기주식회사 Printed circuit board, method for manufacturing the same and semiconductor package having the thereof
JP2017050315A (en) * 2015-08-31 2017-03-09 イビデン株式会社 Printed wiring board and printed wiring board manufacturing method
US9743526B1 (en) * 2016-02-10 2017-08-22 International Business Machines Corporation Wiring board with stacked embedded capacitors and method of making
KR101942744B1 (en) * 2017-11-03 2019-01-28 삼성전기 주식회사 Fan-out semiconductor package
US10347586B2 (en) * 2017-11-30 2019-07-09 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package

Patent Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5491362A (en) * 1992-04-30 1996-02-13 Vlsi Technology, Inc. Package structure having accessible chip
US6214525B1 (en) * 1996-09-06 2001-04-10 International Business Machines Corp. Printed circuit board with circuitized cavity and methods of producing same
US20070155060A1 (en) * 2002-09-30 2007-07-05 Sony Corporation Method for manufacturing high-frequency module device
US20040183192A1 (en) * 2003-01-31 2004-09-23 Masashi Otsuka Semiconductor device assembled into a chip size package
US7341890B2 (en) * 2003-07-09 2008-03-11 Matsushita Industrial Co., Ltd. Circuit board with built-in electronic component and method for manufacturing the same
US20050230835A1 (en) * 2004-04-20 2005-10-20 Shinko Electric Industries Co., Ltd. Semiconductor device
US20070052086A1 (en) * 2004-05-17 2007-03-08 Shinko Electric Industries Co., Ltd. Electronic parts and method of manufacturing electronic parts packaging structure
US20060003495A1 (en) * 2004-06-30 2006-01-05 Masahiro Sunohara Method for fabricating an electronic component embedded substrate
US20060145331A1 (en) * 2004-12-30 2006-07-06 Samsung Electro-Mechanics Co., Ltd. Printed circuit board including embedded chips and method of fabricating the same using plating
US20060191711A1 (en) * 2005-02-28 2006-08-31 Samsung Electro-Mechanics Co., Ltd. Embedded chip printed circuit board and method of manufacturing the same
US20120293973A1 (en) * 2005-08-29 2012-11-22 Shinko Electric Industries Co., Ltd. Multilayered wiring board and method for fabricating the same
US20070069363A1 (en) * 2005-09-28 2007-03-29 Tdk Corporation Semiconductor IC-embedded substrate and method for manufacturing same
US20070141759A1 (en) * 2005-12-19 2007-06-21 Tdk Corporation Method for manufacturing ic-embedded substrate
US20080211086A1 (en) * 2006-12-22 2008-09-04 Tdk Corporation Mounting method of electronic components, manufacturing method of electronic component-embedded substrate, and electronic component-embedded substrate
US20080196931A1 (en) * 2007-02-15 2008-08-21 Samsung Electro-Mechanics Co., Ltd. Printed circuit board having embedded components and method for manufacturing thereof
US20090224378A1 (en) * 2008-03-04 2009-09-10 Advanced Semiconductor Engineering, Inc. Package structure with embedded die and method of fabricating the same
US20120199971A1 (en) * 2008-07-14 2012-08-09 Stats Chippac, Ltd. Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier
US20100019368A1 (en) * 2008-07-25 2010-01-28 Samsung Electronics Co., Ltd. Semiconductor chip package, stacked package comprising semiconductor chips and methods of fabricating chip and stacked packages
US20130140683A1 (en) * 2009-08-07 2013-06-06 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die
US20110100689A1 (en) * 2009-10-29 2011-05-05 Byun Jung-Soo Electronics component embedded pcb
US20110176246A1 (en) * 2010-01-19 2011-07-21 Samsung Electro-Mechanics Co., Ltd. Pcb strip and manufacturing method for electronic component embedded pcb
US20110216515A1 (en) * 2010-03-05 2011-09-08 Samsung Electro-Mechanics Co., Ltd. Electro device embedded printed circuit board and manufacturing method thereof
US20110214913A1 (en) * 2010-03-05 2011-09-08 Samsung Electro-Machanics Co., Ltd. Electro device embedded printed circuit board and manufacturng method thereof
US20110228464A1 (en) * 2010-03-17 2011-09-22 Guzek John S System-in-package using embedded-die coreless substrates, and processes of forming same
US8772924B2 (en) * 2010-04-06 2014-07-08 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US20110290546A1 (en) * 2010-05-28 2011-12-01 Samsung Electro-Mechanics Co., Ltd. Printed circuit board having electronic component and method for manufacturing thereof
US20120037411A1 (en) 2010-08-13 2012-02-16 Unimicron Technology Corporation Packaging substrate having embedded passive component and fabrication method thereof
US20120037404A1 (en) * 2010-08-13 2012-02-16 Unimicron Technology Corporation Packaging substrate having a passive element embedded therein and method of fabricating the same
US9627227B2 (en) * 2011-06-30 2017-04-18 Intel Corporation Bumpless build-up layer package warpage reduction
US20130285254A1 (en) * 2012-04-26 2013-10-31 Shinko Electric Industries Co., Ltd. Wiring substrate and method for manufacturing wiring subtrate
US20140070396A1 (en) * 2012-09-12 2014-03-13 Shinko Electric Industries Co., Ltd. Semiconductor package and manufacturing method
US20150014861A1 (en) * 2012-09-29 2015-01-15 Intel Corporation Embedded structures for package-on-package architecture
US20140097009A1 (en) * 2012-10-05 2014-04-10 Shinko Electric Industries Co., Ltd. Wiring substrate
US20140182897A1 (en) * 2012-12-31 2014-07-03 Samsung Electro-Mechanics Co., Ltd. Circuit board and method of manufacturing the same
US20140321084A1 (en) * 2013-04-26 2014-10-30 Samsung Electro-Mechanics Co., Ltd. Printed circuit board including electronic component embedded therein and method for manufacturing the same
US20150001708A1 (en) * 2013-06-28 2015-01-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package
US20150091176A1 (en) * 2013-10-01 2015-04-02 Infineon Technologies Austria Ag Electronic Component, Arrangement and Method
US20150171002A1 (en) * 2013-12-16 2015-06-18 Dong Ju Jeon Integrated circuit packaging system with embedded component and method of manufacture thereof
US20150245473A1 (en) * 2014-02-27 2015-08-27 Shinko Electric Industries Co., Ltd. Wiring Substrate, Semiconductor Device, and Method of Manufacturing Wiring Substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Inventor: Dong Ju Jeon et al., U.S. Appl. No. 14/556,992, filed Dec. 1, 2014 Title: Integrated Circuit Packaging System with Embedded Component and Method of Manufacture Thereof.

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190172902A1 (en) * 2015-05-27 2019-06-06 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
US10665662B2 (en) * 2015-05-27 2020-05-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
US11476202B2 (en) 2019-05-10 2022-10-18 Applied Materials, Inc. Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration
US11521935B2 (en) 2019-05-10 2022-12-06 Applied Materials, Inc. Package structure and fabrication methods
US11398433B2 (en) 2019-05-10 2022-07-26 Applied Materials, Inc. Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration
US11887934B2 (en) 2019-05-10 2024-01-30 Applied Materials, Inc. Package structure and fabrication methods
US11264331B2 (en) * 2019-05-10 2022-03-01 Applied Materials, Inc. Package structure and fabrication methods
US11417605B2 (en) 2019-05-10 2022-08-16 Applied Materials, Inc. Reconstituted substrate for radio frequency applications
US11715700B2 (en) 2019-05-10 2023-08-01 Applied Materials, Inc. Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration
US12051653B2 (en) 2019-05-10 2024-07-30 Applied Materials, Inc. Reconstituted substrate for radio frequency applications
US12354968B2 (en) 2019-05-10 2025-07-08 Applied Materials, Inc. Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration
US11362235B2 (en) 2019-05-10 2022-06-14 Applied Materials, Inc. Substrate structuring methods
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US12374611B2 (en) 2019-11-27 2025-07-29 Applied Materials, Inc. Package core assembly and fabrication methods
US12087679B2 (en) 2019-11-27 2024-09-10 Applied Materials, Inc. Package core assembly and fabrication methods
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11881447B2 (en) 2019-11-27 2024-01-23 Applied Materials, Inc. Package core assembly and fabrication methods
US11742330B2 (en) 2020-03-10 2023-08-29 Applied Materials, Inc. High connectivity device stacking
US12388049B2 (en) 2020-03-10 2025-08-12 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11927885B2 (en) 2020-04-15 2024-03-12 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US12358073B2 (en) 2020-07-14 2025-07-15 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US12518986B2 (en) 2020-07-24 2026-01-06 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US12374586B2 (en) 2020-11-20 2025-07-29 Applied Materials, Inc. Methods of TSV formation for advanced packaging
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US12183684B2 (en) 2021-10-26 2024-12-31 Applied Materials, Inc. Semiconductor device packaging methods

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