US9826186B2 - Imaging apparatus and imaging system - Google Patents

Imaging apparatus and imaging system Download PDF

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US9826186B2
US9826186B2 US15/208,380 US201615208380A US9826186B2 US 9826186 B2 US9826186 B2 US 9826186B2 US 201615208380 A US201615208380 A US 201615208380A US 9826186 B2 US9826186 B2 US 9826186B2
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signal
comparison
ramp
imaging apparatus
count
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US20170019621A1 (en
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Hirofumi Totsuka
Daisuke Yoshida
Shinya Nakano
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Canon Inc
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Canon Inc
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    • H04N5/378—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H04N5/3575—

Definitions

  • the present invention relates to an imaging apparatus and an imaging system.
  • An imaging apparatus which has AD converting units configured to AD convert signals output from pixels.
  • Japanese Patent Laid-Open No. 2010-103913 discloses a technology which performs a plurality of AD conversions on one signal output from a pixel by repetitively using ramp signals having an equal amplitude and an equal gradient from a ramp starting potential to a ramp end potential. The lengths of the periods in which the plurality of AD conversions are performed are equal to each other. According to Japanese Patent Laid-Open No. 2010-103913, the technology can provide an imaging apparatus having an improved noise characteristic.
  • An aspect of the present invention provides an imaging apparatus comprising pixels configured to output optical signals, an AD converting unit, a reference signal supplying unit configured to supply a ramp signal to the AD converting unit, and a counter configured to generate a count signal by counting clock signals, wherein the AD converting unit performs a first comparison being a comparison between a ramp signal and the optical signal, the ramp signal having a signal level changing in a first amplitude range at a first changing rate depending on elapsed time, in a case where the magnitude relationship between the ramp signal and the optical signal is changed in the first comparison, the AD converting unit generates a first digital signal by acquiring the count signal corresponding to a change from start of the first comparison to the change of the magnitude relationship between the ramp signal and the optical signal, and generates a second digital signal by performing a second comparison being a comparison between a ramp signal and the optical signal, the ramp signal having a signal level changing in a second amplitude range at a second changing
  • an imaging apparatus comprising pixels each configured to generate an optical signal by performing photoelectric conversion on light and output the optical signal, an AD converting unit, a reference signal supplying unit configured to supply a ramp signal to the AD converting unit, a counter configured to generate a count signal by counting clock signals, and an amplifying unit configured to output to the AD converting unit an amplified signal being a signal acquired by amplifying the optical signal by a predetermined amplification factor, wherein the AD converting unit performs a first comparison being a comparison between the ramp signal and a first amplified signal having undergone amplification by a first amplification factor in the amplifying unit, in a case where the magnitude relationship between the ramp signal and the first amplified signal is changed in the first comparison, the AD converting unit generates a first digital signal by acquiring the count signal corresponding to a period from start of the first comparison to the change of the magnitude relationship between the ramp signal and the first amplified signal and generates a second digital signal by performing a second comparison
  • FIG. 1A illustrates an example of a configuration of an imaging apparatus.
  • FIG. 1B illustrates an example of a configuration of a pixel.
  • FIG. 2A illustrates an example of operations of an imaging apparatus.
  • FIG. 2B illustrates an example of operations of an imaging apparatus.
  • FIG. 2C illustrates an example of operations of an imaging apparatus.
  • FIG. 3 illustrates an example of operations of an imaging apparatus.
  • FIG. 4 illustrates an example of a configuration of an imaging apparatus.
  • FIG. 5A illustrates an example of an operation of an imaging apparatus.
  • FIG. 5B illustrates an example of operations of an imaging apparatus.
  • FIG. 5C illustrates an example of operations of an imaging apparatus.
  • FIG. 6 illustrates an example of a configuration of an imaging system.
  • FIG. 7 illustrates an example of a configuration of an imaging apparatus.
  • FIG. 8 (comprising FIG. 8A and FIG. 8B ) illustrates an example of a configuration of an AD converting unit.
  • FIG. 9A illustrates an example of operations of an imaging apparatus.
  • FIG. 9B illustrates an example of operations of an imaging apparatus.
  • FIG. 9C illustrates an example of operations of an imaging apparatus.
  • FIG. 9D illustrates an example of operations of an imaging apparatus.
  • FIG. 10 illustrates an example of operations of an imaging apparatus.
  • ramp signals having an identical amplitude and an identical gradient from a ramp starting potential to a ramp end potential are repetitively used to perform a plurality of AD conversions irrespective of amplitudes of signals of pixels. This may require long time for performing the plurality of AD conversions in a case where the amplitude of the ramp signal is set so as to include all of the possible range of the amplitudes of signals of pixels, for example.
  • setting the amplitude of the ramp signal so as to only partially include the possible range of the amplitude of signals of pixels may reduce the range of signals of pixels on which AD conversions can be performed and may thus reduce the dynamic range.
  • the imaging apparatus disclosed in Japanese Patent Laid-Open No. 2010-103913 may not properly consider the balance between the length of the period required for the AD conversions and the width of the dynamic range.
  • amplitude represents the amount of change from a reference signal value.
  • a signal A may have an electric potential (such as 0 V) numerically smaller than the electric potential (such as 1 V) of a signal B.
  • a reference signal level such as 3 V for electric potentials of the signal A and the signal B is larger than a medium electric potential between those of the signal A and the signal B, it is expressed as “the amplitude of the signal A is larger than the amplitude of the signal B”.
  • FIG. 1A illustrates an imaging apparatus according to a first exemplary embodiment.
  • a pixel array 101 has a plurality of pixels 100 arranged over a plurality of rows and a plurality of columns.
  • a vertical scanning circuit 102 is configured to perform vertical scanning which sequentially scans the plurality of pixels 100 in the pixel array 101 row by row.
  • the plurality of pixels 100 of each row is electrically connected to the vertical scanning circuit 102 through a control signal line.
  • the plurality of pixels 100 of each column is electrically connected to a vertical signal line 110 .
  • the vertical signal line 110 of each column is provided for each column of the plurality of pixels 100 .
  • the vertical signal line 110 is electrically connected to a comparator 104 provided externally to the pixel array 101 . Signals output from the pixels 100 through the vertical signal line 110 are input to the corresponding comparator 104 .
  • a signal to be input to the comparator 104 will be called a signal VIN, hereinafter.
  • Each of the comparators 104 is electrically connected to a selecting circuit 108 .
  • a ramp signal VRMP 1 and a ramp signal VRMP 2 are supplied from a reference signal supplying circuit 103 to the selecting circuit 108 .
  • the selecting circuit 108 selects one ramp signal of the ramp signal VRMP 1 and the ramp signal VRMP 2 and outputs the selected one to the corresponding comparator 104 .
  • a ramp signal to be output from the selecting circuit 108 to the corresponding comparator 104 will be called a ramp signal VRMPI.
  • Each of the ramp signal VRMP 1 and the ramp signal VRMP 2 is a signal having a signal level that changes depending on elapsed time at a predetermined changing rate. According to this exemplary embodiment, the changing rate of signal level of the ramp signal VRMP 1 is 1 ⁇ 4 times of the changing rate of signal level of the ramp signal VRMP 2 .
  • the reference signal supplying circuit 103 is a reference signal supplying unit configured to supply the ramp signal VRMP 1 and the ramp signal VRMP 2 .
  • the comparator 104 of each column is electrically connected to one counter 105 .
  • Clock signals are input from a timing generator, not illustrated, to the counter 105 .
  • the counter 105 is configured to generate a count signal as a result of counting of the clock signals.
  • the counter 105 of each column is electrically connected to one memory 106 .
  • the memory 106 of each column holds a count signal generated by the corresponding counter 105 .
  • One analog-to-digital (AD) converting unit 200 has one comparator 104 and one counter 105 , and one memory 106 .
  • the one AD converting unit 200 is provided for each column of the plurality of pixels 100 .
  • a horizontal scanning circuit 107 performs horizontal scanning which sequentially scans the memories 106 of columns. Thus, count signals (image signals) held in the memories 106 of the columns are output.
  • FIG. 1B illustrates a configuration of one of the pixels 100 .
  • the pixel 100 has a photodiode PD, a reset transistor M 1 , a transfer transistor M 2 , a amplify transistor M 3 , and a select transistor M 4 .
  • the reset transistor M 1 has a control node which receives a signal ⁇ R input from the vertical scanning circuit 102 .
  • the transfer transistor M 2 has a control node which receives a signal ⁇ T input from the vertical scanning circuit 102 .
  • the select transistor M 4 has an input node which receives a signal ⁇ SEL input from the vertical scanning circuit 102 .
  • Power supply voltage VDD is input to one main node of the reset transistor M 1 and one main node of the amplify transistor M 3 .
  • the other main node of the reset transistor M 1 , one main node of the transfer transistor M 2 and the control node of the amplify transistor M 3 are electrically connected to a node FD.
  • the other main node of the transfer transistor M 2 is electrically connected to the photodiode PD.
  • the other main node of the amplify transistor M 3 is electrically connected to one main node of the select transistor M 4 .
  • the other main node of the select transistor M 4 is electrically connected to the vertical signal line 110 .
  • the amplify transistor M 3 , a current source, not illustrated, electrically connected to the vertical signal line 110 , and the power supply voltage VDD configure a source follower circuit.
  • FIGS. 2A to 2C illustrate operations of the imaging apparatus illustrated in FIG. 1A .
  • FIGS. 2A to 2C illustrate operations of the pixels 100 of one row of the pixels 100 of the plurality of rows illustrated in FIG. 1A .
  • the vertical scanning circuit 102 outputs a signal ⁇ SEL having High level (hereinafter, called Hi) as its signal level to the select transistors M 4 of the pixels 100 of one row from a time T 0 to a time T 11 .
  • Hi High level
  • Signals ⁇ R and ⁇ T illustrated in FIGS. 2A to 2C correspond to the signals illustrated in FIG. 1B .
  • the ramp signals VRMPI illustrated in FIGS. 2A to 2C are ramp signals output from the selecting circuit 108 to the comparator 104 as described above.
  • the vertical scanning circuit 102 outputs the signals ⁇ R and ⁇ T having a signal level of a tow level (hereinafter, called Lo).
  • Lo a tow level
  • the vertical scanning circuit 102 changes the signal ⁇ R to have Hi.
  • reset transistor M 1 is changed to have an ON state. Because of the reset transistor M 1 changed to the ON state, the node FD is reset to a signal level based on the power supply voltage VDD.
  • the vertical scanning circuit 102 changes the signal ⁇ R to Lo.
  • the reset transistor M 1 is turned off.
  • the reset of the node FD is cancelled.
  • the amplify transistor M 3 outputs a signal based on the signal level of the node FD in which the reset has been cancelled. This signal will be called an N signal.
  • the reference signal supplying circuit 103 starts change of the signal level of the ramp signal VRMP 1 depending on elapsed time.
  • the reference signal supplying circuit 103 does not change the signal level of the ramp signal VRMP 2 .
  • the selecting circuits 108 of all columns output the ramp signals VRMP 1 as ramp signals VRMPI to the respective comparators 104 .
  • Each of the comparators 104 compares the ramp signal VRMP 1 and the N signal output to the vertical signal line 110 .
  • the comparator 104 outputs to the counter 105 a comparison result signal representing a result of a comparison between signal levels of signals output to the ramp signal VRMP 1 and the vertical signal line 110 .
  • the counter 105 starts counting of clock signals at the time T 2 .
  • the signal values of the count signals generated by the counter 105 increases depending on elapsed time.
  • the magnitude relationship between the signal levels of the ramp signal VRMP 1 and the N signal is changed.
  • the signal value of a comparison result signal output by the comparator 104 changes.
  • the counter 105 holds the count signal at the time point when the signal value of the comparison result signal has changed.
  • the count signal will be called a first N digital signal.
  • the reference signal supplying circuit 103 finishes changing of the signal level of the ramp signal VRMP 1 depending on elapsed time and resets the ramp signal VRMP 1 to have an initial value.
  • the period from the time T 2 to the time T 3 will be called a first N conversion period N 1 .
  • the first N conversion period N 1 is an analog-to-digital (AD) conversion period in which the first N digital signal is generated.
  • the reference signal supplying circuit 103 restarts changing the signal level of the ramp signal VRMP 1 depending on elapsed time. Also at this time point, the reference signal supplying circuit 103 does not change the signal level of the ramp signal VRMP 2 .
  • the selecting circuits 108 of all columns output the ramp signals VRMP 1 as ramp signals VRMPI to the respective comparators 104 .
  • the counter 105 starts counting clock signals from the signal value of the first N digital signal that it holds.
  • the counter 105 holds the count signal at the time point when the signal value of the comparison result signal has changed.
  • the count signal will be called a second N digital signal.
  • the period from the time T 4 to the time T 5 will be called a second N conversion period N 2 .
  • the second N conversion period N 2 is analog-to-digital (AD) conversion period in which the second N digital signal is generated.
  • the second N conversion period N 2 has an equal length to that of the first N conversion period N 1 .
  • the comparator 104 performs a fourth comparison which compares a ramp signal changing the signal level at a first changing rate depending elapsed time within a first amplitude range and a noise signal.
  • First to third comparisons compare the ramp signal and an optical signal, which will be described below.
  • a second N digital signal generated as a result of a plurality of fourth comparisons is a fourth digital signal.
  • First to third digital signals are digital signals generated as a result of comparisons between the ramp signal and an optical signal, which will be described below.
  • the memory 106 holds the second N digital signal held in the counter 105 .
  • the counter 105 resets the signal value of the count signal to an initial value.
  • the horizontal scanning circuit 107 performs horizontal scanning to cause the memories 106 of the columns to sequentially output the second N digital signals held in the memories 106 of the columns.
  • the vertical scanning circuit 102 changes the signal ⁇ T to Hi. This turns on the transfer transistor M 2 . Thus, transfer of electric carriers accumulated in the photodiode PD to the node FD through the transfer transistor M 2 is started.
  • the vertical scanning circuit 102 changes the signal ⁇ T to Lo. This turns off the transfer transistor M 2 . Thus, the transfer of electric carriers from the photodiode PD to the node FD ends.
  • the amplify transistor M 3 outputs a signal based on the signal level of the node FD to the vertical signal line 110 through the select transistor M 4 .
  • the signal output from the amplify transistor M 3 to the vertical signal line 110 will be called an S signal.
  • the S signal is an optical signal generated and output by a pixel through a photoelectric conversion.
  • the reference signal supplying circuit 103 starts change of the signal level of the ramp signal VRMP 1 depending on elapsed time.
  • the reference signal supplying circuit 103 does not change the signal level of the ramp signal VRMP 2 .
  • the selecting circuits 108 of all columns output the ramp signals VRMP 1 as ramp signals VRMPI to the respective comparators 104 .
  • the comparator 104 compares between signal levels of the S signal output to the vertical signal line 110 and the ramp signal VRMP 1 .
  • the counter 105 starts counting clock signals from the initial value.
  • FIG. 2B illustrates a case where the S signal has an amplitude equal to or smaller than the amplitude of the ramp signal VRMP 1 at the time T 9 .
  • the times T 8 , T 9 , T 10 , and T 11 in FIG. 2B correspond to the times illustrated in FIG. 2A .
  • the magnitude relationship between signal levels of the ramp signal VRMP 1 and the S signal may be changed at a time T 8 A, for example.
  • the change of the magnitude relationship changes the signal value of the comparison result signal.
  • the counter 105 holds the count signal at a time point when the signal value of the comparison result signal has changed.
  • the count signal will be called a first S digital signal.
  • the change of the signal value of the comparison result signal at the time T 8 A is also output to the selecting circuit 108 .
  • the selecting circuit 108 in response to the change of the signal value of the comparison result signal changes the ramp signal VRMPI to be supplied to the comparator 104 at and after the time T 10 to the ramp signal VRMP 1 .
  • a first changing rate depending on elapsed time being a changing rate of the ramp signal VRMPI to be used for AD conversion in a first S conversion period S 1 is equal to a second changing rate depending on elapsed time being a changing rate of the ramp signal VRMPI to be used for AD conversion in a second S conversion period S 2 .
  • the reference signal supplying circuit 103 finishes changing of the signal level of the ramp signal VRMP 1 depending on elapsed time and resets the ramp signal VRMP 1 to have an initial value.
  • the period from the time T 8 to the time T 9 is the first S conversion period S 1 .
  • the first S conversion period S 1 is a first period in which an optical signal and a ramp signal having the first changing rate depending on elapsed time are compared.
  • the comparator 104 performs a first comparison which compares a ramp signal changing the signal level at a first changing rate depending on elapsed time within a first amplitude range and an optical signal.
  • the first S digital signal generated as a result of the first comparison is a first digital signal.
  • the selecting circuit 108 selects one of the ramp signal VRMP 1 and ramp signal VRMP 2 as the ramp signal VRMPI. As described above, in the operations in FIG. 2B , the selecting circuit 108 selects the ramp signal VRMP 1 as the ramp signal VRMPI in response to the change of the signal value of the comparison result signal at the time T 8 A.
  • the reference signal supplying circuit 103 restarts the changing of the signal level of the ramp signal VRMP 1 depending on elapsed time.
  • the changing rate of the signal level of the ramp signal VRMP 1 per unit time is equal to the changing rate of the signal level of the ramp signal VRMP 1 per unit time in the period from the time T 8 to the time T 9 .
  • the changing rate depending on elapsed time of the signal level of a ramp signal changing its potential in a period from the time T 10 to a time T 11 is also equal to the first changing rate depending on elapsed time.
  • the counter 105 starts counting clock signals from the signal value of the first S digital signal that it holds.
  • the counter 105 holds the count signal at the time point when the signal value of the comparison result signal has changed. This count signal will be called a second S digital signal.
  • the period from the time T 10 to the time T 11 is the second S conversion period S 2 .
  • the second S conversion period S 2 has a length equal to that of the first S conversion period S 1 .
  • the second S conversion period S 2 is a second period in which an optical signal and a ramp signal having the first changing rate depending on elapsed time are compared.
  • the second S conversion period S 2 is a period having a length equal to that of the first S conversion period S 1 .
  • the ramp signal in the second period has a maximum amplitude (of the signal level at the time T 11 ) equal to a maximum amplitude (of the signal level at the time T 9 ) of the ramp signal in the first period.
  • the comparator 104 performs a second comparison which compares a ramp signal changing the signal level at a second changing rate depending on elapsed time within a second amplitude range and an optical signal.
  • the second S digital signal generated as a result of the second comparison is a second digital signal.
  • the memory 106 holds the second S digital signal held in the counter 105 .
  • the counter 105 resets the signal value of the count signal to an initial value.
  • the horizontal scanning circuit 107 performs horizontal scanning to cause the memories 106 of the columns to sequentially output the second S digital signals held in the memories 106 of the columns.
  • FIG. 2C illustrates a case where the S signal has an amplitude larger than the amplitude of the ramp signal VRMP 1 at the time T 9 .
  • the times T 8 , T 9 , T 10 , and T 11 correspond to the respective times illustrated in FIG. 2A .
  • the signal value of the comparison result signal does not change.
  • the counter 105 finishes the counting of the clock signal at the time T 9 and resets the signal value of the count signal to an initial value.
  • the selecting circuit 108 in response to no change of the signal value of the comparison result signal in the period from the time T 8 to the time T 9 selects the ramp signal VRMP 2 as a ramp signal VRMPI to be supplied to the comparator 104 at and subsequent to a time T 10 .
  • a third changing rate depending on elapsed time being a changing rate of the ramp signal VRMPI to be used for AD conversion of the second S conversion period S 2 is larger than the first changing rate being a changing rate of signal level of the ramp signal VRMPI used for AD conversion of the first S conversion period S 1 .
  • the reference signal supplying circuit 103 restarts the changing of the signal level of the ramp signal VRMP depending on elapsed time.
  • the counter 105 starts counting clock signals from the initial value. In the case illustrated in FIG. 20 , eight times count up (3 bit shift) of the case illustrated in FIG. 2B is performed.
  • One reason for performing the 8 ⁇ count up is that the changing rate depending on elapsed time of the ramp signal VRMP 2 is four times the changing rate depending on elapsed time of the ramp signal VRMP 1 .
  • the second S digital signal generated by the operations in FIG. 2B is a signal acquired by adding results of two AD conversions while the digital signal generated by the operations in FIG. 2C is acquired by performing the operation of one AD conversion.
  • the counter 105 holds the count signal at the time point when the signal value of the comparison result signal has changed.
  • the count signal will be called a third S digital signal.
  • the third S digital signal is a signal acquired by counting the period from the time T 10 to the time T 10 B only while the second S digital signal is a signal acquired by adding and counting the period from the time T 8 to the time T 8 A and the period from the time T 10 to the time T 10 A.
  • the third S digital signal is a digital signal generated by one comparison operation performed by the comparator 104 .
  • the second S digital signal is a digital signal acquired by adding digital signals generated by a plurality of comparison operations performed by the comparator 104 .
  • the counter 105 is an adding unit configured to generate a digital signal by adding digital signals generated by a plurality of AD conversions.
  • the comparator 104 performs a third comparison which is a comparison between a ramp signal changing the signal level at a third changing rate depending on elapsed time within a third amplitude range and an optical signal.
  • the third S digital signal generated as a result of the third comparison is a third digital signal.
  • the memory 106 holds the third S digital signal held in the counter 105 .
  • the counter 105 then resets the signal value of the count signal to an initial value.
  • the second S conversion period S 2 has an equal length to that of the first S conversion period S 1 . Because the changing rate depending on elapsed time of the ramp signal VRMP 2 is four times the changing rate depending on elapsed time of the ramp signal VRMP 1 , the amplitude of the ramp signal VRMP 2 at the time T 11 is four times the amplitude of the ramp signal VRMP 1 at the same time. Therefore, the amplitude in which the signal level of the ramp signal VRMP 2 changes is larger than the amplitude in which the signal level of the ramp signal VRMP 1 changes.
  • the amplitude range in which the signal level of the ramp signal VRMP changes is equal to the AD conversion of the first N conversion period N 1 and the AD conversion of the second N conversion period N 2 .
  • the amplitude range in which the signal level of the ramp signal VAMP of an AD conversion in the first S conversion period S 1 changes is a first amplitude range in both of the operations in FIGS. 2B and 2C .
  • the amplitude range in which the signal level of the ramp signal VRMP of AD conversion in the second S conversion period S 2 is a second amplitude range in the operations in FIG. 23 and is a third amplitude range in the operations in FIG. 2C .
  • the first amplitude range and the second amplitude range are equal to each other.
  • the third amplitude range is larger than the first amplitude range and the second amplitude range.
  • the second S digital signal is a signal based on a result of addition of digital signals generated by performing a plurality of AD conversions on an S signal. Because of the addition of digital signals generated by performing a plurality of AD conversions, the second S digital signal can have reduced random noise compared with a digital signal acquired by performing one AD conversion on an S signal. Therefore, the imaging apparatus of this exemplary embodiment can advantageously output digital signals having reduced random noise.
  • the imaging apparatus of this exemplary embodiment defines one digital signal based on an S signal for a high luminance object in which random noise is not noticeable and generation of a digital signal based on an S signal is performed twice for a low-luminance object in which random noise is noticeable.
  • ramp signals having an identical changing rate depending on elapsed time is used a plurality of number of times to perform a plurality of AD conversions.
  • the ramp signals to be used here should have an amplitude including all possible amplitudes of an S signal so that AD conversions can be performed on the S signal.
  • the ramp signal VRMP 2 described in conjunction with the operations in FIG. 2C of this exemplary embodiment includes all possible amplitudes of an S signal.
  • the changing rate depending on elapsed time of the ramp signal may be required to be lowered to increase the resolution of the AD conversions.
  • a ramp signal having a small changing rate depending on elapsed time such as the ramp signal VRMP 1 according to this exemplary embodiment, may be used.
  • the AD conversion period is increased.
  • the ramp signal VRMP 1 according to this exemplary embodiment changes the signal level to include all possible amplitude ranges, of the S signal, a period four times the first S conversion period S 1 may be required. Therefore, in Japanese Patent Laid-Open No. 2010-103913, performing a plurality of AD conversions for reducing random noise with high accuracy increases the AD conversion period.
  • the number of AD conversions is changed in accordance with the amplitude of an S signal.
  • the amplitude of the S signal is larger than a predetermined threshold, the changing rate depending on elapsed time of the ramp signal is increased to perform the AD conversions.
  • the imaging apparatus of this exemplary embodiment allows reduction of random noise and can increase the speed of AD conversions.
  • the maximum amplitude of the ramp signal VRMP 1 of a first S conversion S 1 may be adjusted in order to reduce the period required for performing a plurality of AD conversions and at the same time to generate a digital signal having reduced random noise of the S signal. More specifically, the maximum amplitude of the ramp signal VRMP 1 in the first S conversion period S 1 may be 1 ⁇ 2 N being a maximum amplitude of the ramp signal VRMP 2 in the second S conversion period S 2 . Furthermore, the maximum amplitude of the ramp signal VRMP 1 in the first S conversion period S 1 may be equal to or lower than 1 ⁇ 2 and equal to or higher than 1 ⁇ 8 of the maximum amplitude of the ramp signal VRMP 2 of the second S conversion period S 2 .
  • a second digital N signal output from the imaging apparatus is a signal acquired by averaging fluctuations (random noise) contained in an N signal.
  • the AD converting unit 200 can acquire a signal as a result of reduction of random noise contained in the N signal.
  • a signal processing unit not illustrated, provided externally to the imaging apparatus performs a correlated double sampling (CDS) process for acquiring a difference between the second N digital signal and the second S digital signal.
  • the signal processing unit uses the difference to generate an image.
  • the signal processing unit may be implemented by a output signal processing unit 155 according to a third exemplary embodiment, which will be described below.
  • the signal processing unit uses the difference to generate an image.
  • the process may be performed within the imaging apparatus.
  • the imaging apparatus outputs a difference between the second S digital signal or third S digital signal and the second N digital signal to a signal processing unit provided externally to the imaging apparatus.
  • the signal processing unit may perform a CDS process for acquiring a signal of the difference output from the imaging apparatus and then generate an image.
  • the operations in FIG. 2C may include a plurality of AD conversions using the ramp signal VRMP 2 .
  • the counter 105 operates so as to add count signals of a plurality of AD conversions using the ramp signal VRMP 2 .
  • digital signals containing random noise that can be reduced can be generated.
  • the imaging apparatus of this exemplary embodiment performs AD conversions in the first S conversion period S 1 , including setting the changing rate depending on elapsed time of the ramp signal VRMPI for the AD conversions in the second S conversion period S 2 and AD conversions with a smaller amplitude of S signals.
  • the AD conversions in the first S conversion period S 1 may be performed by comparing a signal set to a predetermined threshold voltage and the S signal and setting the changing rate depending on elapsed time of the ramp signal VRMP 1 for AD conversions in the second S conversion period S 2 based on the comparison result, without operating the counter 105 .
  • the imaging apparatus of this exemplary embodiment can also use the AD conversion in a case where the S signals have a smaller amplitude, digital signals in which random noise can be reduced can be acquired.
  • the imaging apparatus of this exemplary embodiment performs a predetermined number of AD conversions when S signals have a larger amplitude than a threshold and, when the S signals have a smaller amplitude than a threshold, performs more AD conversions than those performed when the amplitude of the S signals is smaller than the threshold.
  • the imaging apparatus of this exemplary embodiment can properly balance the lengths of the periods required for AD conversions and the width of the dynamic range.
  • the ramp signals VRMP 1 in the first S conversion period S 1 and the second S conversion period S 2 have an equal changing rate depending on elapsed time.
  • the changing rate depending on elapsed time of the ramp signal VRMP 1 in the second S conversion period S 2 may be changed with respect to the ramp signal VRMP 1 in the first S conversion period S 1 .
  • the counting operation to be performed by the counter 105 may be changed to acquire an equal AD conversion gain between the AD conversions in the first S conversion period S 1 and the AD conversions in the second S conversion period S 2 .
  • the changing rate depending on elapsed time of the ramp signal VRMP 2 is four times the changing rate depending on elapsed time of the ramp signal VRMP 1 .
  • the changing rate depending on elapsed time of the ramp signal VRMP 2 may only be required to be larger than the changing rate depending on elapsed time of the ramp signal VRMP 1 .
  • the changing rate depending on elapsed time of the ramp signal VRMP 2 may be 2 N times the changing rate depending on elapsed time of the ramp signal VRMP 1 . This is for facilitating to acquire equal AD conversion gains of digital signals generated by operations of AD conversions performed both in the first S conversion period S 1 and the second S conversion period S 2 . More specifically, it is because the operation for generating count signals by the counter 105 can be performed by bit-shifting to a higher level by N bits.
  • the imaging apparatus of this exemplary embodiment is not limited to those examples as described above but may be changed in various manners. Variation examples will be described below.
  • a CDS process is performed in a following stage of the memory 106 .
  • the counter 105 may perform the CDS process. More specifically, after the second N conversion period N 2 , the counter 105 acquires a complement of 2 of the second N digital signal. The complement is held in the counter 105 . The counter 105 starts counting clock signals in the first S conversion period S 1 from the held complement as the initial value. In this case, a result of the CDS process may be output by horizontal scanning after the second S conversion period S 2 without requiring the horizontal scanning after the second N conversion period N 2 .
  • the counter 105 down-counts and holds a negative counted value and then starts up-counting from the initial value of the counter 105 in the first S conversion period S 1 .
  • AD conversion periods may be provided for an N signal. Because the number of times of generation of digital N signals based on an N signal is increased, a digital signal based on an N signal having reduced random noise can be generated.
  • the ramp signal VRMPI to be used in the second N conversion period N 2 may be the ramp signal VRMP 2 .
  • the counter 105 resets the signal value of the count signal to the initial value.
  • the AD conversions performed in the second N conversion period N 2 can result in a second N digital signal.
  • the memory 106 further holds the second N digital signal.
  • the memory 106 outputs the first N digital signal and the second N digital signal.
  • the signal processing unit acquires a difference between the second S digital signal generated by the operations in FIG. 2 B and the doubled first N digital signal.
  • the second S digital signal is generated by adding, in the counter 105 , a count signal resulting from an AD conversion in the second S conversion period S 2 to the first S digital signal.
  • the counter 105 resets the signal value of the count signal to the initial value.
  • the AD conversions performed in the second S conversion period S 2 can result in a second S digital signal, and the memory 106 further holds the second S digital signal.
  • the memory 106 outputs the first S digital signal and the second S digital signal.
  • a signal processing unit may add the first S digital signal and the second S digital signal.
  • a second N digital signal may be generated without adding a count signal to the first N digital signal in the counter 105 .
  • the signal processing unit may add the first N digital signal and the second N digital signal.
  • the signal processing unit is an adding unit configured to add digital signals generated by a plurality of AD conversions.
  • each of the plurality of AD converting units 200 has the counter 105 .
  • a counter may be included which supplies a common count signal to the memories 106 in the plurality of AD converting units 200 .
  • the counter does not perform the up-count operation for generation of a count signal, which is performed in the AD conversions in the second S conversion period S 2 in FIG. 2C according to this exemplary embodiment.
  • the memories 106 of each column may bit shift a count signal supplied from the counter to an upper level and hold the result.
  • AD conversion gains may be added in the AD conversions in the second S conversion periods S 2 in FIGS. 2B and 2C .
  • the bit shift may not be necessarily performed in the memory 106 .
  • the signal processing unit which receives input of digital signals output by the memories 106 through horizontal scanning may perform the bit shift.
  • an amplifier may be provided in an electrical path between the vertical signal line 110 and the comparator 104 .
  • the amplifier outputs to the comparator 104 signals acquired by amplifying an N signal and an S signal output to the vertical signal line 110 .
  • the first N digital signal and the second N digital signal are signals based on a signal acquired by amplifying an N signal by the amplifier.
  • the first S digital signal, the second S digital signal, and the third S digital signal are signals based on a signal acquired by amplifying an S signal by the amplifier.
  • a correlated double sampling (CDS) circuit may be provided in an electrical path between the vertical signal line 110 and the comparator 104 .
  • the CDS circuit outputs a signal acquired by subtracting an N signal from an S signal output to the vertical signal line 110 .
  • the first N digital signal and the second N digital signal dominantly contain noise and offset caused by the comparator 104 .
  • the ramp signal VRMP 1 and the ramp signal VRMP 2 are signals having signal levels changing in a slopewise manner, they may be signals having signal levels changing in a stepwise manner.
  • the signals having signal levels changing in a stepwise manner are also ramp signals having signal levels changing depending on elapsed time.
  • An imaging apparatus according to a second exemplary embodiment will be described with focus on differences from the first exemplary embodiment.
  • the imaging apparatus changes the changing rate depending on elapsed time of a ramp signal VRMP 1 to be input to the comparator 104 in accordance with the amplitude of an S signal.
  • a signal acquired by amplifying an S signal is input to the comparator 104 .
  • the imaging apparatus of this exemplary embodiment is different from the imaging apparatus of the first exemplary embodiment in that the amplification factor of an S signal is changed in accordance with the amplitude of the S signal.
  • FIG. 4 illustrates a configuration of an imaging apparatus according to this exemplary embodiment.
  • Like numbers refer to like parts having like functions in FIG. 1A and FIG. 4 .
  • the reference signal supplying circuit 113 outputs a ramp signal VRMP to the comparators 104 of each column.
  • An amplifying circuit 109 outputs to the corresponding comparator 104 signals acquired by amplifying an N signal and an S signal output from the corresponding pixel 100 to the vertical signal line 110 .
  • the signal VIN of this exemplary embodiment is representative of a signal to be output from the amplifying circuit 109 to the comparator 104 .
  • the amplifying circuit 109 of this exemplary embodiment has amplification factors of 1 ⁇ and 4 ⁇ .
  • An amplification factor of 4 ⁇ is called a first amplification factor
  • an amplification factor of 1 ⁇ is called a second amplification factor.
  • An amplification factor of 1 ⁇ also comes under an amplification category herein.
  • the first amplification factor is preferably 2 N times the second amplification factor.
  • a signal acquired by amplifying an N signal to be output by the amplifying circuit 109 will be called amplified N signal.
  • a signal acquired by amplifying an S signal to be output by the amplifying circuit 109 will be called amplified S signal.
  • the amplified S signal is an amplified signal generated by amplifying an optical signal by the amplifying circuit 109 being an amplifying unit.
  • a first amplified signal is an amplified S signal acquired by amplifying an S signal with an amplification factor of 4 ⁇ being the first amplification factor.
  • a second amplified signal is an amplified S signal acquired by amplifying an S signal with an amplification factor of 1 ⁇ being the second amplification factor.
  • a third amplified signal is an amplified N signal acquired by amplifying an N signal with an amplification factor of 4 ⁇ being the first amplification factor.
  • FIG. 5A illustrates operations of the imaging apparatus illustrated in FIG. 4 .
  • All of ramp signals VRMP to be used in the first N conversion period N 1 , the, second N conversion period N 2 , the first S conversion period S 1 , and the second S conversion period S 2 have an equal changing rate.
  • the amplitude range in which the signal level of the ramp signal VRMP changes is equal to the AD conversion of the first N conversion period N 1 and the AD conversion of the second N conversion period N 2 .
  • the amplitude range in which the signal level of the ramp signal VRMP changes is equal to the AD conversion of the first S conversion period S 1 and the AD conversion of the second S conversion period S 2 .
  • the amplitude range in which the signal level of a ramp signal VRMP changes with the AD conversions in the first S conversion period S 1 and the AD conversions in the second S conversion period S 2 is larger than the amplitude range with the AD conversions in the first N conversion period N 1 and the AD conversion of the second N conversion period N 2 .
  • FIG. 5B illustrates a case where the amplitude of an S signal is equal to or smaller than the amplitude of a ramp signal VRMP at a time T 9 .
  • the amplifying circuit 109 amplifies an S signal with an amplification factor of 4 ⁇ .
  • a change of the signal value of a comparison result signal at a time T 8 A is output to the counter 105 and the amplifying circuit 109 .
  • the amplifying circuit 109 in response to a change of the signal value of the comparison result signal keeps an amplification factor of 4 ⁇ for an S signal in the second S conversion period S 2 .
  • the operations in the second S conversion period S 2 are the same as the operations described with reference to FIG. 2B .
  • the second S digital signal is generated.
  • FIG. 5C illustrates a case where the amplitude of an S signal is larger than the amplitude of the ramp signal VRMP at the time T 9 .
  • the amplifying circuit 109 amplifies an S signal by an amplification factor of 4 ⁇ .
  • the amplifying circuit 109 changes the amplification factor for an S signal in the second S conversion period S 2 to 1 ⁇ .
  • the other operations are the same as the operations described with reference to FIG. 2C .
  • the third S digital signal is generated.
  • an amplitude range in which the signal level of a ramp signal VRMP changes is required so as to include all of the amplitude range of the amplified S signal acquired by amplifying an S signal by 4.
  • the imaging apparatus changes the amplification factor of the amplifying circuit 109 in the second S conversion period S 2 based on a result of AD conversions in the first S conversion period S 1 .
  • This configuration can reduce the amplitude range in which the signal level of the ramp signal VRMP changes.
  • the period required for a plurality of AD conversions can be reduced, compared with the configuration in Japanese Patent Laid-Open No. 2010-103913.
  • a second S digital signal being a signal from which random noise can be reduced can be acquired.
  • FIG. 7 illustrates a configuration of an imaging apparatus according to this exemplary embodiment.
  • the imaging apparatus includes a plurality of AD converting units 2000 .
  • Each of the AD converting units 2000 has a selecting circuit 108 , a comparator 104 , a second selecting circuit 120 , a first memory group 121 , a second memory group 122 , and a decision signal memory 128 .
  • the second selecting circuit 120 outputs a control signal VCOMP being a comparison result signal to one of the first memory group 121 , the second memory group 122 , and the decision signal memory 128 .
  • a counter 1050 outputs a count signal group 123 being count signals including a 11-bit Gray code signal, for example, through a plurality of signal lines.
  • the plurality of signal lines to which the count signal group 123 is output from the counter 1050 are commonly connected to the first memory group 121 and second memory group 122 of each column.
  • the value (count signal) exhibited by the count signal group 123 corresponds to an elapsed time from start of a change of a ramp signal VRMPI.
  • the first memory group 121 and the second memory group 122 hold a count signal corresponding to a time point when the signal value of the control signal VCOMP changes as a digital signal being a result of AD conversions.
  • the digital signals held in the first memory group 121 and the second memory group 122 are sequentially output by scanning from the horizontal scanning circuit 107 to a circuit in a following stage of the imaging apparatus through the output line 124 .
  • two of the first memory group 121 and second memory group 122 are provided in the AD converting unit 2000 as memory groups configured to hold digital signals resulting from AD conversions.
  • the decision signal memory 128 is configured to hold a control signal VCOMP.
  • FIGS. 8A and 8B illustrate a configuration of the memories included in one AD converting unit 2000 according to this exemplary embodiment.
  • FIG. 8A illustrates the first memory group 121 , the second memory group 122 , and the decision signal memory 128 .
  • FIG. 8B is a block diagram illustrating in more detail the configuration of memories included the first memory group 121 and the second memory group 122 .
  • the counter 1050 outputs a count signal group 123 including 12 count signals through 12 signal lines. It is assumed here that count signals 123 - 0 to 123 - 10 , and 123 - 3 M are transmitted through the respective signal lines.
  • the count signals 123 - 0 to 123 - 10 configure a 11-bit Gray code signal having the count signal 123 - 0 as a least significant bit and the count signal 123 - 10 as a most significant bit.
  • the count signals 123 - 0 , 123 - 1 , 123 - 2 , and 123 - 3 M configure a 4-bit Gray code signal having the count signal 123 - 0 as a least significant bit and the count signal 123 - 3 M as a most significant bit.
  • the first memory group 121 includes 5-bit memories 121 - 0 to 121 - 3 .
  • the memories 121 - 0 to 121 - 3 receive input of the count signals 123 - 0 , 123 - 1 , 123 - 2 , and 123 - 3 M.
  • the memory 121 -C receives input of the control signal VCOMP.
  • the second memory group 122 includes 11-bit memories 122 - 0 to 122 - 10 .
  • the memories 122 - 0 to 122 - 10 receive input of the count signals 123 - 0 to 123 - 10 .
  • FIG. 8B illustrates a configuration example of the first memory group 121 and the second memory group 122 .
  • the configuration of the memory 122 - 0 will be described as a typical example of those memories though the other memories can also have the same configuration.
  • the memory 122 - 0 of this exemplary embodiment is configured to hold two digital signals so that a video signal processing unit within the imaging apparatus or in a following stage of the imaging apparatus can perform a digital correlated double sampling (CDS) process.
  • the memory 122 - 0 has an N latch 200 -N configured to hold an AD conversion result of a signal at a reset level and an S latch 200 -S configured to hold an AD conversion result of an optical signal.
  • the number of memories included in the first memory group 121 is defined to a value higher than the highest value of difference values between AD conversion results of a plurality of AD conversions performed on one signal.
  • Those difference values are mainly due to a random noise component superimposed on a pixel signal VIN and a ramp signal VRMP and a random noise component generated by the comparator 104 .
  • a plurality of bit values which may change between two AD conversion results.
  • the bit width required for the first memory group 121 is equal to N+1 bits.
  • FIGS. 9A and 9B are timing chart illustrating operations of the whole imaging apparatus of this exemplary embodiment.
  • FIG. 9A illustrates a case where an object has a low luminance
  • FIG. 9B illustrates a case where an object has a high luminance.
  • FIG. 9C is a timing chart illustrating count signals.
  • FIG. 9D is a timing chart illustrating a variation example of count signals.
  • a control signal ⁇ R is changed to have a high level, which turns on a reset transistor M 1 .
  • the voltage of the floating diffusion FD is reset to a predetermined voltage level.
  • the second selecting circuit 120 selects the first memory group 121 as an output destination of the control signal VCOMP.
  • the voltage of the ramp signal VRMP output from the reference signal supplying circuit 103 starts to decrease.
  • the number of count signals included in the count signal group 123 output from the counter 1050 start to increase depending on elapsed time.
  • the control signal VCOMP output from the comparator 104 has a high level.
  • the first memory group 121 holds count signals included in the count signal group 123 at the time T 2 A as digital signals at the reset level after the AD conversion.
  • the first memory group 121 includes four memories 121 - 0 to 121 - 3 .
  • the digital signals to be held in the first memory group 121 in the period N 1 are lower 4 bits only from the least significant bit to the fourth bit of the count signals included in the count signal group 123 .
  • a second AD conversion is performed in a period N 2 .
  • the second selecting circuit 120 selects the second memory group 122 as an output destination for the control signal VCOMP.
  • the AD conversion is performed in the same manner as described above.
  • the second memory group 122 holds count signals included in the count signal group 123 at the time T 4 A as digital signals at the reset level after the AD conversion.
  • the second memory group 122 includes 11 memories 122 - 0 to 122 - 10 . In other words, because the second memory group 122 has a bit width of 11 bits, the digital signals to be held in the second memory group 122 in the period N 2 are from the least significant bit to the eleventh bits of the count signals included in the count signal group 123 .
  • the digital signals acquired by the AD conversions in the period N 1 and period N 2 are held in the N latch 200 -N at the corresponding memory. It is assumed that the gradient of the ramp signal VRMPI to be used for the second AD conversion in the period N 2 is equal to the gradient of the ramp signal VRMPI to be used for the first AD conversion in the period N 1 .
  • a control signal ⁇ T is changed to have a high level, which turns on the transfer transistor M 2 .
  • electric carriers generated from incident light in the photodiode PD are transferred to the floating diffusion FD.
  • the voltage of the pixel signal VIN decreases.
  • the voltage of the pixel signal VIN is changed to have a value according to the optical signal because of the transfer of electric carriers.
  • the selecting circuit 108 selects and outputs a VRMP 1 signal.
  • the selecting circuit 108 uses the control signal VCOMP at the time T 9 to select a ramp signal to be used for the AD conversion in the S conversion period S 2 .
  • digital signals acquired by performing the AD conversions are saved in an S latch 200 -S of the corresponding memory.
  • the decision signal memory holds the level of the control signal VCOMP output by the comparator 104 at the time T 9 .
  • the AD conversion operations in the S conversion periods S 1 and S 2 will be described separately in terms of a case where the photodiode PD receives light from a high-luminance object and a case where the photodiode PD receives light from a low-luminance object.
  • the threshold for determining the “low luminance” and the “high luminance” of an object is the level of the ramp signal VRMPI at the time T 9 .
  • FIG. 9C illustrates count signals 123 - 0 to 123 - 5 of the lower 6 bits of the count signal group 123 and pulses of the count signal 123 - 3 M in the S conversion period S 1 and the S conversion period S 2 .
  • the count signals 123 - 0 to 123 - 2 and 123 - 3 M exhibits a Gray code value of “0000” (“0” in the decimal numbering system).
  • the value increases depending on elapsed time.
  • the Gray code value reaches “1000” (“15” in the decimal numbering system)
  • it returns to “0000” again.
  • the count signals 123 - 4 to 123 - 10 always have a low level (0).
  • the 4 bit Gray code signal configured by the count signals 123 - 0 to 123 - 2 and 123 - 3 M repeats counts 0 to 15. Therefore, at the time T 8 A when the level of the control signal VCOMP is changed, the S latches 200 -S in the first memory group 121 holds one of the count signals 0 to 15 in Gray code.
  • the decision signal memory 128 holds the signal VCOMP having a low level.
  • the control signal VCOMP changes from a high level to a low level during the S conversion period S 1 . Because the signal VCOMP has a low level at the time T 9 A, the selecting circuit 108 selects VRMP 1 as a signal to be output in the S conversion period S 2 .
  • the count signals 123 - 0 to 123 - 10 exhibits a Gray code value of “0 . . . 0000” (“0” in the decimal numbering system).
  • the values exhibited by the count signals 123 - 0 to 123 - 10 increase depending on elapsed time.
  • 11-bit Gray code configured by the count signals 123 - 0 to 123 - 10 is counted. Therefore, at the time T 10 A when the level of the signal VCOMP changes, the S latches 200 -S in the second memory group 122 hold count signals in the 11-bit Gray code.
  • two AD conversions are performed in two periods of the S conversion periods S 1 and S 2 . Because the count signal to be held in the S conversion period S 2 is 11 bits, that is, all bits of the count signal group 123 , the count signal to be held in the S conversion period S 1 is lower 4 bits of the count signal group 123 .
  • the digital signals acquired in the S conversion periods S 1 and S 2 as described above may be used to add or average results of the two AD conversions so that noise included in the AD conversion results can be reduced.
  • the count signal output in the S conversion period S 1 is different from the count signal output in the S conversion period S 2 .
  • the count signals 123 - 3 to 123 - 10 not related to the AD conversion operations have a low level at all times.
  • the power consumption can be reduced, compared with a case where the levels of the count signals 123 - 3 to 123 - 10 are also changed in the S conversion period S 1 .
  • the count signal in the S conversion periods S 1 and S 2 have identical operating timing.
  • the count signal output by the counter 1050 for the first AD conversion and the count signal output by the counter 1050 for the second AD conversion may be identical.
  • the counter 1050 performs common operations in the first AD conversion and in the second AD conversion, which may simplify the control over the operations of the counter 1050 .
  • the selecting circuit 108 selects the ramp signal VRMP 2 as a ramp signal VRMPI to be used in the S conversion period S 2 .
  • the subsequent AD conversion operations at the time T 9 are the same as those to be performed when an object has a low luminance.
  • each memory group holds a lower 4-bit digital signal held in the S conversion period S 1 and whole 11-bit digital signal held in the S conversion period S 2 . Therefore, because simple addition of them does not result in the target value, arithmetic operation processing which will be described below may be required.
  • the arithmetic operation processing is performed digital signals after converted from Gray code to binary code.
  • S 1 (ALL)+S 2 (ALL) which is a sum of two AD conversion results.
  • Known values held in each memory group are S 1 (Lo) and S 2 (ALL). From this point of view, S 1 (ALL)+S 2 (ALL) is changed as follows.
  • Bin[ 0 ] to Bin[ 3 ] are lower 4 bits of a waveform of each bit after S 1 or S 2 is binarized.
  • a Row S 2 (ALL) is an example of possible values of Bin[ 0 ] to Bin[ 3 ].
  • S 2 (ALL) is “55” (binary value of “110111”).
  • a row S 2 (Lo) shows a value “7” (binary value of “0111”) of lower 4 bit s when S 2 (ALL) is “55”.
  • S 2 (ALL) is “55”
  • the possible range of S 1 (ALL) is “55” ⁇ 7 [LSB].
  • a row S 1 (Lo) shows “0” to “14” (binary values of “0000” to “1110”) which are lower 4 bits of S 1 (ALL).
  • a row S 1 (Lo) ⁇ S 2 (Lo) shows values acquired by subtracting S 2 (Lo) from S 1 (Lo), and the diff row shows a result after digit processing is performed thereon. Because digit processing is not performed in this case, a value identical to that of the row S 1 (Lo) ⁇ S 2 (Lo) can be acquired.
  • a row S 1 +S 2 (expected value) shows expected values of an added value S 1 (ALL)+S 2 (ALL) of AD conversion results in a possible range (“55” ⁇ 7[LSB]) of S 1 (ALL) where S 2 (ALL) is “55”.
  • a row S 1 +S 2 shows the following expression which is a calculated value acquired if the digit processing is not performed. 2 ⁇ S 2 (ALL)+ S 1 (Lo) ⁇ S 2 (Lo)
  • a row S 1 +S 2 shows the following expression which is a calculated value after digit processing is performed. 2 ⁇ S 2 (ALL)+diff
  • Digit processing is required to be performed such that the value can be equal to S 1 +S 2 (expected value). Because ⁇ 8 ⁇ S 1 (Lo) ⁇ S 2 (Lo) ⁇ 8 in this case, no difference occurs between S 1 +S 2 (Simple) and S 1 +S 2 (expected value) in the illustrated possible range of S 1 . Therefore, no digit processing is required in this case.
  • S 2 (ALL) is “63” (a binary value of “111111”)
  • S 2 (Lo) is “15” (a binary value of “1111”).
  • S 1 (ALL) is “64”(a binary value of 1000000) which is higher than S 2 (ALL) by “1” will be considered below.
  • the value S 1 (Lo) actually held in the first memory group 121 is “0” (a binary value of 0000), and the following expression is satisfied without performing digit processing.
  • S 2 (ALL) is “64” (a binary value of 1000000), and S 2 (Lo) is “0” (a binary value of 0000).
  • S 1 (ALL) is “63”(a binary value of “111111”) which is larger than S 2 (ALL) by “1”
  • S 1 (Lo) actually held in the first memory group 121 is “15” (a binary value of “1111”), and if digit processing is not performed, the following expression is satisfied.
  • the digit processing has been described in terms of AD conversion results of an optical signal in a case where an object ha a low luminance. However, the same processing may be performed on AD conversion results at a pixel reset level. After the digit processing ends, performing digital CDS processing can provide image data from which noise included at a reset level can be removed.
  • the aforementioned digit processing method may be performed in a following stage of each memory group within the imaging apparatus and may be performed by a video signal processing unit in a following stage of the imaging apparatus.
  • a plurality of AD conversions are performed on a pixel signal output from one pixel.
  • Adding AD conversion results acquired by performing a plurality of AD conversions can reduce noise.
  • This addition can reduce the bit width of the first memory group 121 compared with the all bit count of a signal in accordance with assumed noise.
  • This can reduce the number of memories within the first memory group 121 compared with a case where the number of memories are set to be equal to the all bit count of a signal. For example, 11 memories are reduced to four memories in the example above. Therefore, the number of components of the imaging apparatus can be reduced.
  • a count signal output from a counter signal group is Gray code
  • it may be any form except for Gray code.
  • binary code using normal binary digits may be applied.
  • Gray code may be applied to a count signal.
  • bit width of the first memory group 121 is 4 bits, that the bit width of the second memory group 122 is 11 bits, and that the count signal exhibited by the count signal group 123 is also 11 bits, an embodiment of the present invention is not limited thereto.
  • the bit count may be any arbitrary value without departing from the spirit and scope of the present invention.
  • the bit count may be generalized as described below. In a case where the absolute value of a difference value between the first and second AD conversion results is equal to or lower than 2 N ⁇ 1 [LSB] (where N is a natural number), the bit width of the first memory group 121 is N+1 bits.
  • the bit width of the second memory group 122 and the bit count of a count signal exhibited by the count signal group 123 is M bits (where M is a natural number) higher than N+1.
  • the first memory group 121 holds values from the least significant bit to the (N+1)th bit of the count signal group 123 .
  • the second memory group 122 holds values from the least significant bit to the Mth bit of the count signal group 123 .
  • the aforementioned digit processing can be generalized by using N as will be described below.
  • the imaging apparatus is configured to perform two AD conversions and holds the AD conversion results in two memory groups
  • the number of AD conversions and the number of memory groups are not limited to two. For example, three or more AD conversions may be performed, and the AD conversion results may be held in three or more memory groups.
  • the addition may be replaced by other methods.
  • the addition processing described above may be replaced by averaging processing which divides the added value by the number of added signals.
  • This exemplary embodiment relates to an imaging system applying an imaging apparatus according to any one of the first to third exemplary embodiments.
  • the imaging system may be a digital still camera, a digital camcorder, or a surveillance camera, for example.
  • FIG. 6 is a schematic diagram illustrating a case where the imaging apparatus is applied to a digital still camera as an example of the imaging system.
  • the imaging system illustrated in FIG. 6 has a barrier 151 for lens protection, a lens 152 for focusing an optical image of an object to an imaging apparatus 154 , and a diaphragm 153 for adjustment of the amount of light to pass through the lens 152 .
  • the lens 152 and the diaphragm 153 configure an optical system which gathers light to the imaging apparatus 154 .
  • the imaging system illustrated in FIG. 6 further has an output signal processing unit 155 configured to process an output signal from the imaging apparatus 154 .
  • the output signal processing unit 155 is configured to perform operations including correcting or compressing as required and outputting the resulting signal.
  • the imaging system illustrated in FIG. 6 further has a buffer memory unit 156 configured to temporarily store image data and an external interface unit 157 for communication with an external computer, for example.
  • the imaging system further has a recording medium 159 detachably mounted thereto, such as a semiconductor memory, to and from which imaged data is written and read out and a recording medium control interface 158 usable for writing and reading to and from the recording medium 159 .
  • the solid-state imaging system further has a general control/calculation unit 1510 configured to control arithmetic operations and the entire digital still camera, and a timing supply unit 1511 configured to output timing signals to the imaging apparatus 154 and the output signal processing unit 155 .
  • timing signals may be input from outside, and the imaging system may have at least the imaging apparatus 154 and the output signal processing unit 155 configured to process an output signal from the imaging apparatus 154 .
  • the output signal processing unit 155 may be a signal processing unit externally provided to imaging apparatus as in the first to third exemplary embodiments.
  • the imaging system of this exemplary embodiment applies the imaging apparatus 154 to perform imaging operations.
  • the present invention can achieve proper balance between the length of a period required for AD conversions and the width of a dynamic range.

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JP6921587B2 (ja) 2017-03-31 2021-08-18 キヤノン株式会社 撮像装置、撮像システム、移動体
KR20190020408A (ko) * 2017-08-21 2019-03-04 에스케이하이닉스 주식회사 고 선형성의 투-스텝 싱글-슬롭 비교 장치 및 그에 따른 씨모스 이미지 센서
JP7005231B2 (ja) * 2017-08-28 2022-01-21 キヤノン株式会社 撮像装置、撮像システム、移動体
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