US9331575B2 - Phase adjustment circuit of power converter, power converter, and control method thereof - Google Patents

Phase adjustment circuit of power converter, power converter, and control method thereof Download PDF

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US9331575B2
US9331575B2 US14/265,372 US201414265372A US9331575B2 US 9331575 B2 US9331575 B2 US 9331575B2 US 201414265372 A US201414265372 A US 201414265372A US 9331575 B2 US9331575 B2 US 9331575B2
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signal
terminal
coupled
amplifier
error signal
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US20150022171A1 (en
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Ya-Ping Chen
Hung-Hsuan Cheng
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UPI Semiconductor Corp
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UPI Semiconductor Corp
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H02M2001/0025—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y02B70/1466—

Definitions

  • the invention relates to a power converter.
  • the invention relates to a phase adjustment circuit of a power converter, the power converter, and a control method of the power converter.
  • FIG. 1 is a schematic diagram illustrating a conventional power converter.
  • FIG. 2 is a schematic diagram illustrating waveforms in a conventional power converter. Please refer to both FIG. 1 and FIG. 2 .
  • the existing power converter 100 is often designed in a circuit structure featuring a constant on time (COT) control architecture.
  • a comparator 110 of the power converter 100 generates a comparison signal Xcm by comparing an error signal Xerr with a ramp signal Xramp.
  • a timing controller circuit 120 generates a pulse width modulation (PWM) signal Xpwm according to the comparison signal Xcm, an input voltage Vin, and an output voltage Vout.
  • PWM pulse width modulation
  • the width of the on time Ton of the PWM signal Xpwm is fixed in each cycle, and the width of the on time Ton (as shown in FIG. 2 ) is associated with the input voltage Vin and the output voltage Vout.
  • the comparison signal Xcm is generated according to the error signal Xerr and the ramp signal Xramp, and the time point at which the on time Ton of the PWM signal Xpwm is output is determined according to the comparison signal Xcm.
  • the value of the error signal Xerr is associated with both a feedback signal Vfb and a reference voltage Vref.
  • the conventional PWM operation may ensure the fixed frequency.
  • an equivalent serial resistance DCR of an inductor L and an equivalent serial resistance ESR of a capacitor CL at an output terminal of the power converter 100 are rather small, the energy compensated by the capacitor CL and the inductor L in response to the transient variation of the load is delayed, and therefore the feedback signal Vfb and the error signal Xerr are also delayed.
  • the error signal Xerr originally generated by a compensation circuit 130 can no longer be applied to converge the output voltage Vout, and hence the waveforms of the output voltage Vout oscillate in a noticeable manner.
  • the invention is directed to a phase adjustment circuit of a power converter, the power converter, and a control method of the power converter, which resolves the problem exemplarily mentioned in the related art.
  • a phase adjustment circuit of a power converter is provided.
  • the phase adjustment circuit generates a delay signal according to an error signal and amplifies a difference between the error signal and the delay signal to provide a control signal according to the amplified difference and the error signal.
  • the error signal is associated with an output voltage of the power converter.
  • the phase adjustment circuit includes a first amplifier, a first resistor, a first capacitor, and a voltage control voltage source (VCVS).
  • a first input terminal of the first amplifier receives the error signal.
  • a first terminal of the first resistor is coupled to a second input terminal and an output terminal of the first amplifier.
  • the first capacitor is coupled between a second terminal of the first resistor and a ground terminal.
  • a first input terminal of the VCVS is coupled to the first terminal of the first resistor.
  • a second input terminal of the VCVS is coupled to the second terminal of the first resistor.
  • a first output terminal of the VCVS outputs the control signal.
  • a second output terminal of the VCVS is coupled to the first input terminal of the first amplifier.
  • the phase adjustment circuit includes a second amplifier, a second resistor, and a second capacitor.
  • a first input terminal of the second amplifier receives the error signal.
  • An output terminal of the second amplifier outputs the control signal.
  • the second resistor is coupled between a second input terminal and the output terminal of the second amplifier.
  • the second capacitor is coupled between the second input terminal of the second amplifier and a ground terminal.
  • the phase adjustment circuit further includes a current source, a first current mirror, a first p-type metal oxide semiconductor transistor, a third capacitor, a first n-type metal oxide semiconductor transistor, a third resistor, and a second current mirror.
  • the first current mirror is coupled between an operating voltage and the current source.
  • a source of the first p-type metal oxide semiconductor transistor is coupled to the first mirror.
  • a gate of the first p-type metal oxide semiconductor transistor receives the error signal.
  • a first terminal of the third capacitor is coupled to the operating voltage.
  • a second terminal of the third capacitor is coupled to the source of the first p-type metal oxide semiconductor transistor.
  • a gate of the first n-type metal oxide semiconductor transistor is coupled to the gate of the first p-type metal oxide semiconductor transistor.
  • a first terminal of the third resistor is coupled to the source of the first n-type metal oxide semiconductor transistor.
  • the second current mirror is coupled to a drain of the first p-type metal oxide semiconductor transistor, a second terminal of the third resistor, and a ground terminal.
  • the control signal is generated at a region where the second current mirror and the third resistor are coupled to each other.
  • a phase of the control signal leads a phase of the error signal.
  • a power converter in an embodiment of the invention, includes a first amplifier, a phase adjustment circuit, a comparator, and a control circuit.
  • a first input terminal of the first amplifier receives the error signal.
  • a second input terminal of the first amplifier receives the feedback signal.
  • the feedback signal is associated with an output voltage of the power converter.
  • An output terminal of the first amplifier outputs the error signal.
  • the phase adjustment circuit is coupled to the first amplifier. Besides, the phase adjustment circuit generates a delay signal according to the error signal and amplifies a difference between the error signal and the delay signal to provide a control signal according to the amplified difference and the error signal.
  • a first input terminal of the comparator receives the control signal.
  • a second input terminal of the comparator receives a ramp signal. An output terminal of the comparator outputs a comparison signal.
  • the control circuit generates a pulse width modulation (PWM) signal according to the comparison signal, so as to control the power converter.
  • PWM pulse width modulation
  • a control method of a power converter includes following steps.
  • a delay signal is generated according to an error signal, and the error signal is associated with an output voltage of the power converter.
  • a difference between the error signal and the delay signal is amplified. According to the amplified difference and the error signal, a control signal is provided.
  • the error signal is converted into a new control signal through the phase-lead mechanism, and the control signal replaces the error signal.
  • the control signal may contribute to phase compensation; hence, the output voltage of the power converter may be converged in a rapid manner, and the transient response is rather stable.
  • FIG. 1 is a schematic diagram illustrating a conventional power converter.
  • FIG. 2 is a schematic diagram illustrating waveforms in a conventional power converter.
  • FIG. 3 is a schematic diagram illustrating the structure of a power converter according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram illustrating a phase adjustment circuit according to a first embodiment of the invention.
  • FIG. 5 is a schematic diagram illustrating a phase adjustment circuit according to a second embodiment of the invention.
  • FIG. 6 illustrates an analysis result of waveforms in a power converter according to an embodiment of the invention.
  • FIG. 7 illustrates a comparison result between waveforms in a power converter and waveforms in a conventional power converter according to an embodiment of the invention.
  • FIG. 8 is a flowchart illustrating a control method of a power converter according to an embodiment of the invention.
  • FIG. 9 is a schematic diagram illustrating a phase adjustment circuit according to a third embodiment of the invention.
  • the device when one device is “connected to” or “coupled to” another device, the device may be directly connected to or coupled to another device; alternatively, there may be a device between the two connected or coupled devices.
  • the term “circuit” or “unit” may represent one or plural devices; these devices may be actively and/or passively coupled to each other or one another to perform proper functions.
  • the term “signal” may refer to at least one current, voltage, load, temperature, data, or any other signal.
  • FIG. 3 is a schematic diagram illustrating the structure of a power converter according to an embodiment of the invention. Please refer to FIG. 3 .
  • the power converter 300 includes a driver 10 , an output stage 20 , an inductor L, a capacitor CL, a feedback circuit 30 , and a feedback control circuit 40 .
  • a first terminal of a high side switch 21 in the output stage 20 receives an input voltage Vin.
  • a low side switch 22 is coupled between a second terminal of the high side switch 21 and a ground terminal GND.
  • the feedback control circuit 40 and the driver 10 may together construct a DC-DC controller; while the DC-DC controller is applied in an integrated circuit (IC), a compensation circuit 130 in the feedback control circuit 40 may be configured outside the IC.
  • the feedback control circuit 40 may construct a DC-DC controller and is applied in a single IC.
  • the feedback control circuit 40 , the driver 10 , and the output stage 20 may together construct a DC-DC converter; while the DC-DC converter is applied in an IC, the compensation circuit 130 in the feedback control circuit 40 may be configured outside the IC.
  • the feedback control circuit 40 includes an amplifier 310 , a phase adjustment circuit 320 , a comparator 330 , and a control circuit 340 .
  • the feedback control circuit 40 may further include a compensation circuit 130 .
  • a first input terminal of the amplifier 310 receives a reference voltage Vref.
  • a second input terminal of the amplifier 310 receives a feedback signal Vfb.
  • the feedback signal Vfb is associated with an output voltage Vout of the power converter 300 .
  • the feedback signal Vfb may also be the output voltage Vout.
  • An output terminal of the amplifier 310 outputs an error signal Verr.
  • the phase adjustment circuit 320 is coupled to the amplifier 310 and provides a control signal Vnew_err according to the error signal Verr.
  • a first input terminal of the comparator 330 receives the control signal Vnew_err.
  • a second input terminal of the comparator 330 receives a ramp signal Vramp.
  • An output terminal of the comparator 330 outputs a comparison signal Vcm.
  • the control circuit 340 generates a pulse width modulation (PWM) signal Vpwm according to the comparison signal Vcm, so as to control the power converter 300 .
  • the PWM signal Vpwm may be a constant-on-time (COT) signal.
  • the PWM signal Vpwm may be of another type, which should not be construed as a limitation to the invention.
  • the driver 10 According to the PWM signal Vpwm, the driver 10 generates a high side switch control signal UG and a low side switch control signal LG, so as to respectively control the high side switch 21 and the low side switch 22 .
  • the output stage 20 serves to perform a DC-DC conversion on the input voltage Vin, and thereby the power converter 300 may generate the output voltage Vout and output the output voltage Vout to a load.
  • the phase adjustment circuit may be referred to as a delay processing circuit for performing delay processing on the error signal Verr.
  • the delayed error signal is then added to the original error signal Verr to generate the new error signal Vnew_err (i.e., the control signal Vnew_err).
  • FIG. 4 is a schematic diagram illustrating a phase adjustment circuit according to a first embodiment of the invention. Please refer to FIG. 4 .
  • the phase adjustment circuit 320 A described herein may be applied to the power converter 300 shown in FIG. 3 .
  • the phase adjustment circuit 320 A includes an amplifier 321 , a resistor Rdelay, a capacitor Cdelay, and a voltage control voltage source (VCVS) 322 .
  • VCVS voltage control voltage source
  • a first input terminal of the amplifier 321 receives the error signal Verr.
  • the error signal Verr is associated with the output voltage Vout of the power converter 300 .
  • a first terminal of the resistor Rdelay is coupled to a second input terminal and an output terminal of the amplifier 321 .
  • the capacitor Cdelay is coupled between a second terminal of the resistor Rdelay and the ground terminal GND.
  • a first input terminal of the VCVS 322 is coupled to the first terminal of the resistor Rdelay.
  • a second input terminal of the VCVS 322 is coupled to the second terminal of the resistor Rdelay.
  • a first output terminal of the VCVS 322 outputs the control signal Vnew_err.
  • a second output terminal of the VCVS 322 is coupled to the first input terminal of the amplifier 321 .
  • the phase adjustment circuit 320 A generates a delay signal Verr_delay according to the error signal Verr and amplifies a difference ⁇ between the error signal Verr and the delay signal Verr_delay through multiplying the difference ⁇ by multiplying power K (K is greater than 1). If the multiplying power K ranges from 0 to 1, the difference ⁇ may be reduced. According to the amplified difference (K* ⁇ ) and the error signal Verr, the phase adjustment circuit 320 A provides the control signal Vnew_err. Note that the phase of the control signal Vnew_err leads the phase of the error signal Verr.
  • FIG. 5 is a schematic diagram illustrating a phase adjustment circuit according to a second embodiment of the invention. Please refer to FIG. 5 .
  • the phase adjustment circuit 320 B described herein may be applied to the power converter 300 shown in FIG. 3 .
  • the phase adjustment circuit 320 B includes an amplifier 323 , a resistor Rdelay, and a capacitor Cdelay.
  • the resistor Rdelay is coupled between a second input terminal and an output terminal of the amplifier 323 .
  • the capacitor Cdelay is coupled between the second input terminal of the amplifier 323 and the ground terminal GND.
  • a first input terminal of the amplifier 323 receives the error signal Verr.
  • a delay signal Verr_delay is generated by delaying the error signal Verr.
  • the amplifier 323 may be a transconductance amplifier.
  • FIG. 9 is a schematic diagram illustrating a phase adjustment circuit according to a third embodiment of the invention. Please refer to FIG. 9 .
  • the phase adjustment circuit 320 C described herein may be applied to the power converter 300 shown in FIG. 3 .
  • the phase adjustment circuit 320 C includes a current source 91 , a current mirror 92 , a p-type metal oxide semiconductor transistor (PMOS) MPC, a capacitor Cdelay, an n-type metal oxide semiconductor transistor (NMOS) MNC, a resistor R, and a current mirror 93 .
  • the current mirror 92 includes PMOSs MP 1 , MP 2 , MP 3 , and MP 4 .
  • the current mirror 93 includes NMOSs MN 1 , MN 2 , MN 3 , and MN 4 .
  • the current mirror 92 is coupled between an operating voltage VDD and the current source 91 .
  • a source of the PMOS MPC is coupled to the current mirror 92 .
  • a gate of the PMOS MPC receives the error signal Verr.
  • a first terminal of the capacitor Cdelay is coupled to the operating voltage VDD.
  • a second terminal of the capacitor Cdelay is coupled to the source of the PMOS MPC.
  • a gate of the NMOS MNC is coupled to the gate of the PMOS MPC.
  • a first terminal of the resistor R is coupled to the source of the NMOS MNC.
  • the current mirror 93 is coupled to a drain of the PMOS MPC, a second terminal of the resistor R, and the ground terminal GND.
  • the control signal Vnew_err is generated at a region where the current mirror 93 and the resistor R are coupled to each other.
  • the operational principle of the phase adjustment circuit 320 C is described below.
  • the current mirror 92 mirrors a constant current Ib to the source of the PMOS MPC.
  • the mirrored current is obtained by multiplying the constant current Ib by multiplying power K1.
  • the error signal Verr is delayed by the capacitor Cdelay to generate the delay signal Verr_delay.
  • the capacitor Cdelay is able to adjust a small signal delay ratio of the error signal Verr.
  • the error signal Verr is converted into a shift signal Verr_ofs through the NMOS MNC with a source-follow configuration.
  • the shift signal Verr_ofs is in phase with the error signal Verr.
  • the current mirror 93 mirrors a current (that flows through the PMOS MPC) to the source of the NMOS MNC.
  • the current information is converted into voltage information by the current mirror 93 after the current flowing through the resistor R, and the current information is added to the shift signal Verr_ofs, so as to obtain the new control signal Vnew_err. Note that the phase of the control signal Vnew_err leads the phase of the error signal Verr.
  • FIG. 6 illustrates an analysis result of waveforms in the power converter according to an embodiment of the invention. Please refer to FIG. 3 , FIG. 4 , and FIG. 6 together, and the following descriptions are given with reference to the embodiment shown in FIG. 4 .
  • the waveform 63 represents a load current Iload.
  • the waveform 65 represents an inductor current IL on the inductor L.
  • the load current Iload is determined (the waveform 63 )
  • the waveform 61 of the output voltage Vout falls.
  • the waveform 61 oscillates and then reaches a constant value.
  • the difference ⁇ is amplified by multiplying the difference ⁇ by the multiplying power K, for instance, and K is greater than 1.
  • the amplified difference is K*(Verr ⁇ Verr_delay), as shown by the waveform 67 .
  • the waveform 67 is located above the horizontal line, the positive sign (+) is employed to represent that the energy is greater than the load current Iload.
  • the negative sign ( ⁇ ) is employed to represent that the energy is less than the load current Iload.
  • the waveform 67 and the original error signal Verr are added to generate the new control signal Vnew_err.
  • the phase of the control signal Vnew_err leads the phase of the original error signal Verr, and thus the output voltage Vout of the power converter 300 may be converted in an expedited manner, the transient response speed may be improved, and the stability is further enhanced according to the present embodiment in comparison with the related art.
  • FIG. 7 illustrates a comparison result between waveforms in a power converter and waveforms in a conventional power converter according to an embodiment of the invention.
  • the way to control the PWM operation is determined according to the error signal Xerr and the ramp signal Xramp, and the waveforms 71 and 73 respectively represent the output voltage Vout and the inductor current IL.
  • the power converter 300 described herein determines the way to control the PWM operation according to the control signal Vnew_err and the ramp signal Vramp, and the waveforms 72 and 74 respectively represent the output voltage Vout and the inductor current IL.
  • the oscillation amplitude of the waveform 72 is smaller than that of the waveform 71 .
  • the oscillation amplitude of the waveform 74 is smaller than that of the waveform 73 . Since the control signal Vnew_err of the power converter 300 may contribute to loop phase compensation. Hence, during the loop control, the output voltage Vout of the power converter 300 may be converged in a rapid manner, and the transient response is rather stable.
  • FIG. 8 is a flowchart illustrating a control method of a power converter according to an embodiment of the invention.
  • the control method in the present embodiment may include following steps.
  • step S 801 a delay signal Verr_delay is generated according to an error signal Verr, and the error signal Verr is associated with an output voltage Vout of a power converter 300 .
  • step S 803 a difference between the error signal Verr and the delay signal Verr_delay is amplified.
  • step S 805 a control signal Vnew_err is provided according to the amplified difference and the error signal Verr. Note that a phase of the control signal Vnew_err leads a phase of the error signal Verr.
  • the error signal is converted into a new control signal through the phase-lead mechanism, and the control signal replaces the error signal.
  • the control signal may contribute to phase compensation; hence, the output voltage of the power converter may be converged in a rapid manner, and the transient response is rather stable.
  • the phase adjustment circuit of the power converter may be applied to a conventional COT structure.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
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