US9271366B2 - Dimmable LED driver and driving method - Google Patents

Dimmable LED driver and driving method Download PDF

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US9271366B2
US9271366B2 US14/843,860 US201514843860A US9271366B2 US 9271366 B2 US9271366 B2 US 9271366B2 US 201514843860 A US201514843860 A US 201514843860A US 9271366 B2 US9271366 B2 US 9271366B2
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voltage
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input current
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Feng Yu
Xiaodong Huang
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Silergy Semiconductor Technology Hangzhou Ltd
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Silergy Semiconductor Technology Hangzhou Ltd
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    • H05B33/0851
    • H05B33/0815
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
    • H05B45/00Circuit arrangements for operating light emitting diodes [LED]
    • H05B45/10Controlling the intensity of the light
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
    • H05B45/00Circuit arrangements for operating light emitting diodes [LED]
    • H05B45/30Driver circuits
    • H05B45/37Converter circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

Disclosed are dimmable LED driver circuits and methods. A dimmable LED driver can include: an SCR, an electronic transformer, and a rectifier bridge to convert an AC voltage to a DC voltage signal; a power stage circuit that receives the DC voltage signal, and outputs a constant current to drive an LED load, where the power stage circuit includes first and second power stage circuits, the first power stage circuit receiving the DC voltage signal, and generating a first output voltage to the second power stage; and an input current control circuit that receives an input current of the first power stage circuit and the first output voltage, and generates a first control signal to control the input current as a square wave signal during an on time of the SCR, and the input current is substantially zero during an off time of the SCR.

Description

RELATED APPLICATIONS

This application is a continuation of the following application, U.S. patent application Ser. No. 13/916,182, filed on Jun. 12, 2013, and which is hereby incorporated by reference as if it is set forth in full in this specification, and which also claims the benefit of Chinese Patent Application No. 201210249167.2, filed on Jul. 18, 2012, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to field of power electronics, and more particularly to a dimmable light-emitting diode (LED) driver, and a method of driving a dimmable LED.

BACKGROUND

In the lighting field, LED lights are an increasingly preferred alternative to replace traditional light sources (e.g., halogen lamps). When using LED lights to replace halogen lamps, it may be necessary to match with electronic transformers in traditional circuits to ensure normal operation of the electronic transformers. Also, accurate dimming on the LED load may be required in order to maximize advantages of energy saving and high luminous efficiency of the LED light load.

In conventional approaches, a triac dimming scheme may be utilized for dimming an LED lamp load. In an LED driver with an electronic transformer, a triac dimmer is generally placed in front of the electronic transformer. Triac dimming can be used to adjust a supply voltage for the LED lamp load by controlling a triac conducting angle, so as to realize dimming. However, conventional LED drivers generally contain a large filter capacitor, which can cause current through SCR to be uncontrollable due to LC resonance in the circuit, possibly resulting in the SCR not being able to maintain conductivity. Therefore, the LED may appear as a strobe light. In recent years, a variety of control methods using SCRs for LED dimming have also been proposed. For example, a dummy load (e.g., resistors) may be added in order to improve controllability. However, such a dummy load may lower circuit efficiency due to power consumption on the dummy load.

In addition, electronic transformers in traditional circuits were originally designed for halogen lamp (instead of LED lights) loads, so electronic transformers typically require maintaining a minimum load current during normal operation. Therefore, in an LED driver with an electronic transformer, it is difficult to ensure that the LED driver not only meets requirements of electronic transformer minimum operating current, but also can achieve accurate dimming for an LED light load to avoid LED light flash or strobe effects, and to improve circuit efficiency.

SUMMARY

In one embodiment, a dimmable light-emitting diode (LED) driver can include: (i) a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge configured to convert an AC voltage to a DC voltage signal; (ii) a power stage circuit configured to receive the DC voltage signal, and to output a constant current to drive an LED load, where the power stage circuit includes first and second power stage circuits, where the first power stage circuit is configured to receive the DC voltage signal, and to generate a first output voltage to the second power stage; (iii) an input current control circuit configured to receive an input current of the first power stage circuit and the first output voltage, and to generate a first control signal to control the input current as a square wave signal during an on time of the SCR, and the input current is maintained as substantially zero during an off time of the SCR; (iv) where, during the on time of the SCR, a peak of the input current is a substantially constant value that satisfies a minimum load current requirement of the electronic transformer, and a valley of the input current is substantially zero; and (v) where the LED driver is configured to drive the LED load in accordance with the input current and the first output voltage.

In one embodiment, a method of driving a dimmable LED, can include: (i) receiving an AC voltage to obtain a DC voltage signal through a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge; (ii) generating an input current and a first output voltage using the DC voltage signal, where the input current is generated as a square wave signal during an on time of the SCR, and the input current is maintained as substantially zero during an off time of the SCR; (iii) generating a dimming signal from the input current; (iv) generating a constant output current signal using the first output voltage, an LED load current signal, and the dimming signal; and (v) where, during the on time of the SCR, a peak of the input current is a substantially constant value that satisfies a minimum load current requirement of the electronic transformer, and a valley of the input current is substantially zero.

Embodiments of the present invention can advantageously provide several advantages over conventional approaches. For example, the minimum load current requirement of the electronic transformer can be satisfied during operation. In addition, a dimming signal that represents conducting angle information of the SCR can be obtained by detecting input current information of the first power stage circuit through a dimming signal generating circuit. The dimming signal can be used to realize precise dimming on the LED load. Other advantages of the present invention may become readily apparent from the detailed description of preferred embodiments below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic block diagram of a first example dimmable LED driver in accordance with embodiments of present invention.

FIG. 2 shows a schematic block diagram of a second example dimmable LED driver in accordance with embodiments of present invention.

FIG. 3 shows an example circuit structure diagram of a dimmable LED driver in accordance with embodiments of present invention.

FIG. 4 shows an example operation waveform diagram of an input current control circuit of the dimmable LED driver shown in FIG. 3, in accordance with embodiments of present invention.

FIG. 5 shows an example operation waveform diagram of a dimming signal generating circuit of dimmable LED driver shown in FIG. 3, in accordance with embodiments of present invention.

FIG. 6 shows a schematic block diagram of a third example dimmable LED driver in accordance with embodiments of present invention.

FIG. 7 shows an example operation waveform diagram of an input current control circuit of dimmable LED driver shown in FIG. 6, in accordance with embodiments of present invention.

FIG. 8 shows a flow diagram of an example method of driving a dimmable LED, in accordance with embodiments of present invention.

DETAILED DESCRIPTION

Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set fourth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

Various benefits can be realized by utilising dimmable light-emitting diode (LED) driver circuits and methods according to particular embodiments. For example, an input current in a first power stage circuit can be controlled by an input current control circuit to be a square wave signal during a conducting or “on” time period or portion of time of a silicon-controlled rectifier (SCR) with a constant peak value that satisfies a minimum load current requirement through an electronic transformer, and zero valley value. For example, a “valley” value may be a low or minimal value of a square wave or other periodic signal.

During a turn-off time period or “off” or non-conducting time portion of the SCR, the input current can be maintained as substantially zero, to ensure the input current remains higher than a minimum load current of the electronic transformer during operation. This can ensure that the electronic transformer does not turn off during normal operation, thereby solving the flashing or strobe problem of an LED load caused due to inadvertent turn-off of the electronic transformer.

For example, the input current waveform can represent conducting angle information of the SCR, and a dimming signal representing the conducting angle information of the SCR can be obtained by detecting input current information through a dimming signal generating circuit. This can achieve precise dimming on the LED load, as well as a broad dimming range. Also, the LED load current can be controlled as substantially constant through an output current control circuit to provide stable luminance of the LED load. In addition, particular embodiments can employ a two-stage driver structure to avoid using a large filter capacitor after the bridge rectifier, and to reduce ripple current. In this way, improved stability of the SCR load current can be achieved relative to conventional approaches. Further, the two-stage structure driver can also avoid using a dummy load to obtain a high efficiency.

In one embodiment, a dimmable light-emitting diode (LED) driver can include: (i) a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge configured to convert an AC voltage to a DC voltage signal; (ii) a power stage circuit configured to receive the DC voltage signal, and to output a constant current to drive an LED load, where the power stage circuit includes first and second power stage circuits, where the first power stage circuit is configured to receive the DC voltage signal, and to generate a first output voltage to the second power stage; (iii) an input current control circuit configured to receive an input current of the first power stage circuit and the first output voltage, and to generate a first control signal to control the input current as a square wave signal during an on time of the SCR, and the input current is maintained as substantially zero during an off time of the SCR; (iv) where, during the on time of the SCR, a peak of the input current is a substantially constant value that satisfies a minimum load current requirement of the electronic transformer, and a valley of the input current is substantially zero; and (v) where the LED driver is configured to drive the LED load in accordance with the input current and the first output voltage.

Referring now to FIG. 1, shown is a block schematic diagram of a first example dimmable LED driver in accordance with embodiments of present invention. After being processed by an SCR or other rectifier circuit or Triac, and an electronic transformer, a grid AC voltage can be input to a rectifier bridge to obtain a DC voltage signal Vin. Also, power stage circuitry 10 can be used for receiving DC voltage signal Vin and to output a substantially constant current to drive an LED load. As shown in FIG. 1, power stage circuitry 10 can include power stage circuit 101 and power stage circuit 102. For example, power stage circuit 101 can be a first stage boost circuit, and may include inductor L1, diode D1, switch Q1, and output capacitor Cbus.

For example, stage circuit 102 can be a second stage buck topology circuit, and may include inductor L2, switch Q2, switch Q3, and output capacitor Cout. Power stage circuit 101 can receive DC voltage signal Vin, and convert Vin to output voltage Vbus that can be supplied to power stage circuit 102. Power stage circuit 101 can be a boost topology, and power stage circuit 102 can be buck topology or boost-buck topology. However, these power stage circuits can also be any suitable topology in particular embodiments. This particular example dimmable LED driver can also include input current control circuit 11, dimming signal generating circuit 12, and output current control circuit 13.

In particular embodiments, input current control circuit 11 can be used for receiving input current Iin of power stage circuit 101 and output voltage Vbus, and may generate control signal PWM1. Control signal PWM1 can be used for controlling input current to be a square wave signal during a conducting or on time of the SCR. The current peak of the square wave signal can be a substantially constant value that satisfies a minimum load current requirement of electronic transformer, while the current valley or low point of the square wave signal can be essentially zero. When the SCR is off, input current can be kept at zero. Input current Iin of power stage circuit 101 can be obtained by sampling current of inductor L1, and may be configured as a load current of the electronic transformer. In particular, control signal PWM1 can control input current Iin and output voltage Vbus by controlling a switching operation of switch Q1.

Dimming signal generating circuit 12 can receive input current Iin of power stage circuit 101 and May output dimming signal Tout ref that represents conducting angle information of the SCR. Output current control circuit 13 can receive current signal IED of the LED load and dimming signal Iout ref from dimming signal generating circuit 12 to generate control signal PWM2 for controlling power stage circuit 102 to provide a substantially constant output current signal for LED load. In this way, dimming may be realized for the LED load. More specifically, control signal PWM2 can control a switching operation of switch Q2, and an inverted version of control signal PWM2 can control a switching operation of switch Q3, to realize substantially constant current control and brightness adjustment of the LED load.

By controlling input current of power stage circuit 101 to be a square wave signal during an on time of the SCR, a peak value can be a substantially constant value to meet minimum load current requirements of the electronic transformer, and the current valley of the square wave signal can be essentially zero. During an off time of the SCR, input current can be maintained at essentially zero. In this way, input current can be ensured to meet minimum load current requirements of the electronic transformer during normal operation, and to maintain the electronic transformer in a normal operating state. This approach a particular embodiments can solve problems caused by LED blinks or strobe action due to inadvertent turn-off of electronic transformer.

In addition, a waveform of the input current may represent conducting angle information of the SCR. Therefore, dimming signal generating circuit 12 can be used to address the adjusting of brightness of the LED load in the exemplified two-stage circuit. Dimming signal generating circuit 12 can generate a dimming signal that represents conducting angle information of the SCR by detecting input current information, so as to adjust brightness of LED load accordingly. In this way, particular embodiments can achieve substantially constant current control and brightness regulation of LED load in a two-stage circuit, as well as high precision control and broad dimming scope.

Referring now to FIG. 2, shown is a schematic block diagram of a second example dimmable LED driver in accordance with embodiments of the present invention. In this example, input current control circuit 21 can include current control circuit 21-1, voltage control circuit 21-2, and logic circuit 21-3. For example, current control circuit 21-1 can receive input current Iin and reference current Iref1, and may generate current control signal Vct1. Reference current Iref1 can correspond to a peak value of square wave signal that represents input current Iin. Voltage control circuit 21-2 can receive output voltage Vbus and reference voltage Vref1, and may generate voltage control signal Vct2. Logic circuit 21-3 can receive current control signal Vct1 and voltage control signal Vct2, and may generate control signal PWM1 after performing a logic operation.

In this particular embodiment, when the SCR is turned on at a certain angle, power stage circuit 26 (e.g., a first stage boost circuit) can absorb power from the input side and begin to operate. Then, voltage control circuit 21-2 can generate voltage control signal Vct2 to control output voltage Vbus to fluctuate within a relatively small voltage range, for minimal ripple on Vbus. Also, when output voltage Vbus reaches an upper limit value of the desired voltage range, voltage control circuit 21-2 can control power switch Q1 to turn off. Therefore, power stage circuit 26 can operate in a discontinuous operating mode. Thus, input current Iin can be in a shape of a plurality of pulses, such as square wave signal(s).

Also, during operation of power stage circuit 26, current control circuit 21-1 can form a peak of square wave signal as substantially constant, where the constant value can be determined according to reference current Iref1. In this example, reference current Iref1 can be set as slightly greater than the minimum load current of electronic transformer, so that peak of square wave signal can meet minimum load current requirements of the electronic transformer. On other hand, when power stage circuit 26 stops operating, input current Iin may drop to zero such that the valley value of square wave signal can be zero. Thereafter, when the SCR is turned off, input current Iin can be maintained at essentially zero.

Thus, as can be seen from above operating process, an LED driver in particular embodiments may not need to change circuit structures of the SCR and electronic transformer that are found in conventional circuitry. Instead, particular embodiments may control input current Iin of power stage circuit 26 through input current control circuit 21-1. Thus, the input current can meet minimum load current requirements of electronic transformers, and they enable the electronic transformer to operate normally. Also, the input current waveform can represent conducting angle information of the SCR, and therefore can be used as an input signal of a latter-stage dimming signal generating circuit (e.g., 22), to generate a dimming signal that represents the conducting angle of SCR.

Referring now to FIG. 3, shown is an example circuit structure diagram of a dimmable LED driver in accordance with embodiments of present invention. Here, input current control circuit 31 is one example implementation of input current control circuit 21 in FIG. 2. Current control circuit 21-1 can include comparator 301, and a non-inverting input terminal of comparator 301 can receive input current while in inverting input terminal can receive reference current Iref1. By comparing reference current Iref1 against input current a comparison signal can be generated as current control signal Vct1. Alternatively, considering the influence of a changing duty cycle of a switch on the input current, the non-inverting input terminal of comparator 301 may receive a superimposed signal of reference current Iref1 and a ramp signal, so as to improve stability of sampled input current.

Voltage control circuit 21-2 can include hysteresis comparator 302. A non-inverting input terminal of hysteresis comparator 302 can receive output voltage Vbus, and the inverting input terminal can receive reference voltage Vref1. In this particular example, hysteresis comparator 302 can receive hysteresis reference voltage Vhys ref as reference voltage Vref1, and may generate a hysteresis comparison signal. The hysteresis comparison signal can be configured as voltage control signal Vct2, where hysteresis comparator 302 has a hysteresis width set by an upper limit threshold voltage VH and lower limit threshold voltage VL.

Logic circuit 21-3 in this particular example can include OR-gate 303 and flip-flop 304. For example, flip-flop 304 can be an RS type flip-flop. Current control signal Vct1 and voltage control signal Vct2 can be input to a reset terminal of flip-flop 304 via the logic operation of first OR-gate 303. The set terminal of flip-flop 304 can receive clock signal CLK1, and the output terminal can output control signal PWM1 to control a switching operation of switch Q1 in power stage circuit 26.

Dimming signal generating circuit 32 in this example can include timing circuit 305 and averaging circuit 306. Timing circuit 305 can receive input current Iin of power stage circuit 26 and threshold current Ith, and output square wave signal “Angle” that represents conducting angle information of SCR. Averaging circuit 306 can receive reference current Iref2 and square wave signal Angle, and can generate a relatively smooth dimming signal Iout ref that represents the conducting angle signal of SCR by averaging reference current Iref2 in accordance with square wave signal Angle. For example, threshold current Ith can be set to be a value between zero and input current Iin.

Timing circuit 305 in this particular example can include comparator 305-1, charge-discharge circuit 305-2, clamp circuit 305-3, and comparator 305-4. For example, the inverting input terminal of comparator 305-1 can receive input current and the non-inverting input terminal can receive threshold current Ith. The output terminal of comparator 305-1 can output comparison signal CMP4 to be used for controlling the charge-discharge operation of charge-discharge circuit 305-2.

Charge-discharge circuit 305-2 can include parallel connected voltage-controlled current source, capacitor C1, and switch S1. Comparison signal CMP4 can be used to control the voltage-controlled current source so as to provide charging current for capacitor C1. Also, after being inverted, comparison signal CMP4 can be used to control a switching operation of switch S1 to control charge-discharge operation of capacitor C1. The voltage across capacitor C1 can be capacitor voltage Vc1 as shown.

Clamp circuit 305-3 may utilize clamp voltage Vp to clamp first capacitor voltage Vc1. In this particular example, clamp circuit 305-3 can include a voltage source and a zener diode, and the clamp voltage Vp can be a sum of the voltage source voltage and the breakdown voltage of the zener diode. When capacitor voltage Vc1 is greater than clamp voltage Vp, clamp circuit 305-3 can clamp the voltage of capacitor C1 to clamp voltage Vp, and clamp voltage Vp can be transmitted to comparator 305-4 as a comparative voltage signal. When capacitor voltage Vc1 is less than clamp voltage Vp, capacitor voltage Vc1 can be transmitted to comparator 305-4 as the comparative voltage signal. Also, the non-inverting input terminal of comparator 305-4 can receive the comparative voltage signal, the inverting input terminal of comparator 305-4 can receive reference voltage Vref2, and the output terminal of comparator 305-4 can output square wave signal Angle.

In this example, averaging circuit 306 can include chopper circuit 306-1 having switches S2 and S3, and RC filter circuit 306-2. Chopper circuit 306-1 can receive reference current Iref2 and square wave signal Angle, and may output chopper signal VZ by “chopping” reference current Iref2. The switching state of switch S2 can be controlled by an inverted version of square wave signal Angle, and the switching state of switch S3 can be controlled by square wave signal Angle. RC filter circuit 306-2 can receive chopper signal VZ, and may output a relatively smooth dimming signal Tout ref that represents conducting angle information of the SCR after a filter process.

Output current control circuit 33 in this example can receive LED load current signal IED and dimming signal Iout ref from dimming signal generating circuit 32, and may generate control signal PWM2. Control signal PWM2 can be used for controlling the power stage circuit 27 to provide a substantially constant output current signal for the LED load, and to realize LED load dimming. For example, output current control circuit 33 can include a current regulating circuitry and a flip-flop. For example, flip-flop 309 can be an RS type of flip-flop. One current regulating circuit can include transconductance operational amplifier 307 with a non-inverting input terminal receiving dimming signal Iout ref and an inverting input receiving LED load current signal ILED, and an output terminal that outputs a current adjusting signal.

Another current regulating circuit can include comparator 308 with an inverting input terminal that receives the current adjusting signal compensated by a compensation circuit, and a non-inverting input terminal that receives inductor current signal IL2 in power stage circuit 27. Comparator 308 may output another current adjusting signal as a reset terminal of flip-flop 309. The set terminal of flip-flop 309 can receive clock signal CLK3, and the output of flip-flop 309 can be control signal PWM2 for controlling a switching operation of switch Q2 in the power stage circuit 27. Also, an inverted version control signal PWM2 can be used for controlling the switching operation of switch Q3, so as to achieve substantially constant current control and brightness adjustment for the LED load.

The following further describes example operation of the above described LED drivers in conjunction with operation waveform diagrams of FIGS. 4 and 5. FIG. 4 shows an operation waveform diagram of an input current control circuit of the dimmable LED driver of FIG. 3, in accordance with embodiments of the present invention. FIG. 5 shows an operation waveform diagram of a dimming signal generating circuit of the dimmable LED driver of FIG. 3, in accordance with embodiments of the present invention.

Input current control circuit 31 operation will be described herein. When the SCR is turned on at a certain phase angle, the power stage circuit 26 can absorb power from the AC power supply, and input current Iin can be gradually increased. Output voltage Vbus output by the power stage circuit 26 can also gradually increase. When input current Iin reaches a level of reference current Iref1, or input current Iin reaches a level of a superimposed signal of reference current Iref1 and a ramp signal, the output of comparator 301 may go high, and switch Q1 can be turned off by the RS flip-flop 304 so that input current Iin may decrease.

When high-frequency clock signal CLK1 triggers the output of first RS flip-flop 304 to go high, then control signal PWM1 can control switch Q1 to turn on again so as to achieve a substantially constant current control of input current Thus, in the operating state of the power stage circuit 26, input current Iin can be configured as the load current of the electronic transformer. As long as input current Iin is controlled to be higher than the minimum load current of the electronic transformer, the electronic transformer during this period can remain on and operate normally. In this particular example, reference current Iref1 can set to be slightly higher than the minimum load current of the electronic transformer, so as to ensure normal operation of the electronic transformer.

As described above, after the SCR is turned on, output voltage Vbus may increase gradually. When output voltage Vbus rises to a level of upper limit voltage VH of hysteresis comparator 302, hysteresis comparison signal Vct2 output by hysteresis comparator 302 may go high. Control signal PWM1 output by RS flip-flop 304 can control switch Q1 to turn off, and input current Iin may continue decrease until reaching zero, when power stage circuit 26 may stop operating. When output voltage Vbus drops to the lower limit voltage VL of hysteresis comparator 302, hysteresis comparison signal Vct2 may go low, clock signal CLK1 at the set terminal of the RS flip-flop 304 can control switch Q1 to turn on again, and input current Iin and output voltage Vbus can increase.

This operation as described above can be repeated. As can be seen from FIG. 4, during the conducting or on time of the SCR, output voltage Vbus may vary within a relatively small hysteresis voltage range through hysteresis control. Thus, output voltage Vbus may have a relatively small ripple, thereby avoiding LED load flashing or strobe. Also, from FIG. 4 it can be seen that the fluctuation range of output voltage Vbus can be relatively small, so capacitor Cbus can be a relatively small capacitance to maintain output and reduce circuit costs.

The input current control circuit 31 can carry out hysteresis control on output voltage Vbus of the power stage circuit 26. During the on time of the SCR, power stage circuit 26 may operate in a discontinuous operating state, and input current Iin of the power stage circuit 26 can be a multi-pulse output. From FIG. 4, it can be seen that the input current waveform can be a square wave signal with a peak value that is substantially constant and greater than the minimum load current of the electronic transformer, and with a valley value of essentially zero. After the SCR is turned off, input current Iin can remain at zero.

As shown in FIG. 5, input current Iin can be a multi-pulse output. When the SCR is turned on, at time t1, input current Iin can be higher than threshold current Ith, and comparison signal CMP4 can be low. The voltage controlled current source may not generate an output current, and comparison signal CMP4 can be inverted to be high to control switch S1 to turn on, and capacitor C1 may start discharging. When capacitor voltage Vc1 drops to less than reference voltage Vref2, square wave signal Angle may go low. Then, switch Q1 can be turned off, and input current Iin may decrease. When input current Iin is less than threshold current Ith, comparison signal CMP4 may go high. At this time, switch S1 may turn off, and the voltage controlled current source can be used to charge capacitor C1. Capacitor voltage Vc1 may rise accordingly but still be less than reference voltage Vref2.

Until time t2, the SCR is turned off, and no input current may be generated in power stage circuit 26, and comparison signal CMP4 may remain high. Also capacitor C1 can be continuously charged so capacitor voltage Vc1 can continuously rise. When capacitor voltage Vc1 increases to a level of reference voltage Vref2 (e.g., at time t3 in FIG. 5), square wave signal Angle may go high, and capacitor voltage Vc1 can keep rising. When capacitor voltage Vc1 is greater than clamp voltage Vp of clamp circuit 305-3, the clamp circuit can clamp capacitor voltage Vc1 to clamp voltage Vp. In this particular example, reference voltage Vref2 can be set to make the charging time ratio of capacitor C1 to be longer than the time when the square wave signal is low, and clamp voltage Vp can set to be slightly higher than reference voltage Vref2.

As can be seen from above process, during the conducting or on time of the SCR, capacitor voltage Vc1 can be less than reference voltage Vref2, and square wave signal Angle can remain low. As can be seen from FIG. 5, there is a certain offset time Δt=t3-t2 between the low period of the square wave signal Angle and actual conducting time of the SCR, and the offset time may be a fixed value representing the charging time for charging capacitor C1 to reach reference voltage Vref2. The offset time may not affect square wave signal Angle to represent the conducting time of the SCR.

Within a half switching period, the on time of the SCR can correspond to its conducting angle information. For example, square wave signal Angle can represent the conducting angle of the SCR, and then Angle can be converted to the relatively smooth dimming signal that represents the conducting angle of the SCR through averaging circuit 306. Chopper circuit 306-1 can receive reference current Iref2 and the square wave signal Angle, and may provide a relatively smooth dimming signal Tout ref that represents the conducting angle of the SCR after chopping and filtering via 306-2. Therefore, dimming signal Tout ref can be coupled to output current control circuit 33 to realize brightness adjustment of LED load.

Based on the above description, the input current can be controlled by the input current control circuit to be a square wave signal during an on time of the SCR, with a fixed peak value that is substantially constant and larger than a minimum load current of the electronic transformer. Also, through hysteresis, a fluctuation range of the output voltage Vbus can be controlled to be relatively small to provide a relatively good operating voltage for power stage circuit 27. The dimming signal generating circuit 32 can obtain a square wave signal that corresponds to the conducting time of the SCR, and to further provide a dimming signal that represents the conducting angle information of the SCR, thereby realizing brightness adjustment of LED load in the two-stage circuit.

In this way, LED dimmer control of particular embodiments can not only meet requirements of minimum operating current of the electronic transformer to avoid LED light strobe, but may also can realize accurate dimming of the LED load. Further, particular embodiments may achieve substantially constant current control and brightness adjustment of LED. Also, components consuming large power (e.g., a dummy load) may not be needed in particular embodiments, thus increasing LED driver efficiency, as compared to conventional approaches.

Referring now to FIG. 6, shown is a schematic block diagram of a third example dimmable LED driver in accordance with embodiments of the present invention. In this example, the dimming signal generating circuit and output current control circuit are similar to those in above examples. However, implementation of the input current control circuit 61 in the present example may differ as compared to above examples, while dimming signal generating circuit 62 in FIG. 6 can be the same as dimming signal generating circuit 32 in FIG. 3, and output current control circuit 63 can be the same as output current control circuit 33 in FIG. 3.

In the example of FIG. 6, input current control circuit 61 can include a current control circuit, a voltage control circuit, and a logic circuit. The current control circuit can include transconductance operational amplifier 601, compensation circuit 602, and comparator 603. The non-inverting input of the transconductance operational amplifier 601 can receive input current Iin and the inverting input terminal can receive reference current Iref1, and operational amplifier 601 can output an error current signal. This error current signal can form error voltage signal Ve after being compensated by compensation circuit 602.

Reference current generating circuit 608 can be used for generating reference current Iref1. Reference current generating circuit 608 can receive reference current source Is, and when the square wave signal that represents input current Iin in power stage circuit 26 is active, reference current source Is can be configured as reference current Iref1. When the square wave signal is inactive, reference current Iref1 can be zero. In this particular example, reference current generating circuit 608 can achieve control on reference current Iref1 by a switch circuit that includes switches S4 and S5. For example, a switching state of switch S4 can be controlled by trigger signal V3, and a switching state of switch S5 can be controlled by an inverted version of trigger signal V3.

The inverting input terminal of comparator 603 can receive error voltage signal Ve, and the non-inverting input terminal can receive voltage signal Vs that represents the inductor current in power stage circuit 26, or can receive a superimposed signal of voltage signal Vs and a ramp signal Se2. Similarly, ramp signal Se2 can be used to guarantee better stability of sampling voltage signal Vs. The output terminal of comparator 603 can provide a comparison signal as current control signal Vct1.

The voltage control circuit can include comparator 604, and the non-inverting input terminal of comparator 604 can receive output voltage Vbus. The inverting input terminal of comparator 604 can receive a reference voltage (e.g., threshold voltage Vbus th. The comparison signal may be output from comparator 604 as voltage control signal Vct2. Also, the logic circuit can include flip-flops 605 and 606, and AND-gate 607. Each of flip-flops 605 and 606 can be RS type flip-flops. The reset terminal of the flip-flop 605 can connect current control signal Vct1, and the set terminal can connect to clock signal CLK2, while flip-flop 605 outputs trigger signal V2. The reset terminal of the flip-flop 606 can receive voltage control signal Vct2 and the set terminal can receive an enable trigger signal EN, while flip-flop 606 outputs trigger signal V3. Control signal PWM1 can be output from AND-gate 607 according to the trigger signals, and control signal PWM1 can be used for controlling the switching operation of switch Q1 in the power stage circuit 26.

The following may describe the operating process of the input current control circuit in accordance with embodiments of the present invention, in conjunction with the operational waveform diagram of FIG. 7. FIG. 7 shows one example operational waveform diagram of the input current control circuit of an example dimmable LED driver as shown in FIG. 6.

After the SCR conducts in a certain phase angle, power stage circuit 26 can absorb power from the AC power supply side. In this case, input current Iin can be gradually increased, while output voltage Vbus of power stage circuit 26 can be gradually increased. In this case, trigger signal V3 can be high, switch S4 can be turned on, and switch S5 can be turned off. Reference current value L can be as reference current Iref1, and transconductance operational amplifier 601 can receive input current Iin and reference current Iref1, and a output error voltage signal Ve. When a superimposed signal of voltage signal Vs that represents inductor current in power stage circuit 26 and ramp signal See reaches a level of error voltage signal Ve, the output of comparator 603 goes high, and the RS flip-flop 605 output may go low. AND-gate 607 can output control signal PWM1 to control switch Q1 to turn off, and input current Iin decreases.

When a pulse of high-frequency clock signal CLK2 arrives, RS flip-flop 605 output can go high. In this case, when the output of RS flip-flop 606 goes high, AND-gate 607 can output control signal PWM1 to control switch Q1 to turn on, and input current Iin can be gradually increased. By repeating the cycle, input current Iin can be maintained as substantially constant. In order to meet current requirements of the electronic transformer, reference current source L can be set to be slightly larger than the minimum load current of the electronic transformer, so that input current Iin can be maintained higher than the minimum load current during the operation of the power stage circuit 26. In this way, the electronic transformer may not be turned off to avoid flashing or a strobe effect of the LED load.

Thereafter, when output voltage Vbus gradually increases to a level of threshold voltage Vbus th, the output of the comparator 604 may go high, and the output of the RS flip-flop 606 may go low. Thus, control signal PWM1 can control switch Q1 to turn off, and input current Iin can continue to decrease to zero. Also, power stage circuit 26 may stop operating, so output voltage Vbus may gradually decrease. Also, since trigger signal V3 is low, switch S4 can be turned off, switch S5 can be turned on, and reference current Iref2 can be zero. Therefore, error voltage Ve output by transconductance operational amplifier 601 can remain unchanged, and the output of comparator 603 can be low.

When clock signal CLK2 arrives, the output of the flip-flop 605 can be high. The output of RS flip-flop 606 may go high when enable trigger signal EN arrives. Then, AND-gate 607 can output control signal PWM1 to control switch Q1 to turn on, and output current Iin may continue to rise. Correspondingly, output voltage Vbus may also increase. By repeating the operation cycle, output voltage Vbus can fluctuate within a small range and the LED load may not flash/strobe.

By controlling the enable trigger signal of the voltage control circuit, during the conducting time period of SCR, power stage circuit 26 can operate in a discontinuous operation state, and input current Iin in power stage circuit 26 can be in a shape of multi-pulse output. As can be seen from FIG. 7, the waveform of the input current can also be a square wave signal, as discussed above. Also, dimming signal generating circuit 62 can generate a square wave signal corresponding to the SCR conducting time by sampling input current and further obtaining a dimming signal that represents the conducting angle information of the SCR for diming the latter stage. Particular embodiments can also achieve accurate dimming of the LED lamp load with a relatively wide dimming range. Also, the minimum operating current requirements of the electronic transformer can be met so as to avoid LED load flashing.

In particular embodiments, the trigger period (e.g., about 1 ms) of the enable trigger signal can be set according to requirements of the user. Accordingly, the reference voltage of the dimming signal generating circuit can be set to enable the charging time of the capacitor to be longer than 1 ms.

In one embodiment, a method of driving a dimmable LED, can include: (i) receiving an AC voltage to obtain a DC voltage signal through a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge; (ii) generating an input current and a first output voltage using the DC voltage signal, where the input current is generated as a square wave signal during an on time of the SCR, and the input current is maintained as substantially zero during an off time of the SCR; (iii) generating a dimming signal from the input current; (iv) generating a constant output current signal using the first output voltage, an LED load current signal, and the dimming signal; and (v) where, during the on time of the SCR, a peak of the input current is a substantially constant value that satisfies a minimum load current requirement of the electronic transformer, and a valley of the input current is substantially zero.

Referring now to FIG. 8, shown is a flow diagram of a method of controlling dimming in an LED driver, in accordance with embodiments of the present invention. At S801, an AC voltage can be received, and a DC voltage signal can be generated after being processed by an SCR rectifier circuit, an electronic transformer, and a rectifier bridge. At S802, the DC voltage signal can be received to generate a first stage input current and a first output voltage. The input current in the SCR rectifier circuit can be a square wave signal during the on time of the SCR, and the peak can be a substantially constant value to meet minimum load current requirements of the electronic transformer, while the valley or low value of the square wave signal can be zero. During the off time of the SCR, the input current can be maintained at zero.

At S803, a dimming signal can be generated from the input current (e.g., via dimming signal generating circuit 62). At S804, a constant output current signal can be generated from the first output voltage, an LED load current signal, and the dimming signal. Step S802 can also include receiving the first stage input current and a first reference current to generate a current control signal. For example, the first reference current can correspond to the peak of the square wave signal. The first output voltage and a first reference voltage can be used to generate a voltage control signal, and a first control signal can be generated from a current control signal and a voltage control signal.

In addition, S802 can also include comparing the first stage input current with the first reference current to generate a current control signal. The first output voltage and the first reference voltage may be utilized to produce a hysteresis comparison signal by a hysteresis comparator, and the hysteresis comparison signal can be a voltage control signal. A reset signal can be generated after an OR logic operation according to the current control signal and the voltage control signal. The reset signal and a first clock signal can be utilized to generate the first control signal.

Step S802 can also include receiving the first stage input current and the first reference current to generate a first error voltage signal. The first error voltage signal can be compared with a voltage signal that represents the inductor current in the first power stage circuit, to generate the current control signal. The first output voltage can be compared with the first reference voltage to generate voltage control signal. The current control signal can be received as a reset signal, and a second clock signal can be received as a set signal, to generate a second trigger signal. A voltage control signal can be received as a reset signal, and an enable trigger signal can be received as a set signal, to generate a third trigger signal. The second and third trigger signals can be used for generating the first control signal after a logic operation.

Step S803 can also include receiving the output current of the first stage and a threshold current to output second square wave signal that represents the conducting angle information of the SCR. The second square wave signal and a second reference current can be utilized to generate a relatively smooth dimming signal that represents the conducting angle information of the SCR by averaging the second reference current according to the second square wave signal.

Described herein are example dimmable LED drivers and driving methods. However, particular embodiments are amenable to various implementations of the input current control circuit, the dimming signal generating circuit, and output current control circuit. Those skilled in the art will recognize that other circuit structures with the same or similar functions can also be applied in the above-described examples in accordance with embodiments of the present invention.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims (17)

What is claimed is:
1. A dimmable light-emitting diode (LED) driver, comprising:
a) a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge configured to convert an AC voltage to a DC voltage signal;
b) a power stage circuitry configured to receive said DC voltage signal, and to output a constant current to drive an LED load, wherein said power stage circuitry comprises first and second power stage circuits, wherein said first power stage circuit is configured to receive said DC voltage signal, and to generate a first output voltage to said second power stage;
c) an input current control circuit configured to receive an input current of said first power stage circuit and said first output voltage, and to generate a first control signal to control said input current as a pseudo square waveform signal, wherein a high frequency saw-tooth waveform is formed from upper portions of said pseudo square waveform signal during an on time of said SCR;
d) wherein a peak value of said saw-tooth waveform is configured to satisfy a minimum load current requirement of said electronic transformer, and lower portions of said pseudo square waveform signal are maintained as substantially zero; and
e) said second power stage circuit being configured to generate a substantially constant output current to drive said LED load in accordance with said input current.
2. The LED driver of claim 1, wherein said input current control circuit comprises:
a) a current control circuit configured to receive said input current and a first reference current, and to generate a current control signal, wherein said first reference current corresponds to said peak value of said pseudo square waveform signal;
b) a voltage control circuit configured to receive said first output voltage and a first reference voltage, and to generate a voltage control signal; and
c) a logic circuit configured to receive said current control signal and said voltage control signal, and to generate said first control signal.
3. The LED driver of claim 2, wherein:
a) said current control circuit comprises a first comparator configured to generate said current control signal by a comparison of said input current against said first reference current;
b) said voltage control circuit comprises a hysteresis comparator configured to generate said voltage control signal by a comparison of said first output voltage against an upper threshold and a lower threshold based on said first reference voltage; and
c) said logic circuit comprises a first OR-gate and a first flip-flop, wherein said first OR-gate is configured to receive said current control signal and said voltage control signal, and wherein an output of said first OR-gate is coupled to a reset terminal of said first flip-flop, and a set terminal of said first flip-flop is configured to receive a first clock signal.
4. The LED driver of claim 2, wherein:
a) said current control circuit comprises a first transconductance operational amplifier, a first compensation circuit, and a second comparator, wherein said first transconductance operational amplifier is configured to receive said input current and said first reference current, and to generate a first error voltage signal after being compensated by said first compensation circuit;
b) said second comparator is configured to receive said first error voltage signal and a voltage signal that represents an inductor current in said first power stage circuit, and to generate said current control signal;
c) said voltage control circuit comprises a third comparator configured to receive said first output voltage and said first reference voltage, and to generate said voltage control signal;
d) said logic circuit comprises a second flip-flop, a third flip-flop, and a first AND-gate, wherein a reset terminal of said second flip-flop is configured to receive said current control signal, a set terminal of said second flip-flop is configured to receive a second clock signal, and said second flip-flop is configured to output a second trigger signal;
e) a reset terminal of said third flip-flop is configured to receive said voltage control signal, a set terminal of said third flip-flop is configured to receive an enable trigger signal, and said third flip-flop is configured to output a third trigger signal; and
f) said first control signal is output from said first AND-gate based on said second trigger signal and said third trigger signal.
5. The LED driver of claim 4, wherein said current control circuit further comprises a first reference current generating circuit configured to receive a reference current source, and to generate said first reference current, and wherein:
a) said reference current source is configured as said first reference current when said square wave signal of said input current of said first power stage circuit is active; and
b) said first reference current is zero when said square wave signal is inactive.
6. The LED driver of claim 1, further comprising a dimming signal generating circuit configured to generate a dimming signal that represents conducting angle information of said SCR in accordance with time intervals of said saw-tooth waveform of said input current.
7. The LED driver of claim 6, further comprising an output current control circuit configured to receive a current signal of said LED load and said dimming signal, and to generate a second control signal configured to control said second power stage circuit to provide said output current signal for said LED load.
8. The LED driver of claim 1, wherein said first power stage circuit comprises a boost topology.
9. The LED driver of claim 1, wherein said second power stage circuit comprises a buck topology or a boost-buck topology.
10. The LED driver of claim 6, wherein said dimming signal generating circuit comprises:
a) a timer circuit configured to receive said input current and a threshold current, and to generate a second square wave signal that represents conducting angle information of said SCR; and
b) an averaging circuit configured to receive said second square wave signal and a second reference current, and to generate said dimming signal that represents said conducting angle information of said SCR by averaging said second reference current in accordance with said second square wave signal.
11. The LED driver of claim 1, wherein during said on time of said SCR, said first output voltage is indicated as a saw-tooth waveform, and wherein a frequency of said saw-tooth waveform of said first output voltage is less than a frequency of said saw-tooth waveform of said input current.
12. A method of driving a dimmable light-emitting diode (LED), the method comprising:
a) receiving an AC voltage to obtain a DC voltage signal through a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge;
b) generating an input current and a first output voltage using said DC voltage signal, wherein said input current is generated as a square wave signal during an on time of said SCR, and said input current is maintained as substantially zero during an off time of said SCR;
c) generating a dimming signal from said input current; and
d) generating a constant output current signal using said first output voltage, an LED load current signal, and said dimming signal.
13. The method of claim 12, wherein said generating said input current and said first output voltage further comprises:
a) generating a current control signal using said input current and a first reference current, wherein said first reference current corresponds to a peak value of said square wave signal;
b) generating a voltage control signal using said first output voltage and a first reference voltage; and
c) generating a first control signal by performing a logic operation on said current control signal and said voltage control signal.
14. The method of claim 13, further comprising:
a) generating said current control signal by comparing said input current against said first reference current;
b) generating a hysteresis comparison signal by a hysteresis comparator receiving said first output voltage and said first reference voltage, wherein said hysteresis comparison signal is configured as said voltage control signal;
c) generating a reset signal after an OR logic operation based on said current control signal and said voltage control signal; and
d) generating said first control signal using said reset signal and a first clock signal as a set signal.
15. The method of claim 13, further comprising:
a) generating a first error voltage signal using said input current and said first reference current;
b) generating said current control signal by comparing said first error voltage signal against a voltage signal that represents an inductor current in a first power stage circuit;
c) generating said voltage control signal by comparing said first output voltage against said first reference voltage;
d) generating a second trigger signal by using said current control signal as a reset signal and a second clock signal as a set signal;
e) generating a third trigger signal by using said voltage control signal as a reset signal and an enable trigger signal as a set signal; and
f) generating said first control signal after performing a logic operation on said second trigger signal and said third trigger signal.
16. The method of claim 15, further comprising receiving a reference current source, wherein:
a) when said square wave signal that represents said input current is active, said reference current source is configured as said first reference current; and
b) when said square wave signal is inactive, said first reference current is zero.
17. The method of claim 15, wherein said generating said dimming signal further comprises:
a) generating a second square wave signal that represents conducting angle information of said SCR based on said input current and a threshold current; and
b) generating said dimming signal representing said conducting angle information of said SCR by averaging said second reference current according to said second square wave signal.
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US20140021879A1 (en) * 2012-07-18 2014-01-23 Silergy Semiconductor Technology (Hangzhou) Ltd Dimmable led driver and driving method
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US9899947B2 (en) * 2013-10-28 2018-02-20 Jaguar Precision Industry Co., Ltd. Control apparatus for DC inverter electric motor
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TW201410067A (en) 2014-03-01
CN102740571B (en) 2014-10-15
TWI523569B (en) 2016-02-21
US20150382423A1 (en) 2015-12-31
US9161407B2 (en) 2015-10-13
CN102740571A (en) 2012-10-17
US20140021879A1 (en) 2014-01-23

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