US9210438B2 - Logical intra mode naming in HEVC video coding - Google Patents

Logical intra mode naming in HEVC video coding Download PDF

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US9210438B2
US9210438B2 US13/674,646 US201213674646A US9210438B2 US 9210438 B2 US9210438 B2 US 9210438B2 US 201213674646 A US201213674646 A US 201213674646A US 9210438 B2 US9210438 B2 US 9210438B2
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mode
modes
intra
transform
prediction
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US20130188695A1 (en
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Ehsan Maani
Ali Tabatabai
Jun Xu
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Sony Corp
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Priority to PCT/US2012/069023 priority patent/WO2013109359A1/en
Priority to CN201610621392.2A priority patent/CN106101729B/zh
Priority to CN201610620187.4A priority patent/CN106210748B/zh
Priority to CN201310006236.1A priority patent/CN103220511B/zh
Priority to CN201610136245.6A priority patent/CN105791872B/zh
Priority to CN201610620135.7A priority patent/CN106101728B/zh
Priority to CN201610134084.7A priority patent/CN105721878B/zh
Priority to EP13150711.3A priority patent/EP2618575A3/en
Priority to EP19157408.6A priority patent/EP3518546A1/en
Priority to EP16205989.3A priority patent/EP3188484A1/en
Priority to KR1020130003327A priority patent/KR101502674B1/ko
Priority to JP2013019866A priority patent/JP5585946B2/ja
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Priority to JP2014018483A priority patent/JP5861993B2/ja
Priority to JP2014018484A priority patent/JP5811511B2/ja
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Priority to KR1020140135716A priority patent/KR20140135682A/ko
Priority to KR1020140135720A priority patent/KR101952473B1/ko
Priority to KR1020140135722A priority patent/KR101940347B1/ko
Priority to US14/930,861 priority patent/US10567795B2/en
Priority to US14/930,867 priority patent/US10148980B2/en
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Priority to JP2017199247A priority patent/JP2018026870A/ja
Priority to US16/163,269 priority patent/US10623772B2/en
Priority to KR1020180162031A priority patent/KR20180136922A/ko
Priority to JP2018245316A priority patent/JP6702406B2/ja
Priority to KR1020190110505A priority patent/KR20190106962A/ko
Priority to US16/737,164 priority patent/US11012712B2/en
Priority to JP2020041057A priority patent/JP6841361B2/ja
Priority to KR1020200122106A priority patent/KR102204800B1/ko
Priority to KR1020200160667A priority patent/KR102252161B1/ko
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
    • H04N19/11—Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/593—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
    • H04N19/122—Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/46—Embedding additional information in the video signal during the compression process
    • H04N19/463—Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]

Definitions

  • This invention pertains generally to video coding, and more particularly to intra mode naming with high-efficiency video coding devices.
  • HEVC High Efficiency Video Coding
  • Bit stream mode numbers are used to signal the mode to the decoder, and in some implementations, such as HM5.0, may require many look-up tables (e.g., Mode Dependent (MD) coefficient scan, intra smoothing, intra prediction and Mode Dependent (MD) transform) in the programming of the video coding device.
  • Bit stream mode numbers were utilized with advanced video coding (AVC) coding and considered to be sorted in their frequency of occurrences. However, statistics collected on High Efficiency Video Coding (HEVC), do not indicate any bias towards any of the angular directions (not including Planar and DC), while bypass coding is utilized for the remaining modes.
  • AVC advanced video coding
  • HEVC High Efficiency Video Coding
  • Logical intra mode naming in High Efficiency Video Coding (HEVC) of the present invention utilizes logical mode names and numbering for all mode uses and thus replaces the use of bit stream mode numbers.
  • the logical modes have meaningful numbering (naming) for intra modes.
  • a coding unit (CU) may have variable block sizes depending on video content, and may be split into smaller blocks for prediction as Prediction Units (PU) or transform as Transform Units (TU).
  • Prediction units (PU) can be thought of similarly to partitions described in other video coding standards, such as the H.264 standard.
  • a prediction block is formed based on previously encoded and reconstructed blocks adjacent to the current block, the prediction block is configured for being subtracted from the current block prior to encoding.
  • prediction modes for these blocks which define a method of generating a signal from previously encoded blocks, for example including prediction types and directions.
  • Encoders and decoders implemented with high efficiency video coding utilize both logical mode numbers and bit stream mode numbers.
  • intra prediction is performed from samples already decoded in adjacent PUs. Different modes can exist for these PUs, including DC (average), up to 33 angular directions and planar mode.
  • the coding decisions can be simplified by utilizing the same set of logical mode numbers for both prediction and coding for communication to a decoder.
  • the following discusses making these decisions in response to the use of look up tables, it should be appreciated that the simplification is also applicable when the decisions are made using other software mechanisms, such as conditional statements, jump tables, pointer references and so forth.
  • a number of tables related to intra mode coding can be typically eliminated to simplify HEVC encoders and decoders according to the invention (e.g., eliminating tables: g_aucIntraDirToScanIdx, m_aucIntraFilter, g_aucAngIntraModeOrder, g_aucDCTDSTMode_Hor, g_aucDCTDSTMode_Ver in HM5.0).
  • design and implementation of fast encoders can be simplified using these logical intra mode names.
  • MPMs Most Probable Modes
  • MPMs are a mechanism for optimizing the coding process. More particularly, probabilities are estimated for optimal intra direction as the most probable mode (MPM) of its neighboring blocks, because current blocks have a strong correlation with patterns found in neighboring blocks.
  • MPMs including the third MPM, are derived using logical numbering without additional look up tables.
  • the method of determining multiple most probable modes (MPMs) is shared by both encoder and decoder.
  • Logical mode numbers according to the invention are utilized for both performing prediction and coding in the bit stream. These logical mode numbers are numbered, named or sorted based on angle according to the invention. For the sake of simplicity of discussion, the following will describe these as being mode numbers, although one of ordinary skill in the art will appreciate that naming and sorting can be similarly utilized.
  • the logical mode numbering is performed with respect to an arbitrary reference, and these are more beneficially meaningful as they result in an improved design with the removal of several otherwise necessary look-up tables. In addition to many simplifications that result from this type of numbering, simulations indicate a small coding efficiency benefit.
  • adding an additional MPM is very efficient since no additional tables are required.
  • fast intra mode decision algorithms can be simplified. Since modes provide a clear link (association) between numbers (names) and angular directions it is easier to apply various Fast Mode Decision (FMD) algorithms, such as utilizing a hierarchical approach.
  • FMD Fast Mode Decision
  • the method can facilitate or simplify other algorithms, for example deriving neighboring and perpendicular modes to simplify algorithms, such as three MPM algorithms.
  • utilizing an association between logical intra mode names and angular directions allows simplifying decision logic and look-up tables, or elimination of certain look-up tables altogether.
  • the inventive apparatus and method is applicable to video coding devices implemented according to the HEVC standard and similar video systems which would be enhanced by the intra mode naming taught herein.
  • FIG. 1 is a schematic of a video encoder using logical intra mode naming according to an embodiment of the present invention.
  • FIG. 2 is a schematic of a video decoder using logical intra mode naming according to an embodiment of the present invention.
  • FIG. 3 is a map of logical intra mode naming according to an embodiment of the present invention, showing directions for each logical name.
  • FIGS. 4A and 4B are pseudo code instructions of using logical intra mode naming according to an embodiment of the present invention.
  • FIG. 5 is a flow diagram of an encoding tree for intra mode operation according to an embodiment of the present invention.
  • FIG. 6 is a flow diagram of a decoding tree for intra mode operation according to an embodiment of the present invention.
  • FIGS. 7A and 7B is a flow diagram of determining three MPMs according to an embodiment of the present invention.
  • the present invention utilizes a form of logical mode numbers, which are enough to describe the directions and which also can be directly coded into the bit stream instead of using bit stream mode numbers.
  • inventive logical mode numbers throughout the coding system provides multiple advantages, including the following.
  • the logical mode numbering makes it simple to compute adjacent directions.
  • directions are utilized which are adjacent to the neighboring intra mode. Coding system implementations according to these embodiments can be greatly simplified since the adjacent directions are computed with simple arithmetic means, such as just by incrementing or decrementing the neighbouring mode number (depending on PU size).
  • the invention also applies in cases having the same numbers of increments and decrements.
  • FIG. 1 illustrates an example embodiment of a coding apparatus comprising an encoder 10 according to the invention for utilizing logical intra mode naming (LIMN).
  • the invention is implemented in both the entropy encoding block 34 and intra prediction block 26 , shown containing generalized logical intra mode naming (LIMN), but otherwise can rely on conventional video coding which maximizes compatibility with coding systems. It should be appreciated that other blocks of the encoder may be optimized in response to the inventive teachings.
  • the encoder 10 is shown with encoding elements 12 executed by one or more processors 44 .
  • video frame input 14 is shown along with reference frames 16 and frame output 18 .
  • Inter-prediction 20 is depicted with motion estimation (ME) 22 and motion compensation (MC) 24 .
  • Intra prediction 26 is shown which operates with the logical intra mode naming (LIMN) of the invention and switching is depicted between inter prediction and intra prediction.
  • a sum junction 28 is shown with output to a forward transform 30 , operating with Discrete Cosine Transforms (DCT) and/or Discrete Sine Transforms (DST) which are performed based on the predictions to generate transform coefficients of residual data.
  • DCT Discrete Cosine Transforms
  • DST Discrete Sine Transforms
  • Quantization of the transform coefficients is performed at quantization stage 32 , which is followed by entropy encoding 34 , which also utilizes logical intra mode naming (LIMN).
  • Inverse quantization 36 and inverse transform 38 operations are shown coupled to a summing junction 40 followed by a filter 42 , such as a deblocking and/or loop filter and/or sample adaptive offset.
  • the encoder is shown implemented with a processing means 44 , such as comprising at least one processing device (e.g., CPU) 46 and at least one memory 48 for executing programming associated with the encoding.
  • a processing means 44 such as comprising at least one processing device (e.g., CPU) 46 and at least one memory 48 for executing programming associated with the encoding.
  • elements of the present invention can be implemented as programming stored on a media, which can be accessed for execution by a CPU for the encoder 10 and/or decoder 50 .
  • FIG. 2 illustrates an example embodiment 50 of a decoder, shown with process blocks 52 and an associated processing means 76 .
  • the decoder is substantially a subset of the elements contained in encoder 10 of FIG. 1 , operating on reference frames 54 , encoded video signal 56 and outputting video 74 .
  • Decoder 50 utilizes logical intra mode naming (LIMN) during entropy decoding and intra prediction, although the information can also be utilized in other decoding process steps toward increased efficiency.
  • the decoder blocks receive an encoded video signal 56 which is processed through entropy decoder 58 which utilizes the inventive logical intra mode naming (LIMN).
  • LIMN inventive logical intra mode naming
  • inter prediction also utilizes the logical intra mode naming (LIMN).
  • LIMN logical intra mode naming
  • Output from summing junction 64 is received by filter 72 , which can be configured as a loop filter, a deblocking filter, sample adaptive offset, or any combination thereof.
  • the decoder can be implemented with a processing means 76 which comprises at least one processing device 78 and at least one memory 80 for executing programming associated with the decoding.
  • elements of the present invention can be implemented as programming stored on a media, wherein said media can be accessed for execution by processing device (CPU) 78 .
  • elements of the present invention 10 and 50 are implemented for execution by a processing means 44 and 76 , such as in response to programming resident in memory 48 and 80 which is executable on computer processor (CPU) 46 and 78 .
  • elements of the present invention can be implemented as programming stored on a media, wherein said media can be accessed for execution by CPU 46 and 78 .
  • the programming is executable from the memory which is a tangible (physical) computer readable media that is non-transitory in that it does not merely constitute a transitory propagating signal, but is actually capable of retaining programming, such as within any desired form and number of static or dynamic memory devices.
  • These memory devices need not be implemented to maintain data under all conditions (e.g., power fail) to be considered herein as non-transitory media.
  • FIG. 3 illustrates an example embodiment of intra mode numbering utilized according to an embodiment of the present invention, showing a simple monotonic sequence, exemplified with sequential numbering from 2 through 34, whose angles pass through various horizontal, up-right diagonal scan (shown as up-right scan for brevity) and vertical scans.
  • Direction 0 represents Planar, and 1 represents DC, which are not shown in the figure.
  • a function based on a subset of real numbers with real values is called monotonic, if all x and y with x ⁇ y has f(x) ⁇ f(y) for monotonically increasing, or with x ⁇ y for f(x) ⁇ f(y) for monotonically decreasing, thereby preserving the order.
  • Embodiments of the present invention can be implemented with any desired alternative number sequences, in particular monotonic number sequences, without departing from the teachings of the present invention.
  • the index of the scan can be easily derived by calculating the distance of the mode from vertical and horizontal directions. Therefore, the look-up table g_aucIntraDirToScanIdx [MAX_CU_DEPTH][NUM_INTRA_MODE] can be removed.
  • intra mode smoothing the angular offset from both horizontal and vertical can be readily determined in response to numerical displacement, such as utilizing simple comparisons by addition and subtraction from logical intra mode naming.
  • intra mode smoothing is performed in response to the amount of angular difference found between logical intra mode names (which represent angular offsets from horizontal and/or vertical). For example, with the minimum of these numerical displacements compared against a pre-determined value stored in a much smaller look-up table, such as of size 5 rather than 5 ⁇ 36 array in current test model of HEVC (HM5.0). If the minimum numerical displacement (angular difference) is larger than the value of the table for the corresponding block size, then smoothing is applied.
  • a value of 10 is sufficiently large to prevent smoothing from being applied to any intra mode for that block size.
  • the modes for which smoothing is applied are exactly the same as HEVC test model HM 5.0, yet the table size is reduced.
  • mode dependent transforms In coding systems in which mode dependent transforms are based on intra modes, the tables for mode dependent transforms (e.g., Discrete Sine Transforms and Discrete Cosine Transforms (DST and DCT)), can also be removed in a similar fashion, in view of using the logical mode numbers.
  • DST and DCT Discrete Sine Transforms and Discrete Cosine Transforms
  • Horizontal DST is, on the other hand, applied to planar mode and to modes 2 through 25 for horizontal transform.
  • the present invention can be extended to any desired number of Most Probable Modes (MPMs), the following example describing extension to three MPMs.
  • MPMs Most Probable Modes
  • the rationale is to have the number of modes as a structure with 3 MPMs+x, where x is the number of remaining modes.
  • the present invention thus provides a full symmetric approach with no gain in which x is a power of two. So in a 4 ⁇ 4 the value of x is 16, while in others x is equal to 32.
  • the introduction of a third MPM adds no additional complexity or memory-context requirements.
  • the 3 MPMs are derived using simple operations without any look-up tables as seen in Table 1 in which the value of ⁇ is 2 for 4 ⁇ 4 PUs and 1 for the rest of the PU sizes in HM 5.0 and the value can vary in general.
  • Table 1 the value of ⁇ is 2 for 4 ⁇ 4 PUs and 1 for the rest of the PU sizes in HM 5.0 and the value can vary in general.
  • the values of ⁇ and the look up tables can be implemented in various alternative ways without departing from the teachings of the invention. It should be appreciated that the table basically indicates how to set MPMs from neighboring blocks, as seen in more detail in FIG. 4A and FIG. 4B , described in a later section.
  • FIG. 4A and FIG. 4B illustrate MPM derivation according to the invention, shown as generalized pseudo-code.
  • FIG. 4A the decisions are shown for the condition if iLeftIntraDir is equal to iAboveIntraDir, while in FIG. 4B decisions are otherwise shown for when iLeftIntraDir is not equal to AboveIntraDir. These are described in a more readily understood form in FIG. 5 and FIG. 6 , respectively.
  • FIG. 5 illustrates an intra mode encoding tree for the intra prediction mode 90 of the invention.
  • a determination 92 is made if the intra prediction is equal to one of MPMs. If not equal to any of MPMs then a zero is encoded 94 , after which encoding is performed 96 with fixed-length codes for the remaining modes. Otherwise, for MPMs the first bit is encoded 100 as a one.
  • a determination is then made 102 if the mode is MPM 0 . If it is MPM 0 then a zero is encoded 104 . If not MPM 0 then a 1 is encoded 106 , and a determination is made 108 if the mode is MPM 1 .
  • MPM 1 If it is MPM 1 then a zero is encoded 110 , and if not MPM 1 mode then a one is encoded 112 . In any case the bits are inserted in the bit stream for intra mode 98 . Even though it seems preferable to perform checking in the order of MPM 0 , MPM 1 and MPM 2 , one of ordinary skill in the art will appreciate that the sequence of encoding for MPMs, MPM 0 and MPM 1 can be selected in any desired order and/or the selection of ones and zeros in the above example scenario can be reversed, without departing from the teachings of the present invention.
  • programming executable on said processor encodes a first bit in a first state indicating that the intra mode is not equal to any of the MPMs, wherein all encoding is according to fixed-length codes for the remaining modes.
  • the first bit is encoded in a second state, inverse to said first state, to indicate that the intra mode is equal to one of the MPMs, whereby subsequent bits after the first bit indicate if MPM 0 , MPM 1 or MPM 2 is selected.
  • FIG. 6 illustrates an intra mode decoding tree for the invention with a bit stream 130 .
  • the first bit is decoded 132 , and if it is zero, then fixed length codes are to be decoded for the remaining modes at block 134 , and decoded fixed-length code is mapped to intra mode 136 , and intra prediction mode is determined 138 . If the first decoded bit is a one, then at block 140 the next bit is decoded, and if it is zero MPM 0 142 is selected, if one, then block 144 decodes the next bit. If this third bit is a zero, then MPM 1 146 is selected, and if a one, then MPM 2 148 is selected, all of which continue with determining intra prediction mode 138 .
  • FIG. 7A and FIG. 7B illustrates an example embodiment of determining 3 MPMs, as utilized in both the encoder and decoder to assist encoding and decoding of intra prediction modes.
  • decision 150 the value iLeftIntraDir is set to the intra prediction mode of left neighboring PU in block 152 if left neighboring PU is intra coded (mode), otherwise iLeftIntraDir is set to DC in block 154 .
  • decision 156 the value iAboveIntraDir is set to the intra prediction mode of above neighboring PU in block 158 if above neighboring PU is intra coded, otherwise iAboveIntraDir is set to DC in block 160 .
  • iLeftIntraDir and iAboveIntraDir 162 if these are not equal in block 164 , then in block 166 a check is made to see if any one is planar. If not planar then MPM 0 is set to iLeftIntraDir mode, MPM 1 set to iAboveIntraDir mode, and MPM 2 set to Planar mode in block 168 . If any are planar, then block 170 determines if the other is DC. If it is not DC, then in block 172 MPM 0 is set to iLeftIntraDir, MPM 1 is set to iAboveIntraDir, and MPM 2 is set to DC.
  • MPM 0 is set to iLeftIntraDir
  • MPM 1 is set to iAboveIntraDir
  • MPM 2 is set to Vertical.
  • block 176 checks if iLeftIntraDir is angular. For non-angular iLeftIntraDir at block 178 MPM 0 is set to Planar, MPM 1 is set to DC, and MPM 2 is set to Vertical.
  • MPM 0 is set to iLeftIntraDir
  • MPM 1 is set to iLeftIntraDir ⁇
  • MPM 2 is set to iLeftIntraDir+ ⁇ , where the value of ⁇ is 2 for 4 ⁇ 4 PUs and 1 for the rest of the PU sizes in HM5.0.
  • Embodiments of the present invention may be described with reference to flowchart illustrations of methods and systems according to embodiments of the invention, and/or algorithms, formulae, or other computational depictions, which may also be implemented as computer program products.
  • each block or step of a flowchart, and combinations of blocks (and/or steps) in a flowchart, algorithm, formula, or computational depiction can be implemented by various means, such as hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic.
  • any such computer program instructions may be loaded onto a computer, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer or other programmable processing apparatus create means for implementing the functions specified in the block(s) of the flowchart(s).
  • blocks of the flowcharts, algorithms, formulae, or computational depictions support combinations of means for performing the specified functions, combinations of steps for performing the specified functions, and computer program instructions, such as embodied in computer-readable program code logic means, for performing the specified functions. It will also be understood that each block of the flowchart illustrations, algorithms, formulae, or computational depictions and combinations thereof described herein, can be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means.
  • these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the block(s) of the flowchart(s).
  • the computer program instructions may also be loaded onto a computer or other programmable processing apparatus to cause a series of operational steps to be performed on the computer or other programmable processing apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the block(s) of the flowchart(s), algorithm(s), formula(e), or computational depiction(s).
  • An apparatus for encoding and decoding video signals comprising: (a) a video encoder having a computer processor; (b) programming executable on said video encoder computer processor for: (i) selecting intra prediction types and modes in a prediction unit and encoding with logical intra mode naming each said mode having a mode number, wherein each mode number in said logical intra mode naming is associated with an angular direction as a monotonic sequence including representations for DC mode, planar mode, and a plurality of directions, and utilizing said logical intra mode naming for decisions made during intra prediction and entropy encoding; and (ii) deriving a scan index from said intra mode naming by calculating distance of each said mode from vertical and horizontal directions for use in making said decisions during intra prediction and entropy encoding; (c) a video decoder having a computer processor; and (d) programming executable on said video decoder computer processor for receiving from said video encoder most probable modes (MPMs) and intra prediction types and modes, and utilizing
  • said video encoder and said video decoder are configured for high efficiency video coding (HEVC), utilizing coding units (CUs) having variable block sizes depending on video content, which are split into smaller blocks for prediction as Prediction Units (PUs) or transform as Transform Units (TUs).
  • HEVC high efficiency video coding
  • CUs coding units having variable block sizes depending on video content, which are split into smaller blocks for prediction as Prediction Units (PUs) or transform as Transform Units (TUs).
  • An apparatus for video encoding comprising: (a) a video encoder having a computer processor; and (b) programming executable on said computer processor for: (i) selecting intra prediction types and modes of a prediction unit (PU); (ii) encoding said prediction types and modes of the prediction units using logical intra mode naming in which each mode has a mode number that is associated with an angular direction as a monotonic sequence including representations for DC mode, planar mode, and a plurality of directions, and (iii) outputting said logical intra mode naming for use by a decoder in determining prediction types and modes based on said logical intra mode naming
  • said video encoder is a high efficiency video coding (HEVC) encoder, utilizing coding units (CUs) having variable block sizes depending on video content, which are split into smaller blocks for prediction as Prediction Units (PUs) or transform as Transform Units (TUs).
  • HEVC high efficiency video coding
  • look-up tables are selected from the group of tables consisting of intra prediction, intra smoothing, mode dependent coefficient scan and mode dependent transform.
  • any preceding embodiment further comprising programming executable on said computer processor for encoding a first bit in a first state indicating that intra prediction mode is not equal to any MPMs, wherein all encoding is according to fixed-length code for remaining modes; and encoding said first bit in a second state, inverse to said first state, indicating that intra prediction mode is equal to one of MPMs, with subsequent bits after said first bit indicating if MPM 0 , MPM 1 or MPM 2 is selected.
  • a two dimensional 4 ⁇ 4 transform as a one dimensional vertical transform followed by a one dimensional horizontal transform; wherein directional modes have values of 2 through 34; wherein a vertical discrete sine transform (DST) is applied to the planar mode and to modes 11 through 34 for vertical transform, with remaining modes using vertical discrete cosine transform (DCT); and wherein a horizontal DST is applied to planar mode and to modes 2 through 25 for horizontal transform.
  • DST vertical discrete sine transform
  • DCT vertical discrete cosine transform
  • An apparatus for decoding video signals comprising: (a) a decoder having a computer processor configured for decoding video frames; and (b) programming executable on said computer processor for: (i) receiving intra prediction types and modes and most probable modes (MPMs) for prediction units (PUs) utilizing logical intra mode naming (LIMN) from an encoder; (ii) wherein each logical mode number is associated with an angular direction as a monotonic sequence whose numbers include representations for DC mode, planar mode, and a plurality of directions; and (iii) making entropy decoding and intra prediction decisions based on received values encoded with logical intra mode naming (LIMN).
  • MCMs intra prediction types and modes and most probable modes
  • LIMN logical intra mode naming
  • said video decoder is a high efficiency video coding (HEVC) encoder, utilizing coding units (CUs) having variable block sizes depending on video content which are split into smaller blocks for prediction as Prediction Units (PUs) or transform as Transform Units (TUs.
  • HEVC high efficiency video coding
  • a two dimensional 4 ⁇ 4 transform as a one dimensional vertical transform followed by a one dimensional horizontal transform; wherein directional modes have values of 2 through 34; wherein a vertical discrete sine transform (DST) is applied to the planar mode and to modes 11 through 34 for vertical transform, with remaining modes using vertical discrete cosine transform (DCT); and wherein a horizontal DST is applied to planar mode and to modes 2 through 25 for horizontal transform.
  • DST vertical discrete sine transform
  • DCT vertical discrete cosine transform

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US13/674,646 US9210438B2 (en) 2012-01-20 2012-11-12 Logical intra mode naming in HEVC video coding
PCT/US2012/069023 WO2013109359A1 (en) 2012-01-20 2012-12-11 Logical intra mode naming in hevc video coding
CN201610621392.2A CN106101729B (zh) 2012-01-20 2013-01-08 Hevc视频编码中的逻辑帧内模式命名
CN201610620187.4A CN106210748B (zh) 2012-01-20 2013-01-08 Hevc视频编码中的逻辑帧内模式命名
CN201310006236.1A CN103220511B (zh) 2012-01-20 2013-01-08 Hevc视频编码中的逻辑帧内模式命名
CN201610136245.6A CN105791872B (zh) 2012-01-20 2013-01-08 Hevc视频编解码中执行帧内预测的图像处理装置及方法
CN201610620135.7A CN106101728B (zh) 2012-01-20 2013-01-08 Hevc视频编码中的逻辑帧内模式命名
CN201610134084.7A CN105721878B (zh) 2012-01-20 2013-01-08 Hevc视频编解码中执行帧内预测的图像处理装置及方法
EP13150711.3A EP2618575A3 (en) 2012-01-20 2013-01-09 Logical intra mode naming in HEVC video coding
EP19157408.6A EP3518546A1 (en) 2012-01-20 2013-01-09 Logical intra mode naming in hevc video coding
EP16205989.3A EP3188484A1 (en) 2012-01-20 2013-01-09 Logical intra mode naming in hevc video coding
KR1020130003327A KR101502674B1 (ko) 2012-01-20 2013-01-11 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
JP2013019866A JP5585946B2 (ja) 2012-01-20 2013-01-17 Ｈｅｖｃビデオ符号化における論理的イントラモードネーミング
JP2014018483A JP5861993B2 (ja) 2012-01-20 2014-02-03 Ｈｅｖｃビデオ符号化における論理的イントラモードネーミング
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KR1020140135722A KR101940347B1 (ko) 2012-01-20 2014-10-08 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
KR1020140135720A KR101952473B1 (ko) 2012-01-20 2014-10-08 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
KR1020140135716A KR20140135682A (ko) 2012-01-20 2014-10-08 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
US14/930,867 US10148980B2 (en) 2012-01-20 2015-11-03 Logical intra mode naming in HEVC video coding
US14/930,861 US10567795B2 (en) 2012-01-20 2015-11-03 Logical intra mode naming in HEVC video coding
JP2015216616A JP6036964B2 (ja) 2012-01-20 2015-11-04 Ｈｅｖｃビデオ符号化における論理的イントラモードネーミング
JP2016203275A JP6256564B2 (ja) 2012-01-20 2016-10-17 Ｈｅｖｃビデオ符号化における論理的イントラモードネーミング
JP2017199247A JP2018026870A (ja) 2012-01-20 2017-10-13 Ｈｅｖｃビデオ符号化における論理的イントラモードネーミング
US16/163,269 US10623772B2 (en) 2012-01-20 2018-10-17 Logical intra mode naming in HEVC video coding
KR1020180162031A KR20180136922A (ko) 2012-01-20 2018-12-14 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
JP2018245316A JP6702406B2 (ja) 2012-01-20 2018-12-27 Ｈｅｖｃビデオ符号化における論理的イントラモードネーミング
KR1020190110505A KR20190106962A (ko) 2012-01-20 2019-09-06 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
US16/737,164 US11012712B2 (en) 2012-01-20 2020-01-08 Logical intra mode naming in HEVC video coding
JP2020041057A JP6841361B2 (ja) 2012-01-20 2020-03-10 Ｈｅｖｃビデオ符号化における論理的イントラモードネーミング
KR1020200122106A KR102204800B1 (ko) 2012-01-20 2020-09-22 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
KR1020200160667A KR102252161B1 (ko) 2012-01-20 2020-11-26 Hevc 비디오 코딩에서 논리 화상내 모드 명칭부여
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