US8981550B2 - Semiconductor package with alternating thermal interface and adhesive materials and method for manufacturing the same - Google Patents

Semiconductor package with alternating thermal interface and adhesive materials and method for manufacturing the same Download PDF

Info

Publication number
US8981550B2
US8981550B2 US13/725,645 US201213725645A US8981550B2 US 8981550 B2 US8981550 B2 US 8981550B2 US 201213725645 A US201213725645 A US 201213725645A US 8981550 B2 US8981550 B2 US 8981550B2
Authority
US
United States
Prior art keywords
interface material
adhesive
semiconductor chip
semiconductor package
inactive surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US13/725,645
Other versions
US20130214402A1 (en
Inventor
Joon Young Park
Jin Suk Jeong
Kyeong Sool Seong
Seo Won Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amkor Technology Inc
Original Assignee
Amkor Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR10-2012-0015799 priority Critical
Priority to KR1020120015799A priority patent/KR101332866B1/en
Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Assigned to AMKOR TECHNOLOGY, INC. reassignment AMKOR TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JEONG, JIN SUK, LEE, SEO WON, PARK, JOON YOUNG, SEONG, KYEONG SOOL
Publication of US20130214402A1 publication Critical patent/US20130214402A1/en
Application granted granted Critical
Publication of US8981550B2 publication Critical patent/US8981550B2/en
Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. PATENT SECURITY AGREEMENT Assignors: AMKOR TECHNOLOGY, INC.
Assigned to BANK OF AMERICA, N.A., AS AGENT reassignment BANK OF AMERICA, N.A., AS AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY, INC.
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29012Shape in top view
    • H01L2224/29013Shape in top view being rectangular or square
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29012Shape in top view
    • H01L2224/29014Shape in top view being circular or elliptic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/29076Plural core members being mutually engaged together, e.g. through inserts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/29078Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335Material
    • H01L2224/33505Layer connectors having different materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16251Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Abstract

A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid.

Description

TECHNICAL FIELD

The present application relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package, which can improve reliability of heat emitting performance, and a method for manufacturing the same.

BACKGROUND

Semiconductor packages are designed and manufactured in various types according to purposes and uses of the semiconductor packages. The semiconductor package typically includes a substrate, a semiconductor chip mounted on the substrate, a conductive member connecting the semiconductor chip and the substrate, and an input/output terminal for inputting/outputting external signal to/from the substrate.

According to the recent trend towards miniaturization, high integration and high performance of electronic devices, the operating speed of a semiconductor package is greatly increasing while the size thereof is gradually decreasing. According to high integration and high-speed operation of chips, the internal temperature of the semiconductor package unavoidably rises.

If the internal temperature of the semiconductor package rises, thermal stress may be applied to the semiconductor package, resulting in a malfunction of a chip circuit and a reduction in the operating speed.

FIGS. 4A-4D illustrates a conventional semiconductor package manufactured in a structure capable of increasing heat emission efficiency while reducing the size.

That is to say, in the conventional semiconductor package, since a substrate and a semiconductor chip are connected by a conductive wire, a loop height of the conductive wire is created in upward and outward directions of the semiconductor chip, making the semiconductor package bulky. In contrast, as shown in FIG. 4A-4D, metallic bumps 12 are directly formed to a bonding pad formed on one surface of a semiconductor chip 14 by a plating process, and the bumps 12 are directly conductively connected to a conductive pattern of a substrate 10, thereby manufacturing the semiconductor package which can be reduced in size.

In particular, in order to obtain a heat emission effect, the semiconductor package shown in FIGS. 4A-4D includes a heat emitting lid 16 adhered to the substrate 10 at its edge while a central portion of the heat emitting lid 16 is tightly fixed to a top surface of the semiconductor chip 14.

Here, as shown in FIG. 5, an epoxy resin based thermal interface material 18 having high heat transmission efficiency is applied to the top surface of the semiconductor chip 14, and the heat emitting lid 16 is adhered to the top surface of the semiconductor chip 14.

Therefore, some of the heat generated from the semiconductor chip 14 is emitted to the outside through the substrate 10 connected by means of the bumps 12, while most of the heat generated from the semiconductor chip 14 is emitted to the outside through the heat emitting lid 16 directly fixed to the semiconductor chip 14.

However, while the thermal interface material 18 has high heat transmission efficiency, it has a poor adhesion, leading to delamination in which the heat emitting lid 16 is delaminated from the top surface of the semiconductor chip 14.

In particular, the delamination of the heat emitting lid 16 concentrates on corner regions on the top surface of the semiconductor chip 14.

If the heat emitting lid 16 is delaminated from the semiconductor chip 14, the effect of emitting the heat generated from the semiconductor chip 14 may be lowered.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B, 1C, 1D, 1E are cross-sectional views of a semiconductor package during fabrication in accordance with one embodiment;

FIG. 2 is a perspective view of a semiconductor chip, a thermal interface material, and a highly adhesive interface material of the semiconductor package of FIGS. 1D, 1E in accordance with one embodiment;

FIGS. 3A, 3B, 3C, 3D are perspective views illustrating various embodiments for applying an adhesive interface material to a semiconductor package according to various embodiments; and

FIGS. 4A, 4B, 4C, 4D are cross-sectional views of a conventional semiconductor package during fabrication; and

FIG. 5 is a perspective view of a semiconductor chip and thermal interface material of the semiconductor package of FIGS. 4C, 4D in accordance with the prior art.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.

DETAILED DESCRIPTION

One embodiment features that a heat emitting lid stacked on a top surface of a semiconductor chip can be maintained at a tightly adhered state by applying a thermal interface material having high heat transmission efficiency throughout the top surface of the semiconductor chip, and applying a highly adhesive interface material to a partial region of the top surface of the semiconductor chip.

FIGS. 1A, 1B, 1C, 1D, 1E are cross-sectional views of a semiconductor package 100 during fabrication in accordance with one embodiment. Referring to FIG. 1A, metallic bumps 12 are directly formed to a bonding pad formed on the lower surface 13, sometime called the active surface, of a semiconductor chip 14 by a plating process, and the bumps 12 are directly conductively connected to a conductive pattern of a substrate 10, thereby completing the semiconductor package which can be greatly reduced in size. The semiconductor chip 14 further has a top surface 15, sometimes called an inactive surface, opposite the lower surface 13.

Referring to FIG. 1B, a highly adhesive interface material 20 may be applied to edge regions on the top surface of the substrate 10 to which legs of a heat emitting lid will subsequently be attached as described further below.

Referring now to FIGS. 1C, 1D and 2 together, an epoxy resin based thermal interface material (TIM) 18 having high heat transmission efficiency is applied to the top surface 15 of the semiconductor chip 14, and a highly adhesive interface material 40, e.g., an adhesive such as an epoxy, is applied to a partial region, sometimes called an adhesion region, of the top surface 15 of the semiconductor chip 14.

In one embodiment, as illustrated in FIGS. 1C and 1D, the highly adhesive interface material 40 is applied first and the TIM 18 is applied second. However, in another embodiment, the TIM 18 is applied first and the highly adhesive interface material 40 is applied second. In yet another embodiment, the TIM 18 and the highly adhesive interface material 40 are applied simultaneously.

Generally, the portion, sometimes called region or area, of the top surface 15 of the semiconductor chip 14 to which the highly adhesive interface material 40 is applied is called an adhesion region of the top surface 15 of the semiconductor chip 14. In contrast, the portion, sometimes called region or area, of the top surface 15 of the semiconductor chip 14 to which the TIM 18 is applied is called a heat transfer region of the top surface 15 of the semiconductor chip 14.

In one embodiment, the adhesion region to which the highly adhesive interface material 40 is applied is exclusive of the heat transfer region to which the TIM 18 is applied, although there can be some overlap of the regions by overlap of the highly adhesive interface material 40 and the TIM 18. Illustratively, the adhesion region to which the highly adhesive interface material 40 is applied collectively with the heat transfer region to which the TIM 18 is applied form the entire top surface 15 of the semiconductor chip 14.

In one embodiment, the highly adhesive interface material 40 has a greater bonding strength than the TIM 18. However, the TIM 18 has a higher heat transmission efficiency, e.g., a higher heat transfer coefficient, than the highly adhesive interface material 40.

Here, referring now to FIG. 1E, in order to effectively emit the heat generated from the semiconductor chip 14 to the outside, a heat emitting lid 16, including a flat plate 30 and legs 32 integrally formed at four sides of the flat plate 30, is tightly adhered to the semiconductor chip 14.

That is to say, while the flat plate 30 of the heat emitting lid 16 is tightly fixed to the top surface 15 of the semiconductor chip 14, the legs 32 of the heat emitting lid 16, corresponding to the edges of the heat emitting lid 16, are adhered and fixed to the substrate 10.

In more detail, the TIM 18 having high heat transmission efficiency is applied throughout the top surface 15 of the semiconductor chip 14, and the highly adhesive interface material 40 is applied to the partial region of the semiconductor chip 14, thereby welding and fixing the heat emitting lid 16 to the TIM 18 so as to transmit heat while being adhered and fixed to the highly adhesive interface material 40.

Here, a highly adhesive interface material 20, sometimes called a highly adhesive substrate interface material, may be applied to edge regions on the top surface of the substrate 10 to which the legs 32 of the heat emitting lid 16 are attached, thereby fixedly attaching the legs 32 of the heat emitting lid 16 to the substrate 10.

In one embodiment, the highly adhesive interface material 20 and the highly adhesive interface material 40 are the same material, e.g., the same type of adhesive. In another embodiment, instead of the highly adhesive interface material 20, the TIM 18 having high heat transmission efficiency while having rather poor adhesion may be applied to edge regions on the top surface of the substrate 10 to which the legs 32 of the heat emitting lid 16 are attached, thereby fixedly attaching the legs 32 of the heat emitting lid 16 to the substrate 10.

Therefore, some of the heat generated from the semiconductor chip 14 is emitted to the outside through the substrate 10 connected by means of the bumps 12, while most of the heat generated from the semiconductor chip 14 is emitted to the outside through the heat emitting lid 16 by means of the TIM 18.

Here, the adhesive interface material 40 mainly serves to firmly fix the heat emitting lid 16 and has lower heat transmission efficiency than the TIM 18. However, the adhesive interface material 40 also serves to transfer the heat generated from the semiconductor chip 14 to the heat emitting lid 16.

According to various embodiments, as illustrated in FIGS. 3A and 3C, since the heat transmission efficiency of the adhesive interface material 40 is slightly lower than that of the TIM 18, the adhesive interface material 40 is applied only to corner regions on the top surface 15 of the semiconductor chip 14 in a circular (FIG. 3A) or oval shape (FIG. 3C), thereby tightly adhering and supporting the heat emitting lid 16. The corner regions of the top surface 15 are regions of the top surface 15 adjacent to the corners of the top surface 15.

In addition, the TIM 18 mainly serving to emit heat is applied throughout the entire top surface 15 of the semiconductor chip 14 other than the corner regions including the adhesive interface material 40 thereon, thereby facilitating heat emission through the heat emitting lid 16.

According to another embodiment, as illustrated in FIG. 3D, since the heat transmission efficiency of the adhesive interface material 40 is slightly lower than that of the TIM 18, the adhesive interface material 40 is applied only to four edge regions on the top surface 15 of the semiconductor chip 14, thereby tightly adhering and supporting the heat emitting lid 16. In addition, the TIM 18 mainly serving to emit heat is applied throughout the entire top surface 15 of the semiconductor chip 14 other than the four edge regions including the adhesive interface material 40 applied thereon, thereby facilitating heat emission through the heat emitting lid 16. The edge regions are long strip like regions of the top surface 15 adjacent the edges of the top surface 15.

According to still another embodiment, as illustrated in FIG. 3B, since the heat transmission efficiency of the adhesive interface material 40 is slightly lower than that of the TIM 18, the adhesive interface material 40 is simultaneously applied to a central portion, the corner regions and the edge regions on the top surface 15 of the semiconductor chip 14, thereby more tightly adhering and supporting the heat emitting lid 16. In addition, the TIM 18 mainly serving to emit heat is applied throughout the entire surface of the semiconductor chip 14 other than the central portion, the corner regions and the edge regions including the adhesive interface material 40, thereby facilitating heat emission through the heat emitting lid 16. The central portion of the top surface 15 of the semiconductor chip 14 is the region at the center of the top surface 15 of the semiconductor chip 14.

As described above, the adhesive interface material 40 is applied in a circular, oval or polygonal shape to the top surface 15 of the semiconductor chip 14 in a dotted manner together with the TIM 18. While the heat emitting lid 16 is adhered to the semiconductor chip 14, the dotted adhesive interface material 40 spreads, thereby easily adhering the adhesive interface material 40 to the heat emitting lid 16.

As described above, the TIM 18 having high heat transmission efficiency is applied to the top surface 15 of the semiconductor chip 14 mounted on the substrate 10 while applying the highly adhesive interface material 40 to a partial region of the top surface 15 of the semiconductor chip 14, thereby firmly adhering and fixing the heat emitting lid 16 stacked on the top surface 15 of the semiconductor chip 14. Accordingly, it is possible to prevent the heat emitting lid 16 from being delaminated from the semiconductor chip 14, thereby improving the reliability of heat emission performance.

This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.

Claims (22)

What is claimed is:
1. A semiconductor package comprising:
a semiconductor chip comprising an inactive surface;
an adhesive interface material adhered to an adhesive region of the inactive surface;
a thermal interface material adhered to a heat transfer region of the inactive surface; and
a heat emitting lid adhered to the inactive surface by the adhesive interface material and the thermal interface material, wherein the adhesive interface material has a greater bonding strength than the thermal interface material.
2. The semiconductor package of claim 1 wherein the thermal interface material has a higher heat transmission efficiency than the adhesive interface material.
3. The semiconductor package of claim 1 wherein the adhesive region and the heat transfer region form the entire inactive surface.
4. The semiconductor package of claim 1 further comprising:
a substrate; and
conductive bumps coupling an active surface of the semiconductor chip to the substrate.
5. The semiconductor package of claim 4 wherein the heat emitting lid comprises:
a flat plate adhered to the inactive surface; and
legs adhered to the substrate.
6. The semiconductor package of claim 5 comprising an adhesive substrate interface material adhering the legs to the substrate.
7. The semiconductor package of claim 6 wherein the adhesive substrate interface material and the adhesive interface material are the same type of material.
8. The semiconductor package of claim 1, wherein the adhesive region comprises corner regions on the inactive surface of the semiconductor chip.
9. The semiconductor package of claim 1, wherein the adhesive region comprises edge regions on the inactive surface of the semiconductor chip.
10. The semiconductor package of claim 1, wherein the adhesive region comprises a central portion, corner regions and edge regions on the inactive surface of the semiconductor chip.
11. The semiconductor package of claim 1, wherein the adhesive interface material is applied in a shape comprising one or more of the following: a circle, an oval and a polygon with rounded edges.
12. A semiconductor package comprising:
a substrate;
a semiconductor chip;
bumps conductively attaching the semiconductor chip to the substrate;
a heat emitting lid attached to an inactive surface of the semiconductor chip and edge regions of a top surface of the substrate, wherein the heat emitting lid is adhered and fixed to a highly adhesive interface material while also being adhered to a thermal interface material having a high heat transmission efficiency throughout the inactive surface of the semiconductor chip, the highly adhesive interface material being applied to an adhesive region of the inactive surface of the semiconductor chip and the thermal interface material being applied at a heat transfer region of the inactive surface of the semiconductor chip different from the adhesive region.
13. The semiconductor package of claim 12, wherein the adhesive interface material is applied to corner regions on the inactive surface of the semiconductor chip.
14. The semiconductor package of claim 12, wherein the adhesive interface material is applied to edge regions on the inactive surface of the semiconductor chip.
15. The semiconductor package of claim 12, wherein the adhesive interface material is applied to a central portion, corner regions and edge regions on the inactive surface of the semiconductor chip.
16. The semiconductor package of claim 12, wherein the adhesive interface material is applied in a shape comprising one or more of the following: a circle, an oval and a polygon with rounded edges.
17. The semiconductor package of claim 12, wherein the heat emitting lid is adhered to the inactive surface of the semiconductor chip and to the edge regions of the top surface of the substrate using a same adhesive.
18. The semiconductor package of claim 12, wherein the adhesive interface material has a greater bonding strength than the thermal interface material, and the thermal interface material has a higher heat transmission efficiency than the adhesive interface material.
19. A semiconductor package comprising:
a substrate;
a semiconductor chip comprising an active surface and an inactive surface;
bumps conductively attaching the active surface of the semiconductor chip to the substrate;
a heat emitting lid attached to the inactive surface of the semiconductor chip using both an epoxy-based adhesive material and an epoxy resin-based thermal interface material.
20. A method for a semiconductor package, the method comprising:
providing a semiconductor package, the package comprising:
a semiconductor chip comprising an inactive surface;
an adhesive interface material adhered to an adhesive region of the inactive surface;
a thermal interface material adhered to a heat transfer region of the inactive surface; and
a heat emitting lid adhered to the inactive surface by the adhesive interface material and the thermal interface material, wherein the adhesive interface material has a greater bonding strength than the thermal interface material.
21. The method of claim 20 wherein the thermal interface material has a higher heat transmission efficiency than the adhesive interface material.
22. The method of claim 20 wherein the adhesive region and the heat transfer region form the entire inactive surface.
US13/725,645 2012-02-16 2012-12-21 Semiconductor package with alternating thermal interface and adhesive materials and method for manufacturing the same Active US8981550B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR10-2012-0015799 2012-02-16
KR1020120015799A KR101332866B1 (en) 2012-02-16 2012-02-16 Semiconductor package and method for manufacturing the same

Publications (2)

Publication Number Publication Date
US20130214402A1 US20130214402A1 (en) 2013-08-22
US8981550B2 true US8981550B2 (en) 2015-03-17

Family

ID=48981651

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/725,645 Active US8981550B2 (en) 2012-02-16 2012-12-21 Semiconductor package with alternating thermal interface and adhesive materials and method for manufacturing the same

Country Status (2)

Country Link
US (1) US8981550B2 (en)
KR (1) KR101332866B1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9391043B2 (en) 2012-11-20 2016-07-12 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9543242B1 (en) 2013-01-29 2017-01-10 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US9704842B2 (en) 2013-11-04 2017-07-11 Amkor Technology, Inc. Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9831190B2 (en) * 2014-01-09 2017-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package with warpage control structure
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9041192B2 (en) * 2012-08-29 2015-05-26 Broadcom Corporation Hybrid thermal interface material for IC packages with integrated heat spreader
JP6261352B2 (en) * 2014-01-23 2018-01-17 新光電気工業株式会社 Carbon nanotube sheet, semiconductor device, method of manufacturing carbon nanotube sheet, and method of manufacturing semiconductor device
FR3023975A1 (en) * 2014-07-18 2016-01-22 Thales Sa Thermal interface device with microporous seal capable of preventing migration of thermal grease
US9728510B2 (en) 2015-04-10 2017-08-08 Analog Devices, Inc. Cavity package with composite substrate

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051888A (en) * 1997-04-07 2000-04-18 Texas Instruments Incorporated Semiconductor package and method for increased thermal dissipation of flip-chip semiconductor package
US6294408B1 (en) * 1999-01-06 2001-09-25 International Business Machines Corporation Method for controlling thermal interface gap distance
US6486554B2 (en) * 2001-03-30 2002-11-26 International Business Machines Corporation Molded body for PBGA and chip-scale packages
US20040036183A1 (en) * 2001-11-03 2004-02-26 Samsung Electronics Co., Ltd. Semiconductor package having DAM and method for fabricating the same
US20050056928A1 (en) * 2001-10-05 2005-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US20050062154A1 (en) * 2003-09-18 2005-03-24 International Business Machines Corporation Electronically grounded heat spreader
US6943436B2 (en) * 2003-01-15 2005-09-13 Sun Microsystems, Inc. EMI heatspreader/lid for integrated circuit packages
US6967403B2 (en) * 2003-06-18 2005-11-22 Advanced Semiconductor Engineering, Inc. Package structure with a heat spreader and manufacturing method thereof
US7112882B2 (en) * 2004-08-25 2006-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and methods for heat dissipation of semiconductor integrated circuits
US7119432B2 (en) * 2004-04-07 2006-10-10 Lsi Logic Corporation Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
US20100020503A1 (en) * 2008-07-22 2010-01-28 International Business Machines Corporation Lid edge capping load
US20100181665A1 (en) * 2009-01-22 2010-07-22 International Business Machines Corporation System and Method of Achieving Mechanical and Thermal Stability in a Multi-Chip Package
US20100208432A1 (en) * 2007-09-11 2010-08-19 Dorab Bhagwagar Thermal Interface Material, Electronic Device Containing the Thermal Interface Material, and Methods for Their Preparation and Use
US7781883B2 (en) * 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US7928562B2 (en) * 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
US20120153453A1 (en) * 2010-12-17 2012-06-21 Oracle America, Inc. Metallic thermal joint for high power density chips
US20130052775A1 (en) * 2011-08-23 2013-02-28 Samsung Electronics Co., Ltd. Semiconductor packages and methods of forming the same
US20130241039A1 (en) * 2011-05-03 2013-09-19 Stats Chippac, Ltd. Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material
US20130309814A1 (en) * 2006-04-21 2013-11-21 Seah Sun Too Lid attach process
US20130320517A1 (en) * 2012-06-05 2013-12-05 Texas Instruments Incorporated Lidded integrated circuit package
US20140061893A1 (en) * 2012-08-29 2014-03-06 Broadcom Corporation Hybrid thermal interface material for ic packages with integrated heat spreader

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970005712B1 (en) * 1994-01-11 1997-04-19 김광호 High heat sink package
KR200179419Y1 (en) 1997-06-30 2000-05-01 김영환 Semiconductor package
KR100411206B1 (en) * 2001-02-19 2003-12-18 삼성전자주식회사 Semiconductor package
KR100571273B1 (en) 2003-07-25 2006-04-13 동부아남반도체 주식회사 The semiconductor package and a method of manufacturing the same

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051888A (en) * 1997-04-07 2000-04-18 Texas Instruments Incorporated Semiconductor package and method for increased thermal dissipation of flip-chip semiconductor package
US6294408B1 (en) * 1999-01-06 2001-09-25 International Business Machines Corporation Method for controlling thermal interface gap distance
US6486554B2 (en) * 2001-03-30 2002-11-26 International Business Machines Corporation Molded body for PBGA and chip-scale packages
US20050056928A1 (en) * 2001-10-05 2005-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US20040036183A1 (en) * 2001-11-03 2004-02-26 Samsung Electronics Co., Ltd. Semiconductor package having DAM and method for fabricating the same
US6943436B2 (en) * 2003-01-15 2005-09-13 Sun Microsystems, Inc. EMI heatspreader/lid for integrated circuit packages
US6967403B2 (en) * 2003-06-18 2005-11-22 Advanced Semiconductor Engineering, Inc. Package structure with a heat spreader and manufacturing method thereof
US20050062154A1 (en) * 2003-09-18 2005-03-24 International Business Machines Corporation Electronically grounded heat spreader
US7119432B2 (en) * 2004-04-07 2006-10-10 Lsi Logic Corporation Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
US7112882B2 (en) * 2004-08-25 2006-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and methods for heat dissipation of semiconductor integrated circuits
US20130309814A1 (en) * 2006-04-21 2013-11-21 Seah Sun Too Lid attach process
US20100208432A1 (en) * 2007-09-11 2010-08-19 Dorab Bhagwagar Thermal Interface Material, Electronic Device Containing the Thermal Interface Material, and Methods for Their Preparation and Use
US7928562B2 (en) * 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
US20100020503A1 (en) * 2008-07-22 2010-01-28 International Business Machines Corporation Lid edge capping load
US7781883B2 (en) * 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US20100181665A1 (en) * 2009-01-22 2010-07-22 International Business Machines Corporation System and Method of Achieving Mechanical and Thermal Stability in a Multi-Chip Package
US20120153453A1 (en) * 2010-12-17 2012-06-21 Oracle America, Inc. Metallic thermal joint for high power density chips
US20130241039A1 (en) * 2011-05-03 2013-09-19 Stats Chippac, Ltd. Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material
US20130052775A1 (en) * 2011-08-23 2013-02-28 Samsung Electronics Co., Ltd. Semiconductor packages and methods of forming the same
US20130320517A1 (en) * 2012-06-05 2013-12-05 Texas Instruments Incorporated Lidded integrated circuit package
US20140061893A1 (en) * 2012-08-29 2014-03-06 Broadcom Corporation Hybrid thermal interface material for ic packages with integrated heat spreader

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US10347562B1 (en) 2011-02-18 2019-07-09 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9391043B2 (en) 2012-11-20 2016-07-12 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9728514B2 (en) 2012-11-20 2017-08-08 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9543242B1 (en) 2013-01-29 2017-01-10 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US9852976B2 (en) 2013-01-29 2017-12-26 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US9704842B2 (en) 2013-11-04 2017-07-11 Amkor Technology, Inc. Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package
US10192816B2 (en) 2013-11-19 2019-01-29 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US9831190B2 (en) * 2014-01-09 2017-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package with warpage control structure
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10490716B2 (en) 2016-09-06 2019-11-26 Amkor Technology, Inc. Semiconductor device with optically-transmissive layer and manufacturing method thereof

Also Published As

Publication number Publication date
US20130214402A1 (en) 2013-08-22
KR20130094502A (en) 2013-08-26
KR101332866B1 (en) 2013-11-22

Similar Documents

Publication Publication Date Title
US6882041B1 (en) Thermally enhanced metal capped BGA package
US7282392B2 (en) Method of fabricating a stacked die in die BGA package
US6909168B2 (en) Resin encapsulation semiconductor device utilizing grooved leads and die pad
US20080224285A1 (en) Power module having stacked flip-chip and method of fabricating the power module
US7279789B2 (en) Thermally enhanced three-dimensional package and method for manufacturing the same
US7723839B2 (en) Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
CN203456452U (en) Integrated circuit packaging piece
US8735222B2 (en) Semiconductor device and method of manufacturing the same
US6846704B2 (en) Semiconductor package and method for manufacturing the same
US6720649B2 (en) Semiconductor package with heat dissipating structure
US6818982B2 (en) Heat dissipation type semiconductor package and method of fabricating the same
JP2006528846A (en) Integrated heat spreader lid
US20070096272A1 (en) Light emitting diode package
US6650006B2 (en) Semiconductor package with stacked chips
US20040178494A1 (en) Semiconductor package with heat sink
KR20030018204A (en) Multi chip package having spacer
WO2006035664A1 (en) Semiconductor light emitting element, manufacturing method and mounting method of the same and light emitting device
US7944038B2 (en) Semiconductor package having an antenna on the molding compound thereof
US6980438B2 (en) Semiconductor package with heat dissipating structure
JP4633971B2 (en) Semiconductor device
TWI469283B (en) Package structure and package process
KR20020078931A (en) Carrier frame for semiconductor package and semiconductor package using it and its manufacturing method
US7719094B2 (en) Semiconductor package and manufacturing method thereof
US8759157B2 (en) Heat dissipation methods and structures for semiconductor device
US8179678B2 (en) Electronic component module

Legal Events

Date Code Title Description
AS Assignment

Owner name: AMKOR TECHNOLOGY, INC., ARIZONA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARK, JOON YOUNG;JEONG, JIN SUK;SEONG, KYEONG SOOL;AND OTHERS;SIGNING DATES FROM 20121220 TO 20121221;REEL/FRAME:029537/0749

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: BANK OF AMERICA, N.A., TEXAS

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AMKOR TECHNOLOGY, INC.;REEL/FRAME:035613/0592

Effective date: 20150409

AS Assignment

Owner name: BANK OF AMERICA, N.A., AS AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:AMKOR TECHNOLOGY, INC.;REEL/FRAME:046683/0139

Effective date: 20180713

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4