US8377749B1 - Integrated circuit transmission line - Google Patents
Integrated circuit transmission line Download PDFInfo
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- US8377749B1 US8377749B1 US12/560,187 US56018709A US8377749B1 US 8377749 B1 US8377749 B1 US 8377749B1 US 56018709 A US56018709 A US 56018709A US 8377749 B1 US8377749 B1 US 8377749B1
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 41
- 239000011248 coating agent Substances 0.000 claims abstract description 84
- 238000000576 coating method Methods 0.000 claims abstract description 84
- 239000012212 insulator Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000012799 electrically-conductive coating Substances 0.000 claims abstract description 18
- 229920000052 poly(p-xylylene) Polymers 0.000 claims abstract description 15
- 230000001419 dependent effect Effects 0.000 claims abstract description 8
- 239000004593 Epoxy Substances 0.000 claims description 17
- 239000003973 paint Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000007598 dipping method Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000004020 conductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010952 in-situ formation Methods 0.000 description 1
- 239000004816 latex Substances 0.000 description 1
- 229920000126 latex Polymers 0.000 description 1
- -1 moisture Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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Definitions
- This invention generally relates to integrated circuit UC) fabrication and, more particularly, to a method for the in-situ formation of transmission lines from conventional wire connections.
- a coaxial type transmission line is comprised of a center conductor with a known diameter, a surrounding insulator, with a known dielectric constant and outer diameter (thickness), and a shield. The signal is carried via the center conductor and the shield is connected to a reference voltage, such as ground.
- a transmission line can be thought of as a series inductor and resistor, with a shunt capacitor.
- IC devices are formed from a die of an active semiconductor device.
- the die can be mounted in a hybrid circuit, printed circuit board (PCB), or a package.
- PCB printed circuit board
- the die may be covered by a passivation layer.
- a package is more typically used since it also dissipates heat and provides a lead system for electrical connections.
- There are many different types of packages including through-hole, surface mount device (SMD) dual/quad, and SMD area array packages. While the package provides protection, it makes access to the die difficult.
- SMD surface mount device
- FIGS. 1A and 1B are perspective views of a dual in-line package (DIP) and an IC die without a package, respectively (prior art). It is common for a package body or lead frame 100 to have a die attach area 102 . The die 106 has electrical contact pads on its top surface. Inner leads 108 connect pads on the die top surface to outer leads or lead frames 110 . Once the inner leads are bonded to the lead frames, the package is sealed with ceramic, in a metal can, or in a polyimide. Epoxy resins are also a common choice.
- DIP packages are relatively easy to manufacture and easy to integrate into circuit boards. While transmission lines can be fabricated in the IC die, and in the circuit board to which the IC is eventually integrated, the wire bonds formed in the IC, from the die to the chip carrier lead frames are simple wires that do not have a controlled impedance, and which promote cross-talk. Thus, it is becoming increasing impractical to use DIP and other IC packages that rely upon wire bonding, to carry high-speed signals.
- the IC device shown in FIG. 1B surface mounts to a PCB socket.
- the input and output contacts of an IC chip are generally disposed in grid-like patterns that substantially cover a surface of the device or in elongated rows which may extend parallel to and adjacent each edge of the device's front surface, or in the center of the front surface.
- a surface mounted chip carrier has terminals formed as plated or etched metallic structures on the dielectric. These terminals typically are connected to the contacts of the chip itself by features such as thin traces extending along the chip carrier itself and by fine leads or wires extending between the contacts of the chip and the terminals or traces. These wires are much shorter than the wires bonds used in DIP packages.
- the package In a surface mounting operation, the package is placed onto a circuit board so that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads. The package can be permanently bonded in place by heating the assembly so as to melt or “reflow” the solder or otherwise activate the bonding material.
- An IC that is designed to be surface mounted has pads, or flat conductive discs, on its packaging.
- Many packages include solder masses in the form of solder balls, typically about 1.0 mm and about 0.8 mm (40 mils and 30 mils) in pitch, and 0.4 to 0.5 mm in diameter, attached to the terminals of the package.
- a package having an array of solder balls projecting from its bottom surface is commonly referred to as a ball grid array or “BGA” package.
- BGA ball grid array
- LGA packages are secured to the substrate by thin layers or lands (pads) formed from solder.
- the pads of an LGA require a socket containing springs or some other type of conductive trace to connect the device to the PCB.
- BGA contact ICs are cost effective for ICs having more than 100 pads.
- wire bonding is more cost effective for smaller pin count packages, the relatively long lengths of the wire bonds are not shielded, and do not have a controlled impedance, which are required in many high frequency applications.
- IC dies could be connected to chip carriers with transmission lines instead of wire bonds. It would be advantageous if the above-mentioned ICs could be initially fabricated with conventional wires bonds that can be converted in-situ to transmission lines.
- a process is described herein that uniformly coats the wires, and anything else exposed, with a selected thickness of insulator that is suitable for use as the dielectric element in a coaxial cable configuration.
- the insulator is then blanket coated with a metallic later to complete the coaxial configuration.
- the wired bonded units are placed in a parylene coating system (vacuum chamber) and parylene is allowed to coat all exposed surfaces to a controlled thickness.
- the units are then removed from the chamber and coated with a metal layer common to ground. This metal layer may be a metal filled epoxy overmold.
- a method for fabricating a transmission line between electrical circuits.
- the method initially provides a first electrical circuit with a signal interface and a reference voltage interface, and a second electrical circuit with a signal interface and a reference voltage interface.
- the first circuit signal interface is connected to the second circuit signal interface with a metal wire.
- An insulator coating e.g., poly-para-xylylene
- an electrically conductive coating is formed, encapsulating the insulator coating.
- the conductive coating is connected to at least one of the first and second circuit reference voltage interfaces.
- the first circuit signal interface connection to the second circuit signal interface is a transmission line formed from the combination of the wire, insulator coating, and conductive coating.
- the transmission line has a frequency-dependent characteristic impedance responsive to the wire diameter, insulator thickness, and dielectric constant.
- FIGS. 1A and 1B are perspective views of a dual in-line package (DIP) and an IC die without a package, respectively (prior art).
- DIP dual in-line package
- FIGS. 2A and 2B are partial cross-sectional and plan views, respectively, of an IC with transmission line wire bonds between a die and a chip carrier.
- FIG. 3 is a partial cross-sectional view of the shielded connector of FIG. 2 .
- FIG. 4 is a flowchart illustrating a method for fabricating a transmission line between electrical circuits.
- FIG. 5 is a flowchart illustrating a method for fabricating transmission line wire bonds between an IC die and a chip carrier.
- FIGS. 2A and 2B are partial cross-sectional and plan views, respectively, of an IC with transmission line wire bonds between a die and a chip carrier.
- the IC 200 comprises an electrical circuit die 202 with a plurality of signal interfaces 204 and at least one reference voltage interface 206 .
- a chip carrier 208 is also shown with a plurality of signal lead frames 210 .
- at least one lead frames is for reference voltage 212 .
- Shielded connectors 214 are formed between the die signal interfaces 204 and the chip carrier signal lead frames 210 .
- FIG. 3 is a partial cross-sectional view of the shielded connector of FIG. 2 .
- Each shielded connector 214 includes a metal wire 216 with one end bonded to a die signal interface, and the other end bonded to a signal lead frame.
- An insulator coating 218 encapsulates the wire 216
- an electrically conductive coating 220 encapsulates the insulator coating 218 .
- the conductive coating 220 isotropically covers unmasked portions of the die 202 and chip carrier 208 , see FIGS. 2A and 2B .
- the insulator coating 220 is poly-para-xylylene.
- the conductive coating 220 is connected to the die reference voltage interface 206 .
- the conductive coating may be connected to the lead frame reference voltage 212 , or both reference voltage interfaces 212 and 206 .
- the conductive coating 200 conformally coats the die and chip carrier.
- the conductive coating is connected to the reference voltage interfaces if these areas are masked during insulator deposition.
- a reference voltage is a ground or a dc power supply voltage.
- a variety of conventional IC processes are known that are capable of isotropically depositing conductive materials such as copper, silver, or gold. Further, a carbon or conductive epoxy paint may be used. In one aspect not shown, the conductive coating is overmolded bulk conductive epoxy.
- the insulator coating 218 has a dielectric constant. Like the conductive coating 220 , the insulator coating 218 may also isotropically covers unmasked portions of the die 202 and chip carrier 208 , as well as the each wire 216 .
- the insulator has a thickness or outer diameter 222 .
- the combination of each wire bond 216 , insulator coating 218 , and conductive coating 220 forms a transmission line having a frequency-dependent characteristic impedance responsive to the wire diameter 224 , insulator thickness 222 , and dielectric constant.
- Poly-para-xylylene is a well-known electronics industry conformal coating that is conventionally used to protect circuitry from ambient air, moisture, chemicals, or ultraviolet (UV) radiation.
- wire bonded units are placed in a vacuum chamber.
- the surfaces not to be coated are covered with latex, or some other masking material.
- the masking is removed and the units are taken from the chamber.
- Poly-para-xylylene has been mentioned as an easy to use material, common to many conventional IC fabrication processes.
- the transmission lines can be made with other insulator materials known in the art that can be isotropically deposited.
- a conductive coating is applied over the poly-para-xylylene.
- the conductive coating connects to the areas that were previously masked, which may be one of more reference voltage (ground) interfaces.
- the units continue through the normal packing process steps.
- the transmission lines can be encapsulated with conductive epoxy, meaning all sides of the package are covered with epoxy. When overmolded, just the top side of the die and wire get covered, and not the bottom side of package.
- overmold is a bulk volume and not a thin layer.
- a thin layer of conductive material overlies the poly-para-xylylene, and is then covered with a non-conductive overmold.
- the overmold is conductive and serves both purposes.
- Silver filled epoxy is an example of a conductive overmold.
- FIG. 4 is a flowchart illustrating a method for fabricating a transmission line between electrical circuits.
- the method may be understood as the in-situ conversion of a wire connection, or wire bond, into a coax transmission line.
- the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence.
- the method starts at Step 400 .
- Step 402 provides a first electrical circuit with a signal interface, and a second electrical circuit with a signal interface.
- Step 403 a connects the first circuit signal interface to the second circuit signal interface with a metal wire.
- Step 402 provides a first electrical circuit with a signal interface connected with a wire to a second electrical circuit with a signal interface.
- Step 404 forms an insulator coating encapsulating the wire.
- the insulator is poly-para-xylylene.
- Step 406 forms an electrically conductive coating encapsulating the insulator coating.
- the conductive coating can be carbon paint, conductive epoxy paint, copper, silver, gold, or overmolded bulk conductive epoxy.
- the conductive coating may be formed using a process such as sputtering, CVD, evaporation, clipping, or electroplating a seed layer.
- Step 402 provides first and second electrical circuits, each having at least one reference voltage interface, and Step 406 connects the conductive coating to at least one of the first and second circuit reference voltage interfaces.
- Step 403 b may mask the reference voltage interface(s), and subsequent to forming the insulator coating and prior to forming the conductive coating, Step 405 removes the reference voltage interface masks.
- Step 402 provides a wire connection having a diameter
- Step 404 forms the insulator coating having a dielectric constant and a thickness. If Step 406 connects the conductive coating to at least one the reference voltage interfaces of the first and second circuits, then the method comprises a further step.
- Step 408 forms a transmission line from the combination of the wire, insulator coating, and conductive coating. The transmission line has a frequency-dependent characteristic impedance responsive to the wire diameter, insulator thickness, and dielectric constant.
- FIG. 5 is a flowchart illustrating a method for fabricating transmission line wire bonds between an IC die and a chip carrier.
- the method begins at Step 500 .
- Step 502 provides an IC die with a plurality of signal interfaces wire bonded to a plurality of chip carrier signal lead frames.
- the method includes an additional step for forming the wire bonds.
- Step 504 forms an insulator coating (e.g., poly-para-xylylene) encapsulating each wire bond.
- Step 506 forms an electrically conductive coating encapsulating each insulator coating.
- the conductive coating can be carbon paint, conductive epoxy paint, copper, silver, gold, or overmolded bulk conductive epoxy.
- the conductive coating may be formed using a process such as sputtering, CVD, evaporation, dipping, or electroplating a seed layer.
- Step 502 provides an IC die with a reference voltage interface and a chip carrier with a reference voltage lead frame interface
- Step 506 connects the conductive coating to at least one of the die or lead frame reference voltage interfaces.
- Step 503 prior to forming the insulator coating, Step 503 masks the die reference voltage interface and a reference voltage lead frame contact point.
- Step 505 removes the reference voltage interface masks.
- Step 502 provides wire bonds having a diameter
- Step 504 forms insulators having a thickness (outer diameter) and a dielectric constant. If Step 506 connects the conductive coating to at least one of the die reference voltage interface or the reference voltage lead frame, the method comprises a further step.
- Step 508 forms a transmission line from the combination of each wire bond, insulator coating, and conductive coating. Each transmission line has a frequency-dependent characteristic impedance responsive to the wire diameter, insulator thickness, and dielectric constant.
- a method for the in-situ conversion of a wire connection, to a transmission line, has been provided, along with an IC die with transmission line connections to a chip carrier. Examples of materials and specific fabrication processes have been given to illustrate the invention. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.
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Abstract
Description
Claims (14)
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US12/560,187 US8377749B1 (en) | 2009-09-15 | 2009-09-15 | Integrated circuit transmission line |
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US12/560,187 US8377749B1 (en) | 2009-09-15 | 2009-09-15 | Integrated circuit transmission line |
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WO2019241737A1 (en) * | 2018-06-14 | 2019-12-19 | Caprice Gray Haley | Coaxial wire |
CN115290214A (en) * | 2022-07-04 | 2022-11-04 | 上海集迦电子科技有限公司 | In-situ wired wafer film temperature sensor |
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