JP2016524338A - Die package with low electromagnetic interference wiring - Google Patents

Die package with low electromagnetic interference wiring Download PDF

Info

Publication number
JP2016524338A
JP2016524338A JP2016522338A JP2016522338A JP2016524338A JP 2016524338 A JP2016524338 A JP 2016524338A JP 2016522338 A JP2016522338 A JP 2016522338A JP 2016522338 A JP2016522338 A JP 2016522338A JP 2016524338 A JP2016524338 A JP 2016524338A
Authority
JP
Japan
Prior art keywords
die
lead
metal core
dielectric
die package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016522338A
Other languages
Japanese (ja)
Other versions
JP6285021B2 (en
Inventor
エス. ケーヒル シーン
エス. ケーヒル シーン
エー. サンフアン エリック
エー. サンフアン エリック
Original Assignee
ローゼンベルガー ホーフフレクベンツテクニーク ゲーエムベーハー ウント ツェーオー カーゲー
ローゼンベルガー ホーフフレクベンツテクニーク ゲーエムベーハー ウント ツェーオー カーゲー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローゼンベルガー ホーフフレクベンツテクニーク ゲーエムベーハー ウント ツェーオー カーゲー, ローゼンベルガー ホーフフレクベンツテクニーク ゲーエムベーハー ウント ツェーオー カーゲー filed Critical ローゼンベルガー ホーフフレクベンツテクニーク ゲーエムベーハー ウント ツェーオー カーゲー
Publication of JP2016524338A publication Critical patent/JP2016524338A/en
Application granted granted Critical
Publication of JP6285021B2 publication Critical patent/JP6285021B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6611Wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6638Differential pair signal lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/4556Disposition, e.g. coating on a part of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/4569Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801Structure
    • H01L2224/48011Length
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/4917Crossed wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8593Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85931Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by chemical means, e.g. etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8593Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85935Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by heating means, e.g. reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8593Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85935Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by heating means, e.g. reflowing
    • H01L2224/85939Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by heating means, e.g. reflowing using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06527Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537Electromagnetic shielding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

電磁干渉低減を提供し、ダイに接続するためのリード線構造を有するダイパッケージ。前記ダイに接続された混合インピーダンスのリード線は、第1の金属コアと、第1の金属コアを被覆する誘電体層と、接地接続された第1の外側金属層を有する第1のリード線と、第2の金属コアと、第2の金属コアを被覆する誘電体層と、接地接続された第2の外側金属層を有する第2のリード線とを備える。各リード線はEMIおよびクロストークに対する感受性を低減する。A die package having a lead structure for providing electromagnetic interference reduction and connecting to a die. A mixed impedance lead connected to the die includes a first metal core, a dielectric layer covering the first metal core, and a first lead having a first outer metal layer connected to ground. And a second metal core, a dielectric layer covering the second metal core, and a second lead wire having a second outer metal layer connected to the ground. Each lead reduces susceptibility to EMI and crosstalk.

Description

本発明は、電磁干渉を低減し、ダイに接続する新規のリード線構造に関する。本発明の実施により、リード線間のクロストーク、パッケージの内側または外側での電磁放出によって生じるノイズへの感受性が低減される。   The present invention relates to a novel lead structure that reduces electromagnetic interference and connects to a die. Implementation of the present invention reduces susceptibility to noise caused by crosstalk between leads, electromagnetic emissions inside or outside the package.

さらに、本発明は1以上のダイに接続する誘電体被覆されたリード線を接続するために形成された新規のマルチグランドプレーンに関する。   Furthermore, the present invention relates to a novel multi-ground plane formed to connect dielectric coated leads that connect to one or more dies.

性能の低下につながる電磁干渉は、パッケージ型ダイ、特にギガヘルツ周波数で作動する入出力(IO)を有するダイにとって一般的な問題になってきている。多くの集積回路は望ましくない量のEMIを発生する。一般的に、集積回路によって生成されるノイズは、ダイと、パッケージを介したダイのピンへの接続に起因する。EMIが隣接する部品や集積回路に結合すると、EMIがそれらの個々の性能に干渉して、システム全体の性能に影響する可能性がある。EMIの悪影響のため、容認できる放射EMIのレベルが厳密な規制限度の対象となるため、集積回路から生成するEMIを阻止または抑制することが望ましい。   Electromagnetic interference leading to performance degradation has become a common problem for packaged dies, particularly dies with input / output (IO) operating at gigahertz frequencies. Many integrated circuits generate an undesirable amount of EMI. In general, the noise generated by an integrated circuit is due to the connection of the die to the pins of the die through the package. When EMI couples to adjacent components or integrated circuits, EMI can interfere with their individual performance and affect overall system performance. Because of the adverse effects of EMI, acceptable radiated EMI levels are subject to strict regulatory limits, so it is desirable to prevent or suppress EMI generated from integrated circuits.

リード線の分離またはシールドでの絶縁といった解決策は、常に利用できたり十分であるわけではない。さらに、ICパッケージレベルでのEMIソリューションは、そのレベルでの主要事項が信号の伝送品質と機能性であるため、しばしば軽視される。パッケージレベルでのEMIソリューションは、「下流」またはアドオンソリューションの必要性の排除に役立つため、有効である。   Solutions such as lead separation or shield insulation are not always available or sufficient. Furthermore, EMI solutions at the IC package level are often neglected because the main issues at that level are signal transmission quality and functionality. EMI solutions at the package level are useful because they help eliminate the need for “downstream” or add-on solutions.

従来技術の課題と欠点に鑑み、本発明の目的は、優れた信号の伝送品質と機能性を備えるコンパクトなダイパッケージを提供することであり、特に2以上のリード線を有するスタックドダイパッケージおよび/またはBGAパッケージを提供することである。   In view of the problems and disadvantages of the prior art, it is an object of the present invention to provide a compact die package with excellent signal transmission quality and functionality, in particular a stacked die package having two or more lead wires and / or Or to provide a BGA package.

当業者には明らかであろう上記および他の目的は、EMI減衰のためのダイパッケージを対象とする本発明によって達成され、そのダイパッケージは、複数の接続パッドを有するダイと、複数の接続要素を支持するダイ基板と、第1の金属コア径を有する第1の金属コア、前記第1の金属コアを被覆する第1の誘電体厚を有する第1の誘電体層、および、前記第1の誘電体層を被覆する第1の外側金属層を有し、前記第1の外側金属層が接地接続されている、第1のリード線と、第2の金属コア径を有する第2の金属コア、前記第2の金属コアを被覆する第2の誘電体厚を有する第2の誘電体層、および、前記第2の誘電体層を被覆する第2の外側金属層を有し、前記第2の外側金属層が接地接続されている、第2のリード線とを備え、その結果、前記第1と第2のリード線は第1と第2のリード線の間のEMIおよびクロストークへの感受性を低減する。   The above and other objects that will be apparent to those skilled in the art are achieved by the present invention directed to a die package for EMI attenuation, the die package comprising a die having a plurality of connection pads and a plurality of connection elements. A die substrate that supports the first metal core, a first metal core having a first metal core diameter, a first dielectric layer having a first dielectric thickness covering the first metal core, and the first A second metal having a first lead wire and a second metal core diameter having a first outer metal layer covering the dielectric layer, wherein the first outer metal layer is grounded A core, a second dielectric layer having a second dielectric thickness covering the second metal core, and a second outer metal layer covering the second dielectric layer, A second lead wire, wherein the second outer metal layer is grounded, and Result, the first and second lead wires reduces the susceptibility to EMI and crosstalk between the first and second leads.

さらに、本発明はダイパッケージを対象とし、そのダイパッケージは、複数の接続パッドを有するダイと、複数の接続要素を支持するダイ基板と、第1の金属コア径を有する第1の金属コア、前記第1の金属コアを被覆する第1の誘電体厚を有する第1の誘電体層、および、前記第1の誘電体層を被覆する第1の外側金属層を有し、第1の外側金属層に第1のグランドプレーンが取り付けられている、第1のリード線と、第2の金属コア径を有する第2の金属コア、前記第2の金属コアを被覆する第2の誘電体厚を有する第2の誘電体層、および、前記第2の誘電体層を被覆する第2の外側金属層を有し、第2の外側金属層に第2のグランドプレーンが取り付けられている、第2のリード線とを備え、その結果、前記第1と第2のリード線は第1と第2のリード線との間のEMIおよびクロストークへの感受性を低減する。第1のリード線は、第1のダイからダイ基板上の複数の接続要素のうち1つに延出してもよい、および/または、第2のリード線は、第2のダイからダイ基板上の複数の接続要素のうち1つに延出してもよい。第2のグランドプレーンは、第1のグランドプレーンに重ね合わせてあってもよいし、重ね合わせていなくてもよい。重ね合わせの場合、電気絶縁を維持する仲介層が、第1のグランドプレーンと第2のグランドプレーンとの間に配置されてもよい。   Furthermore, the present invention is directed to a die package, the die package including a die having a plurality of connection pads, a die substrate supporting a plurality of connection elements, a first metal core having a first metal core diameter, A first dielectric layer having a first dielectric thickness covering the first metal core, and a first outer metal layer covering the first dielectric layer; A first lead wire having a first ground plane attached to the metal layer, a second metal core having a second metal core diameter, and a second dielectric thickness covering the second metal core And a second outer metal layer covering the second dielectric layer, and a second ground plane is attached to the second outer metal layer. 2 lead wires, so that the first and second lead wires are 1 and to reduce the susceptibility to EMI and cross talk between the second lead. The first lead may extend from the first die to one of a plurality of connecting elements on the die substrate, and / or the second lead from the second die to the die substrate One of the plurality of connection elements may be extended. The second ground plane may or may not overlap with the first ground plane. In the case of superposition, an intermediary layer that maintains electrical insulation may be disposed between the first ground plane and the second ground plane.

さらに、本発明に係るダイパッケージは、第1と第2のダイとを有するスタックドダイパッケージであってもよく、前記ダイそれぞれは複数の接続パッドを有し、第1のリード線は、前記第1のダイの前記複数の接続パッドのうち1つから、前記ダイ基板上の前記複数の接続要素のうち1つに延出するか、または、前記第2のダイの前記複数の接続パッドのうち1つに延出し、第2のリード線は、前記第2のダイの前記複数の接続パッドのうち1つから、前記ダイ基板上の前記複数の接続要素のうち1つに延出するか、または、前記第1のダイの前記複数の接続パッドのうち1つに延出する。   Further, the die package according to the present invention may be a stacked die package having a first die and a second die, each die having a plurality of connection pads, and the first lead wire being the first lead wire. Extending from one of the plurality of connection pads of one die to one of the plurality of connection elements on the die substrate, or of the plurality of connection pads of the second die And the second lead extends from one of the plurality of connection pads of the second die to one of the plurality of connection elements on the die substrate, Alternatively, it extends to one of the plurality of connection pads of the first die.

従属請求項は、本発明に係るダイパッケージに効果的な実施形態を対象とし、そこに開示されるそれぞれの特徴は、個別に追加されてもよいし、組み合わせて追加されてもよい。   The dependent claims are directed to embodiments that are advantageous for die packages according to the present invention, and each feature disclosed therein may be added individually or in combination.

新規であると思われる本発明の特徴および本発明に特徴的な要素は、添付の特許請求の範囲に具体的に規定されている。図面は例証のみを目的とし、縮尺通りに描かれているわけではない。しかし、本発明自体は、構成および動作方法の両方において、添付の図面と併せて以下の詳細な説明の参照により最もよく理解されるであろう。   The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The drawings are for illustration purposes only and are not drawn to scale. The invention itself, however, will be best understood by reference to the following detailed description in conjunction with the accompanying drawings in both construction and method of operation.

外側の接地接続された金属被覆を有する誘電体被覆リード線を備えたファインピッチ低クロストークダイパッケージの図である。FIG. 6 is a view of a fine pitch low crosstalk die package with a dielectric coated lead having an outer grounded metal coating. 外側の接地接続された金属被覆を有する低クロストークの重なり合う誘電体被覆リード線を示す図である。FIG. 5 illustrates a low crosstalk overlapping dielectric coated lead having an outer grounded metal coating. スタックドダイパッケージで使用される低クロストークリード線を示す図である。It is a figure which shows the low crosstalk lead wire used with a stacked die package. ダイからダイへの、またはパッケージからパッケージへの実施形態で使用される低クロストークリード線を示す図である。FIG. 6 illustrates a low crosstalk lead used in a die-to-die or package-to-package embodiment. 外側の接地接続された金属被覆を有する誘電体被覆リード線の製造の方法ステップを示すブロック図である。FIG. 6 is a block diagram illustrating method steps for manufacturing a dielectric coated lead having an outer grounded metal coating. 外側の接地接続された金属被覆を有する誘電体被覆リード線の製造のサブトラクティブ法を示す図である。FIG. 6 illustrates a subtractive method of manufacturing a dielectric coated lead having an outer grounded metal coating. 外側の接地接続された金属被覆を有する誘電体被覆リード線を備えたBGAパッケージを示す図である。FIG. 4 shows a BGA package with a dielectric coated lead having an outer grounded metal coating. 外側の接地接続された金属被覆を有する誘電体被覆リード線を備えたリードフレームパッケージの一部分を示す図である。FIG. 5 shows a portion of a leadframe package with a dielectric coated lead having an outer grounded metallization. 周波数に基づくクロストークレベルのSパラメータ測定を示す図である。It is a figure which shows the S parameter measurement of the crosstalk level based on a frequency. 誘電体被覆と外側の接地接続された金属層を有するシングルリード線とディファレンシャルリード線に関連するEM場をそれぞれ示す図である。FIG. 4 shows EM fields associated with a single lead and a differential lead with a dielectric coating and an outer grounded metal layer, respectively. 重なり合っていても重なり合っていなくてもよい分離したグランドプレーンに接続された誘電体および金属を被覆したリード線を有する本発明に係るダイパッケージを示す図である。FIG. 5 shows a die package according to the present invention having dielectric and metal coated lead wires connected to separate ground planes that may or may not overlap. 2つのグランドプレーンを有する本発明に係るダイパッケージを示す図である。FIG. 2 shows a die package according to the present invention having two ground planes. 2つのグランドプレーンがそれぞれRFグランドシールドとDC電力シールドを形成している別例の実施形態を示す図である。FIG. 6 is a diagram illustrating another embodiment in which two ground planes form an RF ground shield and a DC power shield, respectively.

本発明の好適な実施形態を説明するにあたり、図面のうち図1−図13を参照するが、同じ部品番号は本発明の同じ特徴を有している。   In describing the preferred embodiment of the present invention, reference will be made to FIGS. 1-13 of the drawings wherein like parts have the same features of the present invention.

電磁シールドを有し、金属コアと接地接続可能な導電外側層の間に1以上の中間誘電体層を有するリード線が、パッケージの電気的性能を改善するために使用される。これは、異なる長さのリード線156を有する、基板154に取り付けられたダイ152を有するダイパッケージ150を図示した図1に描かれている。図から分かるように、基板154上の接続パッド158は、通常、プロセスを考慮してチップ側よりもスペーシングが大きくなっている。ダイパッドのスペーシングは、ワイヤボンド機で実現可能なピッチに応じて共通に規定される。基板側では、プリント回路基板(PCB)型プロセスのリソグラフィー上の再現性、および、半田、ピンまたは配線要素の配置精度によって規定される。実働上、ワイヤは、パッケージよりもチップにより接近して配置される。これは、ダイのサイズが小さくなるにつれて、特にダイ近傍において望ましくない電磁場結合(クロストーク)が発生することを意味する。本明細書に記載されるように形成されたリード線は、パッケージ内の電磁干渉(EMI)を低減することに加えて、(パッケージの)外部のEMIの感受性を低減し、同様に、電磁放出も実質的に低減する。   Lead wires having an electromagnetic shield and having one or more intermediate dielectric layers between a metal core and a conductive outer layer that can be grounded are used to improve the electrical performance of the package. This is depicted in FIG. 1 illustrating a die package 150 having a die 152 attached to a substrate 154 with different length leads 156. As can be seen from the figure, the connection pads 158 on the substrate 154 usually have a larger spacing than the chip side in consideration of the process. The spacing of the die pad is commonly defined according to the pitch that can be realized by the wire bonding machine. On the board side, it is defined by the lithographic reproducibility of the printed circuit board (PCB) type process and the placement accuracy of solder, pins or wiring elements. In practice, the wires are placed closer to the chip than to the package. This means that as the die size decreases, undesirable electromagnetic field coupling (crosstalk) occurs, particularly near the die. In addition to reducing electromagnetic interference (EMI) within the package, the leads formed as described herein reduce the sensitivity of external EMI (of the package), as well as electromagnetic emissions. Is also substantially reduced.

図2に示すように、半導体ダイパッケージングシステム100は、リード線の構造によって低い電磁放出およびクロストークを有するリード線110、112および114を備える。基板102に実装されたダイ120は、ダイ120によって要求される信号、電力、または他の機能性のための多重接続パッド122を有する。基板102は、パッケージからの導電パスは、直接、または、導電リードフレーム、充填されたビア、導電トレース、二次レベル配線等によって提供する導電パッド104を含んでもよい。リード線110、112および114は、導電パッド104に接続され、また図示されるように、実質的に異なる長さを有していてもよい。図2に示すように、リード線は密集して配置され、交差または上下配置ができ(例えば、リード線110と112は交差して描かれている)、望ましくない多くの電磁結合の可能性を有している。   As shown in FIG. 2, the semiconductor die packaging system 100 includes leads 110, 112 and 114 having low electromagnetic emissions and crosstalk due to the structure of the leads. The die 120 mounted on the substrate 102 has multiple connection pads 122 for signals, power, or other functionality required by the die 120. The substrate 102 may include conductive pads 104 that provide a conductive path from the package directly or by a conductive lead frame, filled vias, conductive traces, secondary level wiring, and the like. Leads 110, 112 and 114 are connected to conductive pad 104 and may have substantially different lengths as shown. As shown in FIG. 2, the leads are densely arranged and can be crossed or placed vertically (eg, leads 110 and 112 are drawn crossing), which creates many undesirable electromagnetic coupling possibilities. Have.

図2に示された実施形態において、リード線110、112および114は内側コアと外側金属層を有している。例えば、リード線110、112および114はその長さに沿って規定の直径の金属コアを有し、その金属コアは薄い誘電体層と導電性金属層で逐次被覆される。同じサイズで付加的な誘電体および金属被覆がない裸リード線と比べて、リード線110、112および114は、放出される放射がより少なく、(パッケージの)外部のEMIへの感受性がより少なく、クロストークがより生じにくい。特定の実施形態において開示されるようなリード線構成の優れた電気的特性により、実質的な長さが異なるが同じコア径を有するリード線は、裸ワイヤと比べて実質的に同じノイズ低減を有することができる。測定されたノイズ低減は、誘電体と、誘電体を被覆する金属層(複数)を持たない裸リード線に比べて、5dBを超えて30dBに及ぶほど大きいことがわかる。特定の実施形態において、EMIへの耐性はリード線の長さ方向の範囲にわたり有効であり、2つのリード線は同じ断面構造とインピーダンスを持つことができるが、一方のリード線は、同じEMI特性を持ちながらも他方のリード線の長さの10倍である。   In the embodiment shown in FIG. 2, leads 110, 112 and 114 have an inner core and an outer metal layer. For example, the leads 110, 112 and 114 have a metal core of a defined diameter along their length, and the metal core is sequentially coated with a thin dielectric layer and a conductive metal layer. Compared to bare leads of the same size and without additional dielectric and metallization, leads 110, 112 and 114 emit less radiation and are less sensitive to external EMI (of the package). Crosstalk is less likely to occur. Due to the superior electrical characteristics of the lead configuration as disclosed in certain embodiments, leads having different core lengths but the same core diameter will have substantially the same noise reduction compared to bare wire. Can have. It can be seen that the measured noise reduction is greater than 5 dB and 30 dB compared to the dielectric and bare lead without the metal layer (s) covering the dielectric. In certain embodiments, EMI resistance is effective over a range of lead lengths, and two leads can have the same cross-sectional structure and impedance, while one lead has the same EMI characteristics. Is 10 times the length of the other lead wire.

不必要なクロストークにつながる電磁場は、横並びのリード線だけで発生するわけではなく、スタック状の構成で互いに隣接しているリード線でも発生することがある。これは、図3に示すスタックドダイで現実化し、図3は、本明細書で説明するような誘電体層と導電金属層を被覆したリード線ではなく、裸ワイヤが使用された場合に、横並びまたは上下配置のリード線から容認できないクロストークが生じる例示的なリード線164a−dおよび166aを有するダイ162a−dを備えるスタックドダイパッケージ160を示している。同様に図4は、ダイからダイへのリード線接続174と、ダイから基板への接続176を有するダイスタック170および172を示す。低減されたクロストークを有する別々に実装されたパッケージングシステム180、182内のダイからダイへの直接接続178があってもよい。   Electromagnetic fields leading to unnecessary crosstalk are not generated only by side-by-side leads, but may also be generated by leads adjacent to each other in a stacked configuration. This is realized with the stacked die shown in FIG. 3, which is shown side-by-side when bare wires are used instead of leads coated with a dielectric layer and a conductive metal layer as described herein. Alternatively, a stacked die package 160 is shown that includes dies 162a-d having exemplary leads 164a-d and 166a that result in unacceptable crosstalk from the vertically disposed leads. Similarly, FIG. 4 shows die stacks 170 and 172 having die-to-die lead connections 174 and die-to-substrate connections 176. There may be a die-to-die direct connection 178 in separately implemented packaging systems 180, 182 with reduced crosstalk.

半導体ダイパッケージングに使用される誘電体被覆リード線は、異なる誘電体厚を有するように形成することができる。コア径と誘電体厚の両方を変えることができる。特定の実施形態において、被覆誘電体の組成も変えることができる。これは、例えば、優れた蒸気バリア、酸素分解耐性等を有する高性能誘電体が、低コストの誘電体材料の厚い層の上に薄く被着することを可能にする。図示される実施形態の別の態様において、リード線110、112および114(図2および3参照)は、内側コアと外側金属層にわたり異なる誘電体厚を有し、それが別個に異なるインピーダンスを提供する。例えば、リード線110はその長さに沿って規定の直径の金属コアを有してもよく、金属コアは薄い誘電体層と導電金属層で逐次被覆される。そのようなリード線110は、結果として得られる低インピーダンスと低静電容量が電力低下を減らすため、電力の伝送に適している。代替的に、リード線112は信号データの伝送に適したより厚い誘電体層を有し、一方で、リード線114は中間の厚さの誘電体層を有している。特定の実施形態において、開示されるリード線構造の優れた電気的特性により、実質的に長さが異なるが同じコア径を有するリード線が、50%以上異なる長さを持つにも拘らず、目標インピーダンスの10%以内での実質的に同じインピーダンスを持つことが可能である。例えば、リード線116は、長さがリード線110の2倍であるにも拘わらず、リード線110とほぼ同じインピーダンスを有することが可能である。特定の実施形態において、リード線の差がさらに大きい場合もあり、2つのリード線は同じ断面構造とインピーダンスとを有しているが、一方のリード線の長さは他方のリード線の長さの10倍である。   Dielectric coated leads used in semiconductor die packaging can be formed to have different dielectric thicknesses. Both core diameter and dielectric thickness can be varied. In certain embodiments, the composition of the coating dielectric can also be varied. This allows, for example, high performance dielectrics with excellent vapor barrier, oxygen decomposition resistance, etc. to be thinly deposited on a thick layer of low cost dielectric material. In another aspect of the illustrated embodiment, the leads 110, 112 and 114 (see FIGS. 2 and 3) have different dielectric thicknesses across the inner core and outer metal layer, which separately provide different impedances. To do. For example, the lead 110 may have a metal core of a defined diameter along its length, and the metal core is sequentially coated with a thin dielectric layer and a conductive metal layer. Such a lead 110 is suitable for power transmission because the resulting low impedance and low capacitance reduce power loss. Alternatively, lead 112 has a thicker dielectric layer suitable for transmission of signal data, while lead 114 has an intermediate thickness of dielectric layer. In certain embodiments, due to the superior electrical properties of the disclosed lead structure, lead wires having substantially different lengths but the same core diameter have different lengths by more than 50%, It is possible to have substantially the same impedance within 10% of the target impedance. For example, the lead 116 can have substantially the same impedance as the lead 110 even though it is twice as long as the lead 110. In certain embodiments, the lead wire difference may be even greater, and the two lead wires have the same cross-sectional structure and impedance, but the length of one lead wire is the length of the other lead wire. 10 times.

一般に、薄い誘電体層は電力線用途に有効な低インピーダンスを提供し、厚い誘電体層は一般に信号の伝送品質のために有効であり、リード線上の外側金属層は効果的には同じ接地に接続される。コア径と誘電体厚の組み合わせが可能であり、一連のそのようなステップが別々のインピーダンスを有するリード線を実現するために行われてもよい。特定の実施形態において、電力処理能力を増加させ、電力線温度を下げ、および/または、接地電位の変動または電力低下を悪化させることになる電源および接地線へのインダクタンスをさらに減少させるために、電力線に大径のコアを備えることが望ましい。   In general, a thin dielectric layer provides a low impedance useful for power line applications, a thick dielectric layer is generally effective for signal transmission quality, and the outer metal layer on the lead is effectively connected to the same ground Is done. A combination of core diameter and dielectric thickness is possible, and a series of such steps may be performed to achieve a lead having separate impedances. In certain embodiments, the power line is used to increase power handling capability, lower power line temperature, and / or further reduce inductance to the power supply and ground line that will exacerbate ground potential fluctuations or power degradation. It is desirable to provide a large-diameter core.

3以上の異なる誘電体厚を有するリード線を備えることが多くのパッケージに効果的であるため、中間厚さの誘電体層も有用である。電力伝送を最大化するために、電源と、実質的に異なるインピーダンスの負荷を接続するために、中間の誘電体厚を有するリード線を使用することができる。例えば、10オームの電源が20オームのリード線で40オームの負荷に接続されてもよい。さらに、誘電体のコストが高くなることがあるため、重要な信号路は厚い誘電体を用いて配線されうるが、一方で、より重要度の低い状態またはリセットのリード線等は、電力リード線よりは厚いが重要な信号リード線よりは薄い(中間)厚さの誘電体層で被覆される。   Intermediate thickness dielectric layers are also useful because it is effective for many packages to have leads having three or more different dielectric thicknesses. In order to maximize power transfer, a lead having an intermediate dielectric thickness can be used to connect a power source and a load of substantially different impedance. For example, a 10 ohm power supply may be connected to a 40 ohm load with a 20 ohm lead. In addition, because the dielectric cost can be high, important signal paths can be routed using thick dielectrics, while less important or reset leads, etc. It is coated with a dielectric layer that is thicker, but thinner (intermediate) than the critical signal leads.

各リード線の所望の特定インピーダンス値を達成するために、ワイヤボンド径と組み合わせて、誘電体被覆の厳密な厚さを選択することができる。   The exact thickness of the dielectric coating can be selected in combination with the wire bond diameter to achieve the desired specific impedance value for each lead.

Figure 2016524338
Figure 2016524338

同軸線の特性のインピーダンスが式(1)に表されており、式(1)において、Lはユニット長ごとのインダクタンスであり、Cはユニット長ごとの静電容量であり、aはボンドワイヤの直径であり、bは誘電体の外径であり、εγは同軸誘電体の比誘電率である。 The impedance of the characteristic of the coaxial line is expressed by Equation (1), where L is the inductance for each unit length, C is the capacitance for each unit length, and a is the bond wire Is the diameter, b is the outer diameter of the dielectric, and ε γ is the relative dielectric constant of the coaxial dielectric.

図5に示されるように、一実施形態において、1以上のグランドプレーンを有する、または持たない外側の接地接続された金属被覆を備えた誘電体被覆リード線の製造は、ブロック図200に示された以下のステップを用いて進行できる。第1のステップ202において、接続パッドが、ダイおよび基板上で洗浄される。次に、ワイヤボンダを用いてダイが接続パッドに接続される(204)。任意で、第2の直径のワイヤ(例えば、電力接続に適した、より大径のワイヤ)が取り付けられてもよいし(206)、または、選択的な被覆を可能にするためにダイの領域がマスキングされるか、または、他の方法で保護されてもよい(ステップ208)。同一または異なる組成の誘電体の1以上の層が被覆されてもよく(ステップ210)、続いて、誘電体被覆ステップ210で被覆された接地接続へのアクセスを可能にするために、誘電体部分の選択的なレーザーまたはサーマルアブレーションまたは化学的除去が行われる(ステップ212)。いくつかの実施形態では接地ビアの必要性を排除することができるため、このステップは任意である。仮想RF接地が容量結合によって達成できるため、また、厚さ値(Erの関数)への周波数依存性が容量結合による接地確立を可能にするため、これは高周波数で稼動するダイに特に適する。次に、金属被覆が行われ(214)、リード線の最外金属被覆層を形成する金属層で誘電体を被覆し、リード線を接地接続する。このプロセス全体を多数回繰り返してもよく(ステップ216)、それは、選択可能な被覆技法を用いる実施形態に有効であり、また、多数のダイまたは複雑かつ異なるインピーダンスのリード線を用いる実施形態では特に有効である。最終ステップ(ステップ218)において、非キャビティパッケージに関しては、リード線を封止するためにオーバーモールドを使用することができる。封止されたリード線は、米国特許第6,770,822号明細書および米国特許出願公開第2012/0066894号明細書に記載された高周波数デバイスパッケージに使用可能なものであり、それらの開示を参照して用いてもよい。   As shown in FIG. 5, in one embodiment, the fabrication of a dielectric coated lead with an outer grounded metallization with or without one or more ground planes is shown in block diagram 200. You can proceed using the following steps: In a first step 202, the connection pads are cleaned on the die and substrate. Next, the die is connected to the connection pad using a wire bonder (204). Optionally, a second diameter wire (eg, a larger diameter wire suitable for power connection) may be attached (206) or the area of the die to allow selective coverage May be masked or otherwise protected (step 208). One or more layers of dielectric of the same or different composition may be coated (step 210), followed by a dielectric portion to allow access to the ground connection coated in dielectric coating step 210. A selective laser or thermal ablation or chemical removal is performed (step 212). This step is optional because in some embodiments the need for ground vias can be eliminated. This is particularly suitable for dies operating at high frequencies since virtual RF grounding can be achieved by capacitive coupling and the frequency dependence on the thickness value (a function of Er) allows ground establishment by capacitive coupling. Next, metallization is performed (214), the dielectric is covered with a metal layer that forms the outermost metallization layer of the lead wire, and the lead wire is grounded. This entire process may be repeated a number of times (step 216), which is useful for embodiments using selectable coating techniques, and particularly in embodiments using multiple dies or complex and different impedance leads. It is valid. In the final step (step 218), for non-cavity packages, overmolding can be used to seal the leads. Sealed leads are those that can be used in the high frequency device packages described in US Pat. No. 6,770,822 and US 2012/0066894, and their disclosure. May be used with reference to

特定の実施形態において、説明されたプロセスへの変更および追加が可能である。例えば、誘電体の共形被覆は、化学的(電気泳動)、機械的(表面張力)、触媒プライマー、電磁(UV、IR)、電子線、その他適切な技法によって達成することができる。電気泳動ポリマーは、それらがプロセスパラメータを調整することにより、および/または電気泳動塗布液に単純に添加剤、濃度、化学的、熱的またはタイミングの変更を施すことによって容易に厳密な厚さに被覆できる自己抑制反応に依存するため、特に有利である。   In particular embodiments, changes and additions to the described processes are possible. For example, dielectric conformal coating can be achieved by chemical (electrophoresis), mechanical (surface tension), catalytic primer, electromagnetic (UV, IR), electron beam, and other suitable techniques. Electrophoretic polymers can be easily made to exact thicknesses by adjusting process parameters and / or simply by applying additive, concentration, chemical, thermal or timing changes to the electrophoretic coating solution. This is particularly advantageous because it depends on the self-inhibiting reaction that can be coated.

別の実施形態において、誘電体を予備被覆したボンドワイヤを用いてリード線を形成してもよい。市販の被覆ワイヤは、例えば50オームのリード線を製造するために必要な誘電体厚よりも典型的に薄いが、所望のインピーダンスを設定するために誘電体厚を増加させるために、上記に説明した誘電体被覆ステップを用いることができる。これらの予備被覆ワイヤの使用は、同軸リード線を形成するために必要な他のプロセスステップを単純化し、必要な蒸着誘電体のより薄い層と、接地ビアを形成するためのより迅速な処理時間を可能にする。予備被覆されたボンドワイヤは、空間が狭いまたは交差するリード線の短絡を防止するために使用することができる。特定の実施形態において、予備被覆ボンドワイヤは、選択的パターニング技法を可能にするために感光性材料で製造された誘電体を有していてもよい。   In another embodiment, the lead may be formed using a bond wire pre-coated with a dielectric. Commercially coated wires are typically thinner than the dielectric thickness required to produce, for example, a 50 ohm lead, but are discussed above to increase the dielectric thickness to set the desired impedance. A dielectric coating step can be used. The use of these pre-coated wires simplifies other process steps required to form coaxial leads and requires a thinner layer of deposited dielectric and faster processing time to form ground vias. Enable. Pre-coated bond wires can be used to prevent shorts in tight or intersecting leads. In certain embodiments, the pre-coated bond wire may have a dielectric made of a photosensitive material to allow selective patterning techniques.

別の実施形態において、誘電性パリレンが使用することができる。パリレンは、水分バリアおよび誘電体バリアとして使用され、多様な化学蒸着ポリ(p−キシレン)ポリマーの商標名である。パリレンは、修正パリレン被覆システムを用いた成長抑制縮合反応で形成することができるものであり、該システムにおいて、ダイ、基板およびリード線は感光板に整列し、それがEM放射(IR、UVまたはその他)を厳密に衝突させ、選択的な誘電体の成長速度を提供する。これが、コンタクトビア形成、パリレンのバルク除去等のプロセスの必要性を効果的に低減または排除できる。   In another embodiment, dielectric parylene can be used. Parylene is used as a moisture barrier and dielectric barrier and is the trade name for a variety of chemical vapor deposited poly (p-xylene) polymers. Parylene can be formed in a growth-inhibited condensation reaction using a modified parylene coating system, in which the die, substrate and lead are aligned with the photosensitive plate, which is EM radiation (IR, UV or Others) closely collide, providing a selective dielectric growth rate. This can effectively reduce or eliminate the need for processes such as contact via formation and parylene bulk removal.

パリレンおよびその他の誘電体は、酸素、水蒸気および熱が存在する場合、酸素切断による分解を受けることが知られている。損傷は、真に密封性の界面を形成できる3−5ミクロン厚さの薄膜層で優れた蒸気酸素バリアを形成する金属層によって制限することができる。代替的に、電気的、熱的または製造上の要求により、金属が選択的に除去されている場合、または金属が特定領域に被覆していない場合、広範なポリマー系蒸気酸素バリアの使用が可能であり、中でもポリビニルアルコール(PVA)は広範に使用される1つのポリマーである。これらのポリマーは、グロブトッピング処理、スクリーン印刷処理、ステンシル処理、ガントリー分配処理、酸素または水蒸気環境に曝されるパリレン表面に噴霧処理されてもよい。有利には、蒸気バリアポリマーの使用は、使用しなければ高コストのパリレンまたは酸素感応物が必要とされるため、コスト削減戦略の一環となりうる。   Parylene and other dielectrics are known to undergo oxygen scission decomposition in the presence of oxygen, water vapor and heat. Damage can be limited by a metal layer that forms an excellent vapor oxygen barrier with a 3-5 micron thick thin film layer that can form a truly hermetic interface. Alternatively, a wide range of polymer-based vapor oxygen barriers can be used if the metal is selectively removed due to electrical, thermal, or manufacturing requirements, or if the metal does not cover a specific area Among them, polyvinyl alcohol (PVA) is one widely used polymer. These polymers may be sprayed onto a parylene surface exposed to a glob topping process, a screen printing process, a stencil process, a gantry distribution process, an oxygen or water vapor environment. Advantageously, the use of a vapor barrier polymer can be part of a cost-reduction strategy because otherwise expensive parylene or oxygen sensitive materials are required.

理解されるように、説明した全ての方法ステップは、種々の選択可能な被覆技法の利点を享受する。選択可能な被覆は、物理的マスキング、指向性ポリマー蒸着、フォトレジスト法、または、被覆時に、金属コア、誘電体層または他の最外層において、異なる被覆厚さを保証する任意の他の適切な方法を用いてもよい。選択可能な被覆では、リード線の構築がアディティブ法で可能であるが、サブトラクティブ法も可能であり、サブトラクティブ法では、異なるインピーダンスの配線を形成するために誘電体または金属が除去される。例えば、1以上のダイが配置されたパッケージが、全パッケージとデバイスパッドの配線用に適宜ワイヤボンド接合されてもよい。ダイパッケージの製造に関するステップと構造を示す図6に関連して示されるように、誘電体被覆300はワイヤボンド金属導体302の上に所定の厚さに被覆することができる(ステップA)が、所定の厚さは二次配線インピーダンスに必要とされる誘電体の厚さである。二次インピーダンスのワイヤボンド誘電体は例えばエッチングステップによって除去される(ステップB)ことができ、続いて第2の被覆304被覆(ステップC)、それに続いて両配線の金属被覆306が行われる(ステップD)。このサブトラクティブプロセスにより、2つの独立したインピーダンスのワイヤボンドが作製される。   As will be appreciated, all described method steps enjoy the advantages of various selectable coating techniques. Selectable coatings can be physical masking, directional polymer deposition, photoresist methods, or any other suitable coating that guarantees different coating thicknesses in the metal core, dielectric layer or other outermost layer when coated. A method may be used. With selectable coatings, lead construction is possible with additive methods, but subtractive methods are also possible, where the dielectric or metal is removed to form wires of different impedances. For example, a package in which one or more dies are arranged may be appropriately wire-bonded for wiring of all packages and device pads. As shown in connection with FIG. 6, which shows the steps and structures related to die package manufacturing, the dielectric coating 300 can be coated to a predetermined thickness over the wirebond metal conductor 302 (step A), The predetermined thickness is the thickness of the dielectric required for the secondary wiring impedance. The secondary impedance wire bond dielectric can be removed, for example, by an etching step (Step B), followed by a second coating 304 coating (Step C), followed by a metal coating 306 of both wires ( Step D). This subtractive process creates two independent impedance wire bonds.

図7に示す実施形態は、多数の選択されたインピーダンスを有する誘電体と金属を被覆したリード線412、414を有するボールグリッドアレイ(BGA)パッケージ410を示す。BGAは、集積回路に広く使用されている表面実装パッケージングであり、BGAの底面全体が接続パッドに使用することができるため、一般に、デュアルインライン、リードフレームまたは他のフラットパッケージよりも多数の配線ピンを提供できる。多くの種類のBGAパッケージにおいて、ダイ416は接続パッドに接続された充填可能なビア420を有する基板418に取り付けられている。リード線412、414は頂部側ダイ416をパッド/ビア420に接続するために使用され、これにより基板418の頂部側から底部への電気接続を提供する。BGAパッケージでは、半田ボール422がパッケージの底部に取り付けられ、プリント回路基板または他の基板への半田付けまでは粘着質のフラックスで定位置に保持される。本明細書で説明するように、従来型BGAパッケージのワイヤボンドは、誘電体層と外側接地接続可能な金属層を有する改良されたリード線で置き換えることができる。リード線は、内側コアおよび外側金属層にわたり変化する誘電体厚を有することができ、誘電体層厚が部分的に相違、または、より良く適合するように選択された特定のインピーダンスを有するように選択的に最適化することができる。図7に示すように、長いリード線412および短いリード線414の両方がサポートされる。   The embodiment shown in FIG. 7 shows a ball grid array (BGA) package 410 having a number of selected impedance dielectric and metal coated leads 412, 414. BGA is a surface mount packaging that is widely used in integrated circuits and generally has more wiring than dual in-line, leadframe or other flat packages because the entire bottom surface of the BGA can be used for connection pads. Can provide pin. In many types of BGA packages, the die 416 is attached to a substrate 418 having fillable vias 420 connected to connection pads. Leads 412, 414 are used to connect top die 416 to pad / via 420, thereby providing an electrical connection from the top side to the bottom of substrate 418. In a BGA package, solder balls 422 are attached to the bottom of the package and held in place with adhesive flux until soldering to a printed circuit board or other board. As described herein, the wire bond of a conventional BGA package can be replaced with an improved lead having a dielectric layer and a metal layer that can be externally grounded. The lead can have a dielectric thickness that varies across the inner core and the outer metal layer so that the dielectric layer thickness is partially different or has a specific impedance selected to better fit. It can be selectively optimized. As shown in FIG. 7, both long leads 412 and short leads 414 are supported.

より詳細には、改良されたBGAパッケージの組み立てにおいて、基板のビアに隣接しビアの周りに形成された接続パッドを支持する基板に対して、ダイの表面を上にした取り付けを要する場合がある。この組み立ては、各々必要な配線向けに適宜ワイヤボンド接合され、ワイヤボンドは基板上の接続パッドとダイ上の接続パッドの間に形成される。低周波数および電力入力は低周波数信号リード線に接続されるが、高周波数入力と出力は高周波数信号リード線に接続される。いくつかの実施形態において、低周波数および電力入力のリード線は、高周波数信号リード線とは異なる厚さを持ちうる。そして、組立品は、基本的に共形の誘電体材料で被覆される。低コスト、真空蒸着の容易さ、および、優れた性能特性のために、パリレンが使用される。リードフレーム取付位置付近の誘電体層の一部分は、接地接続点または接地シールド層への電気的な接続を行うためにエッチング、熱劣化、レーザーアブレーションによって選択的に除去される。同様に、接地接続を可能にするために、誘電体層の一部分が、ダイ接続パッド付近で除去される。誘電体層上への金属被覆層の施工に続いて、構造上の接地接続がなされ、接地シールドを形成する。好ましい金属層の厚さは、皮層深さとDC耐性の点を考慮して選択されるべきであり、銀、銅、または金等の優れた導電体から主に構成されるべきである。殆どのアプリケーションに対して、機能性の点では1ミクロンの被覆厚さで十分であるが、より厚い被覆は、リード線間のクロストークの低減に役立つ。これらの被覆は、リソグラフィーまたはその他のマスキング法と、めっきまたはその他の選択可能な被覆法の組み合わせにより、規定領域に施すことができる。パッケージは、ダイ上にオーバーモールドまたは蓋を配置し、次にダイシング(シンギュレーション)および検査を経て完成することができる。   More particularly, improved BGA package assembly may require die surface up attachment to a substrate that supports connection pads formed adjacent to and around the vias of the substrate. . This assembly is appropriately wirebonded for each required wiring, and wirebonds are formed between the connection pads on the substrate and the connection pads on the die. The low frequency and power inputs are connected to the low frequency signal lead, while the high frequency input and output are connected to the high frequency signal lead. In some embodiments, the low frequency and power input leads may have a different thickness than the high frequency signal leads. The assembly is then basically covered with a conformal dielectric material. Parylene is used because of its low cost, ease of vacuum deposition, and excellent performance characteristics. A portion of the dielectric layer near the lead frame attachment location is selectively removed by etching, thermal degradation, and laser ablation to make an electrical connection to a ground connection point or ground shield layer. Similarly, a portion of the dielectric layer is removed near the die connection pad to allow ground connection. Following the application of the metallization layer on the dielectric layer, a structural ground connection is made to form a ground shield. The preferred metal layer thickness should be selected in view of skin depth and DC resistance, and should be composed primarily of excellent conductors such as silver, copper, or gold. For most applications, a 1 micron coating thickness is sufficient for functionality, but a thicker coating helps reduce crosstalk between leads. These coatings can be applied to defined areas by a combination of lithography or other masking methods and plating or other selectable coating methods. The package can be completed by placing an overmold or lid on the die and then undergoing dicing (singulation) and inspection.

別法として、図8に示した実施形態において、ダイからリードフレームへ延出するワイヤボンドを有するダイパッケージ440をベースとした低コストなリードフレームは、個々のパッケージサイトの二次元アレイと外側フレーム部分を有するリードフレームストリップを形成することによって製造することができる。リードフレーム加工は、従来型であり、別個のリード線のエッチング、打ち抜き加工または電着により形成することができる。リードフレームストリップは、射出成形またはトランスファー成形装置を含むが、これらに限定されないモールドに配置することができる。市販のエポキシモールドコンパウンド等の好ましくはプラスチック製の適切な誘電体材料が、リードフレーム/モールド材料複合体構造を達成するために、モールドに射出、圧送または移送される。モールド材料の特性は、それらの比誘電率、損失正接および電気的分散特性ならびにそれらの温度、湿度および他の機械的な性能属性が重要である。   Alternatively, in the embodiment shown in FIG. 8, a low cost lead frame based on a die package 440 with wire bonds extending from the die to the lead frame comprises a two-dimensional array of individual package sites and an outer frame. It can be manufactured by forming a lead frame strip having a portion. Leadframe processing is conventional and can be formed by etching, punching or electrodeposition of separate lead wires. The leadframe strip can be placed in a mold including but not limited to injection molding or transfer molding equipment. A suitable dielectric material, preferably plastic, such as a commercially available epoxy mold compound, is injected, pumped or transferred to the mold to achieve a leadframe / mold material composite structure. The properties of the mold materials are important for their dielectric constant, loss tangent and electrical dispersion properties and their temperature, humidity and other mechanical performance attributes.

結果として得られる複合リードフレームストリップの各パッケージサイトは、モールド離型剤および/またはバリを除去されて、リードフレームの露出した金属部分の上から金属仕上げの被覆用に準備される。これは、浸漬または電気めっき等のめっき技法によって達成することができるものであり、金属は、腐食抑制とワイヤボンド接合を容易にするために選択される。そのような仕上げの一例は、ニッケルの薄膜層(保護用)に続く金の層(付加的な保護とワイヤボンドの能力)である。次に、結果として得られる成形されたリードフレームストリップの各パッケージサイトには必要なダイが配置されて底部に取り付けられ、ダイ取り付け材料は、特定のパッケージング用途に対応する機械的および熱的特性によって選択される。次に、結果として得られた組立品は各必要な配線向けに適宜ワイヤボンド接合され、ワイヤボンドはリードフレーム上のリード線とダイ上の接続パッドの間に形成される。低周波数および電力入力は低周波数信号リード線に接続され、他方で、高周波数入力および出力は高周波数信号リード線に接続される。いくつかの実施形態において、低周波数および電力入力は、高周波数信号リード線とは異なる厚さであってもよい。   Each package site of the resulting composite leadframe strip is prepared for metallization coating over the exposed metal portion of the leadframe with the mold release agent and / or burrs removed. This can be achieved by plating techniques such as immersion or electroplating, and the metal is selected to facilitate corrosion inhibition and wire bond bonding. An example of such a finish is a nickel thin film layer (for protection) followed by a gold layer (additional protection and wirebond capability). Next, each package site of the resulting molded leadframe strip is placed with the necessary dies and attached to the bottom, and the die attach material has mechanical and thermal properties that correspond to the specific packaging application. Selected by. The resulting assembly is then wirebonded as appropriate for each required wiring, and wirebonds are formed between the lead wires on the lead frame and the connection pads on the die. The low frequency and power input is connected to the low frequency signal lead, while the high frequency input and output is connected to the high frequency signal lead. In some embodiments, the low frequency and power inputs may be of a different thickness than the high frequency signal lead.

前述のBGAパッケージ410と同様に、配置後のリードフレームストリップは、パリレンを含む基本的に共形の誘電体材料で被覆される。パリレンの場合、最終的にPCBに取り付けられるリード線部分への被着を防止するために、アクリル系接着剤が付いた真空対応ポリイミド、または、同様の材料等のテープでパッケージの底部をマスキングすることが好ましい。これは、後続ステップにおいて、より容易な半田付けを可能にする。リードフレームの取り付け位置付近の誘電体の一部分は、接地接点または接地シールド層への電気的な接続を行うために、エッチング、熱的劣化またはレーザーアブレーションによって選択的に除去される。同様に、ダイ接続パッド付近の誘電体層の一部分が接地接続を可能にするために除去される。誘電体層の上からの金属被覆層の塗布に続いて、構造的な接地接続が施され、接地シールドを形成する。好ましい金属層の厚さは、DC耐性の点と皮層深さを考慮して選択されるべきであり、銀、銅または金等の優れた導電体から主に構成されるべきである。殆どの用途において、機能性の点では1ミクロンの被覆厚さが適切であるが、より厚い被覆は、リード線間のクロストークを低減するのに役立つ。これらの被覆は、リソグラフィーまたはその他のマスキング法と、めっきまたは他の選択可能な被覆法の組み合わせで、規定領域に加えることができる。パッケージは、ダイ上にオーバーモールドまたは蓋を配置し、次にダイシング(シンギュレーション)および検査を経て完成される。   Similar to the BGA package 410 described above, the resulting leadframe strip is coated with a basically conformal dielectric material including parylene. In the case of parylene, the bottom of the package is masked with a tape such as a vacuum-compatible polyimide with an acrylic adhesive or a similar material in order to prevent adhesion to the lead wire portion finally attached to the PCB. It is preferable. This allows easier soldering in subsequent steps. A portion of the dielectric near the lead frame attachment location is selectively removed by etching, thermal degradation or laser ablation to make an electrical connection to the ground contact or ground shield layer. Similarly, a portion of the dielectric layer near the die connection pad is removed to allow ground connection. Following application of the metallization layer from above the dielectric layer, a structural ground connection is applied to form a ground shield. The preferred metal layer thickness should be selected in view of DC resistance and skin depth, and should be composed primarily of excellent conductors such as silver, copper or gold. For most applications, a coating thickness of 1 micron is adequate for functionality, but a thicker coating helps to reduce crosstalk between leads. These coatings can be applied to the defined areas by a combination of lithography or other masking methods and plating or other selectable coating methods. The package is completed by placing an overmold or lid on the die, followed by dicing (singulation) and inspection.

例1−クロストーク性能
図9(A)は、裸ワイヤボンド502、30オームの同軸線504および50オームの同軸線506について、周波数の関数としてクロストーク特性を比較するグラフ500である。両同軸リード線は、シールドされていない配線に比べて約25dB改善したクロストーク/絶縁特性を示す。この点において、本発明によって作製された不整合な同軸リード線でさえも、シールドされない裸リード線よりも優れている。
Example 1-Crosstalk Performance FIG. 9A is a graph 500 comparing the crosstalk characteristics as a function of frequency for a bare wire bond 502, a 30 ohm coaxial line 504, and a 50 ohm coaxial line 506. Both coaxial leads show about 25 dB improved crosstalk / insulation characteristics compared to unshielded wiring. In this regard, even mismatched coaxial leads made according to the present invention are superior to unshielded bare leads.

図9(B)は、裸ワイヤボンド512、514および50オームの同軸リード線516、518の、時間ドメインにおける挙動の比較を描いたグラフ510である。図9(A)に描かれた周波数結果と合致して、ノイズ電圧は12倍も低減され(520)(クロストーク/絶縁)、セトリング時間応答は7倍向上する(522)(帯域幅の増加を可能にする)。   FIG. 9B is a graph 510 depicting a comparison in the time domain of bare wire bonds 512, 514 and 50 ohm coaxial leads 516, 518. Consistent with the frequency results depicted in FIG. 9A, the noise voltage is reduced by a factor of 12 (520) (crosstalk / isolation) and the settling time response is improved by a factor of 7 (522) (increase in bandwidth) Possible).

図10(A)−図10(D)は、誘電体被覆と外側が接地接続された金属層を有する場合と、持たない場合とについて、それぞれシングルリード線およびディファレンシャルリード線に関するEM場振幅の空間振幅プロットを示す。図10(A)は、シングルエンドボンドワイヤ602の振幅プロット600を示す。図示されるように、ボンドワイヤのy軸に沿った一点におけるEM場振幅が顕著である。図10(B)は、シングルエンドマイクロ同軸線612の振幅プロット610を示す。明らかなように、同軸線は、裸リード線に比べて実質的に電磁放出が低減されている。   FIGS. 10A to 10D show the space of the EM field amplitude for the single lead and the differential lead, respectively, with and without the dielectric coating and the metal layer grounded on the outside. An amplitude plot is shown. FIG. 10A shows an amplitude plot 600 of a single end bond wire 602. As shown, the EM field amplitude at a point along the y-axis of the bond wire is significant. FIG. 10B shows an amplitude plot 610 of the single-ended microcoaxial line 612. As can be seen, the coaxial wire has substantially reduced electromagnetic emissions compared to the bare lead wire.

これは、ノイズ耐性を改善するために裸リード線で一般に使用される技法であるディファレンシャルペアに特に有効である。反対極性の信号で駆動される一対のリード線は、典型的にほぼ等しいノイズ環境にさらされる。これら2つの信号が差動的に一緒に印可されたとき、共通のノイズが打ち消される。しかし、多数の対のリード線のファインピッチ配置で起こりうるように、ノイズ環境が等しくない場合、隣り合うノイズ源が、より遠い隣のディファレンシャル対よりも、最も近い隣のディファレンシャル対に大きな信号を誘導することがある。このように、シールドされたマイクロ同軸対は、ノイズが信号線に到達する前に大きく減衰されるため、ノイズに対する耐性がかなり大きい。図10(C)は、ディファレンシャルマイクロ同軸線632の空間振幅プロット630を示す。プロットは、ほぼ完全なシールド、つまり、極く少量の電磁放射の放出を示している。   This is particularly useful for differential pairs, a technique commonly used with bare leads to improve noise immunity. A pair of leads driven with signals of opposite polarity are typically exposed to an approximately equal noise environment. When these two signals are applied differentially together, the common noise is canceled out. However, if the noise environment is unequal, as can occur with fine-pitch placement of many pairs of leads, adjacent noise sources will cause a larger signal to the nearest neighboring differential pair than to the farther neighboring differential pair. May induce. Thus, since the shielded micro coaxial pair is greatly attenuated before the noise reaches the signal line, the resistance against the noise is considerably high. FIG. 10C shows a spatial amplitude plot 630 of the differential micro coaxial line 632. The plot shows an almost perfect shield, ie the emission of very little electromagnetic radiation.

図11(A)および図11(B)に示されるように、半導体ダイパッケージングシステム1100は、多数に分離または重なり合ったグランドプレーンを有するように形成される。リード線1110、1112および1114は、リード線構造とグランドプレーンへの接続のために、低い電磁放出およびクロストークを有するように製造される。ダイ基板1102に実装されたダイ1120は、ダイ1120に要求される信号、電力または他の機能性のための多重接続パッド1122を有する。ダイ基板は、パッケージからの導電パスを、直接、または、導電リードフレーム、充填されたビア、導電トレース、二次レベル配線等によって提供される導電パッド1104を有してもよい。リード線1110、1112および1114は導電パッド1104に接続され、また図示するように、実質的に異なる長さを有していてもよい。   As shown in FIGS. 11A and 11B, the semiconductor die packaging system 1100 is formed to have a large number of ground planes that are separated or overlapped. Leads 1110, 1112 and 1114 are manufactured to have low electromagnetic emissions and crosstalk for connection to the lead structure and ground plane. The die 1120 mounted on the die substrate 1102 has multiple connection pads 1122 for signals, power or other functionality required for the die 1120. The die substrate may have conductive pads 1104 provided with conductive paths from the package directly or by conductive lead frames, filled vias, conductive traces, second level wiring, and the like. Leads 1110, 1112 and 1114 are connected to conductive pads 1104 and may have substantially different lengths as shown.

図11(A)に示された実施形態において、リード線1110、1112は内側コアと、第1のグランドプレーン1130に接続された外側金属層を有している。対照的に、リード線1114は、内側コアと、第1のグランドプレーン1130とは分離しており、別個の第2のグランドプレーン1132に接続された外側金属層を有している。同様に、図11(B)は、グランドプレーン1134と1136が物理的に重なり合っていること以外は、パッケージ1100の設計と等しいパッケージ1101を示している。しかし、両グランドプレーンは、誘電体被覆1138(部分的に取り除かれて示されている)がグランド1134と1136を互いに絶縁するために使用されるため、電気的には独立している。理解されるように、リード線1110、1112および1114は、その長さ方向に規定の直径の金属コアを有し、その金属コアは誘電体層と導電性の金属層で逐次被覆される。   In the embodiment shown in FIG. 11A, the lead wires 1110, 1112 have an inner core and an outer metal layer connected to the first ground plane 1130. In contrast, lead 1114 is separate from the inner core and first ground plane 1130 and has an outer metal layer connected to a separate second ground plane 1132. Similarly, FIG. 11B shows a package 1101 that is identical to the design of package 1100 except that ground planes 1134 and 1136 physically overlap. However, both ground planes are electrically independent because a dielectric coating 1138 (shown partially removed) is used to insulate the grounds 1134 and 1136 from each other. As will be appreciated, the leads 1110, 1112 and 1114 have a metal core of a defined diameter along their length, which is sequentially covered with a dielectric layer and a conductive metal layer.

付加的な誘電体および金属被覆が無い同サイズの裸リード線と比べて、リード線1110、1112および1114は放射がより少なく、(パッケージの)外部のEMIの感受性がより少なく、クロストークがより生じにくい。特定の実施形態において、開示されたような構成のリード線の優れた電気的特性により、実質的な長さは異なるが同じコア径を有するリード線は、裸ワイヤに対して実質的に同じノイズ低減を得ることが可能である。測定されるノイズ低減は、誘電体および被覆金属層を持たない裸リード線に比べて、5dBを超えて30dBまで多くなる。特定の実施形態において、EMIへの耐性はリード線の長さ方向の範囲にわたり有効であり、2つのリード線は同じ断面構造とインピーダンスを持つことができるが、一方のリード線は、同じEMI特性を持ちながらも他方のリード線の長さの10倍である。   Leads 1110, 1112 and 1114 are less radiated, less sensitive to external EMI (of the package) and more crosstalk than the same size bare lead without additional dielectric and metallization Hard to occur. In certain embodiments, due to the superior electrical properties of the lead configured as disclosed, leads having different core lengths but the same core diameter may have substantially the same noise relative to bare wire. A reduction can be obtained. The measured noise reduction is greater than 5 dB and up to 30 dB compared to a bare lead without a dielectric and coated metal layer. In certain embodiments, EMI resistance is effective over a range of lead lengths, and two leads can have the same cross-sectional structure and impedance, while one lead has the same EMI characteristics. Is 10 times the length of the other lead wire.

例2、例3、例4−クロストーク性能
例2−図12は、2つのグランドプレーン1200、1202を有する実施形態の一例を示し、両方とも、両リード線端部での接続を可能にするためにパッケージ基板1204からダイ1206に延出している。
Example 2, Example 3, Example 4—Crosstalk Performance Example 2 FIG. 12 shows an example of an embodiment having two ground planes 1200, 1202, both allowing connection at both lead ends. For this purpose, it extends from the package substrate 1204 to the die 1206.

例3−図13は、2つのグランドプレーンがそれぞれRFグランドシールド1300とDC電力グランドシールド1302とを形成する実施形態の一例を示す。   Example 3 FIG. 13 shows an example of an embodiment in which two ground planes form an RF ground shield 1300 and a DC power ground shield 1302, respectively.

例4−別の実施形態において、多数インピーダンス配線は、上記のプロセスの変形例によって実現される。ダイを支持する基板が、全パッケージとデバイスパッドの配線用に、0.7ミリのワイヤで適宜ワイヤボンド接合されてもよい。得られるパッケージ組立品は、パリレンC誘電体の1.31ミクロンの被覆を受ける。パッケージ上の電力用接地接続、および、デバイス上の電力接地接続に対応するビアを空けるプロセスが実行される。電力配線とそれらに関連する接地に関係する領域にのみ金属を形成する第1の選択的金属被覆プロセスが実行される。この選択的金属被覆化は、物理的マスキング、リソグラフィーまたは他の選択的プロセスによって実現することができる。このようにして、完全な5オーム同軸配線が形成される。この場合、誘電体の第2の被覆が被着されて、合計26.34ミクロンの誘電体厚が実現される。信号線に求められる全接地に第2のビアプロセスが実行される。このステップは、必要であれば、電源接地への接続を有してもよい。50オーム線用の接地シールドを形成するために第2の金属被覆化が実行される。このようにして、電力と信号線とのグランドプレーンを別に切り離したオプションで、5オームと50オームの組み合わせの配線が実現される。   Example 4-In another embodiment, multiple impedance wiring is realized by a variation of the above process. The substrate supporting the die may be appropriately wire bonded with 0.7 mm wire for wiring of all packages and device pads. The resulting package assembly receives a 1.31 micron coating of Parylene C dielectric. A process is performed to open a power ground connection on the package and a via corresponding to the power ground connection on the device. A first selective metallization process is performed that forms metal only in areas related to power wiring and their associated ground. This selective metallization can be achieved by physical masking, lithography or other selective processes. In this way, a complete 5 ohm coaxial wiring is formed. In this case, a second coating of dielectric is deposited to achieve a total dielectric thickness of 26.34 microns. The second via process is executed for all the grounds required for the signal lines. This step may have a connection to power ground if necessary. A second metallization is performed to form a ground shield for 50 ohm lines. In this way, a combination of 5 ohms and 50 ohms is realized with the option of separating the power and signal line ground planes separately.

本発明特有の好ましい実施形態について詳しく説明してきたが、前述の説明を考慮すれば、多くの別例、変更例および変形例が考えられることは当業者には明白である。したがって、添付の特許請求の範囲は、そのような別例、変更例および変形例を本発明の範囲および適用範囲内にあるものとして包含すると想定される。   While preferred embodiments specific to the present invention have been described in detail, it will be apparent to those skilled in the art that many alternatives, modifications, and variations are possible in light of the foregoing description. Accordingly, the appended claims are intended to cover such alternatives, modifications, and variations as fall within the scope and scope of the present invention.

特に、本発明は、優れたEMI性能を有するスタックドダイパッケージを対象とし、そのダイパッケージは、各ダイがそれぞれ複数の接続パッドを備える第1と第2のダイと、複数の接続要素を支持するダイ基板と、第1のダイからダイ基板上の複数の接続要素のうち1つに延出する第1のリード線であって、第1の金属コア径を有する第1の金属コア、第1の金属コアを被覆する第1の誘電体厚を有する第1の誘電体層、および、接地接続された外側金属層を有する第1のリード線と、第2のダイからダイ基板上の複数の接続要素のうち1つに延出する第2のリード線であって、第2の金属コア径を有する第2の金属コア、第2の金属コアを被覆する第2の誘電体厚を有する第2の誘電体層、および、接地接続された外側金属層を有する第2のリード線とを備え、第1と第2のリード線間のEMIおよびクロストークの感受性が低減される。   In particular, the present invention is directed to a stacked die package having excellent EMI performance, which die package supports first and second dies each having a plurality of connection pads, and a plurality of connection elements. A first lead wire extending from the first die to one of a plurality of connection elements on the die substrate, wherein the first metal core has a first metal core diameter; A first dielectric layer having a first dielectric thickness covering the metal core, a first lead having an outer metal layer connected to ground, and a plurality of on the die substrate from the second die. A second lead wire extending to one of the connecting elements, a second metal core having a second metal core diameter, and a second dielectric thickness covering the second metal core; A second dielectric layer, and a first layer having an outer metal layer connected to ground. And a lead wire, the sensitivity of EMI and cross talk between the first and second lead wire is reduced.

上記のダイパッケージにおいて、第1のリード線が第2のリード線に重なっている。   In the above die package, the first lead wire overlaps the second lead wire.

上記のダイパッケージにおいて、第1のリード線が第2のリード線の上にある。   In the die package described above, the first lead is on the second lead.

ダイ基板は、BGAパッケージの形成を可能にするために充填されたビアを有してもよい。   The die substrate may have vias filled to allow formation of a BGA package.

ダイ基板は、リードフレームパッケージを形成するためにリードフレームを有してもよい。   The die substrate may have a lead frame to form a lead frame package.

本発明は、ダイからダイへの接続と同様に、ダイから基板への接続を有する。   The present invention has a die to substrate connection as well as a die to die connection.

さらに、本発明は、複数の接続パッドを有するダイと、複数の接続要素を支持するダイ基板と、金属コアと、金属コアを被覆する誘電体層と、接地接続された外側金属層とをそれぞれが有する複数のリード線とを備え、金属コアを被覆する誘電体層と外側金属層とを持たないリード線に比べてクロストークノイズが5dB以上低減される優れたEMI性能を持つBGAパッケージを対象とする。   Furthermore, the present invention provides a die having a plurality of connection pads, a die substrate supporting a plurality of connection elements, a metal core, a dielectric layer covering the metal core, and an outer metal layer connected to ground. A BGA package with excellent EMI performance that has a crosstalk noise reduced by 5 dB or more compared to a lead wire that has a plurality of lead wires and has a dielectric layer covering the metal core and no outer metal layer And

さらに、本発明は、クロストークが低減されたディファレンシャルペアと、クロストークが低減されたクロスオーバー型の長ループ面外リード線を有する。   Furthermore, the present invention has a differential pair with reduced crosstalk and a crossover type long loop out-of-plane lead wire with reduced crosstalk.

さらに、本発明は、複数の接続パッドを有するダイと、複数の接続要素を支持するダイ基板と、第1のダイからダイ基板上の複数の接続要素のうち1つに延出する第1のリード線であって、第1の金属コア径を有する第1の金属コア、第1の金属コアを被覆する第1の誘電体厚を有する第1の誘電体層、および、外側金属層を有する第1のリード線と、第1のリード線の外側金属層に取り付けられた第1のグランドプレーンと、第2のダイからダイ基板上の複数の接続要素のうち1つに延出する第2のリード線であって、第2の金属コア径を有する第2の金属コア、第2の金属コアを被覆する第2の誘電体厚を有する第2の誘電体層を有する第2のリード線と、第2のリード線の外側金属層に取り付けられた第2のグランドプレーンと、を備えたダイパッケージを有する。   The present invention further includes a die having a plurality of connection pads, a die substrate supporting the plurality of connection elements, and a first die extending from the first die to one of the plurality of connection elements on the die substrate. A lead wire having a first metal core having a first metal core diameter, a first dielectric layer having a first dielectric thickness covering the first metal core, and an outer metal layer A first lead wire, a first ground plane attached to an outer metal layer of the first lead wire, and a second extending from the second die to one of a plurality of connecting elements on the die substrate. A second lead wire having a second metal core having a second metal core diameter and a second dielectric layer having a second dielectric thickness covering the second metal core And a second ground plane attached to the outer metal layer of the second lead wire. Having a die package.

上記のダイパッケージにおいて、第2のグランドプレーンは、仲介誘電体層が第1と第2のグランドプレーン間の電気絶縁を維持しながら、第1のグランドプレーンに重なり合っていてもよい。   In the die package described above, the second ground plane may overlap the first ground plane while the intermediary dielectric layer maintains electrical insulation between the first and second ground planes.

ダイパッケージは、BGAパッケージおよび/またはリードフレームパッケージの形態で構築されてもよい。
The die package may be constructed in the form of a BGA package and / or a lead frame package.

当業者には明らかであろう上記および他の目的は、EMI減衰のためのダイパッケージを対象とする本発明によって達成され、そのダイパッケージは、複数の接続パッドを有するダイと、複数の接続要素を支持するダイ基板と、第1の金属コア径を有する第1の金属コア、前記第1の金属コアを被覆する第1の誘電体厚を有する第1の誘電体層、および、前記第1の誘電体層を被覆する第1の外側金属層を有し、前記第1の外側金属層が第1のグランドプレーンに接続されている第1のリード線と、第2の金属コア径を有する第2の金属コア、前記第2の金属コアを被覆する第2の誘電体厚を有する第2の誘電体層、および、前記第2の誘電体層を被覆する第2の外側金属層を有し、前記第2の外側金属層が第2のグランドプレーンに接続されている第2のリード線とを備え、その結果、前記第1と第2のリード線は第1と第2のリード線の間のEMIおよびクロストークへの感受性を低減する。 The above and other objects that will be apparent to those skilled in the art are achieved by the present invention directed to a die package for EMI attenuation, the die package comprising a die having a plurality of connection pads and a plurality of connection elements. A die substrate that supports the first metal core, a first metal core having a first metal core diameter, a first dielectric layer having a first dielectric thickness covering the first metal core, and the first a dielectric layer having a first outer metal layer covering the first lead wire of the first outer metal layer that is connected to the first ground plane, a second metal core diameter A second metal core; a second dielectric layer having a second dielectric thickness covering the second metal core; and a second outer metal layer covering the second dielectric layer. and, of connection to the second outer metal layer is a second ground plane And a second lead Ru Tei, so that the first and second lead wires reduces the susceptibility to EMI and crosstalk between the first and second leads.

さらに、第1のリード線は、第1のダイからダイ基板上の複数の接続要素のうち1つに延出してもよい、および/または、第2のリード線は、第2のダイからダイ基板上の複数の接続要素のうち1つに延出してもよい。第2のグランドプレーンは、第1のグランドプレーンに重ね合わせてあってもよいし、重ね合わせていなくてもよい。重ね合わせの場合、電気絶縁を維持する仲介層が、第1のグランドプレーンと第2のグランドプレーンとの間に配置されてもよい。 Further , the first lead may extend from the first die to one of the plurality of connecting elements on the die substrate, and / or the second lead may be die from the second die. It may extend to one of a plurality of connecting elements on the substrate. The second ground plane may or may not overlap with the first ground plane. In the case of superposition, an intermediary layer that maintains electrical insulation may be disposed between the first ground plane and the second ground plane.

不必要なクロストークにつながる電磁場は、横並びのリード線だけで発生するわけではなく、スタック状の構成で互いに隣接しているリード線でも発生することがある。これは、図3に示すスタックドダイで現実化し、図3は、本明細書で説明するような誘電体層と導電金属層を被覆したリード線ではなく、裸ワイヤが使用された場合に、横並びまたは上下配置のリード線から容認できないクロストークが生じる例示的なリード線164a−dおよび166a−dを有するダイ162a−dを備えるスタックドダイパッケージ160を示している。同様に図4は、ダイからダイへ接続されるリード線174と、ダイから基板へ接されるリード線176を有するダイスタック170および172を示す。低減されたクロストークを有する別々に実装されたパッケージングシステム180、182内のダイからダイへ直接接続されるリード線178があってもよい。 Electromagnetic fields leading to unnecessary crosstalk are not generated only by side-by-side leads, but may also be generated by leads adjacent to each other in a stacked configuration. This is realized with the stacked die shown in FIG. 3, which is shown side-by-side when bare wires are used instead of leads coated with a dielectric layer and a conductive metal layer as described herein. or it shows a stacked die package 160 comprises a die 162a-d having exemplary leads 164a-d and 166a -d crosstalk unacceptable from lead in the vertical arrangement occurs. Similarly Figure 4 shows a lead 1 74 connected from the die to the die, the die stack 170 and 172 and a lead wire 176 which is Connect from the die to the substrate. There may be a lead wire 178 that is directly connected from the die of reduced within the packaging system 180, 182 that are separately mounted with crosstalk to die.

半導体ダイパッケージングに使用される誘電体被覆リード線は、異なる誘電体厚を有するように形成することができる。コア径と誘電体厚の両方を変えることができる。特定の実施形態において、被覆誘電体の組成も変えることができる。これは、例えば、優れた蒸気バリア、酸素分解耐性等を有する高性能誘電体が、低コストの誘電体材料の厚い層の上に薄く被着することを可能にする。図示される実施形態の別の態様において、リード線110、112および114(図2および3参照)は、内側コアと外側金属層にわたり異なる誘電体厚を有し、それが別個に異なるインピーダンスを提供する。例えば、リード線110はその長さに沿って規定の直径の金属コアを有してもよく、金属コアは薄い誘電体層と導電金属層で逐次被覆される。そのようなリード線110は、結果として得られる低インピーダンスと低静電容量が電力低下を減らすため、電力の伝送に適している。代替的に、リード線112は信号データの伝送に適したより厚い誘電体層を有し、一方で、リード線114は中間の厚さの誘電体層を有している。特定の実施形態において、開示されるリード線構造の優れた電気的特性により、実質的に長さが異なるが同じコア径を有するリード線が、50%以上異なる長さを持つにも拘らず、目標インピーダンスの10%以内での実質的に同じインピーダンスを持つことが可能である。例えば、リード線11は、長さがリード線110の2倍であるにも拘わらず、リード線110とほぼ同じインピーダンスを有することが可能である。特定の実施形態において、リード線の差がさらに大きい場合もあり、2つのリード線は同じ断面構造とインピーダンスとを有しているが、一方のリード線の長さは他方のリード線の長さの10倍である。 Dielectric coated leads used in semiconductor die packaging can be formed to have different dielectric thicknesses. Both core diameter and dielectric thickness can be varied. In certain embodiments, the composition of the coating dielectric can also be varied. This allows, for example, high performance dielectrics with excellent vapor barrier, oxygen decomposition resistance, etc. to be thinly deposited on a thick layer of low cost dielectric material. In another aspect of the illustrated embodiment, the leads 110, 112 and 114 (see FIGS. 2 and 3) have different dielectric thicknesses across the inner core and outer metal layer, which separately provide different impedances. To do. For example, the lead 110 may have a metal core of a defined diameter along its length, and the metal core is sequentially coated with a thin dielectric layer and a conductive metal layer. Such a lead 110 is suitable for power transmission because the resulting low impedance and low capacitance reduce power loss. Alternatively, lead 112 has a thicker dielectric layer suitable for transmission of signal data, while lead 114 has an intermediate thickness of dielectric layer. In certain embodiments, due to the superior electrical properties of the disclosed lead structure, lead wires having substantially different lengths but the same core diameter have different lengths by more than 50%, It is possible to have substantially the same impedance within 10% of the target impedance. For example, the leads 11 2, despite twice the lead wire 110 length, it is possible to have substantially the same impedance as the lead 110. In certain embodiments, the lead wire difference may be even greater, and the two lead wires have the same cross-sectional structure and impedance, but the length of one lead wire is the length of the other lead wire. 10 times.

これは、ノイズ耐性を改善するために裸リード線で一般に使用される技法であるディファレンシャルペア(622)に特に有効である(図10(C))。反対極性の信号で駆動される一対のリード線は、典型的にほぼ等しいノイズ環境にさらされる。これら2つの信号が差動的に一緒に印可されたとき、共通のノイズが打ち消される(620)。しかし、多数の対のリード線のファインピッチ配置で起こりうるように、ノイズ環境が等しくない場合、隣り合うノイズ源が、より遠い隣のディファレンシャル対よりも、最も近い隣のディファレンシャル対に大きな信号を誘導することがある。このように、シールドされたマイクロ同軸対は、ノイズが信号線に到達する前に大きく減衰されるため、ノイズに対する耐性がかなり大きい。図10()は、ディファレンシャルマイクロ同軸線632の空間振幅プロット630を示す。プロットは、ほぼ完全なシールド、つまり、極く少量の電磁放射の放出を示している。 This is particularly effective for the differential pair (622) , which is a technique commonly used with bare leads to improve noise immunity (FIG. 10C) . A pair of leads driven with signals of opposite polarity are typically exposed to an approximately equal noise environment. When these two signals are applied differentially together, the common noise is canceled (620) . However, if the noise environment is unequal, as can occur with fine-pitch placement of many pairs of leads, adjacent noise sources will cause a larger signal to the nearest neighboring differential pair than to the farther neighboring differential pair. May induce. Thus, since the shielded micro coaxial pair is greatly attenuated before the noise reaches the signal line, the resistance against the noise is considerably high. FIG. 10 ( D ) shows a spatial amplitude plot 630 of the differential micro coaxial line 632. The plot shows an almost perfect shield, ie the emission of very little electromagnetic radiation.

Claims (18)

複数の接続パッドを有するダイ(152;120;162a−d;170;416)と、
複数の接続要素を支持するダイ基板(154;102;418)と、
第1の金属コア径を持つ第1の金属コア、前記第1の金属コアを被覆する第1の誘電体厚を持つ第1の誘電体層、および、前記第1の誘電体層を被覆する第1の外側金属層を有し、前記第1の外側金属層が接地または第1のグランドプレーンに接続された第1のリード線(156;110;164a;166a;176;412)と、
第2の金属コア径を持つ第2の金属コア、前記第2の金属コアを被覆する第2の誘電体厚を持つ第2の誘電体層、および、前記第2の誘電体層を被覆する第2の外側金属層を有し、前記第2の外側金属層が接地または第2のグランドプレーンに接続された第2のリード線(156;112;164b;166b;176;414)と、を備え、
前記第1のリード線と前記第2のリード線との間のEMIおよびクロストークへの感受性が低減されるダイパッケージ(150;100;160;180;182;410;440;1100)。
A die (152; 120; 162a-d; 170; 416) having a plurality of connection pads;
A die substrate (154; 102; 418) supporting a plurality of connecting elements;
A first metal core having a first metal core diameter; a first dielectric layer having a first dielectric thickness covering said first metal core; and covering said first dielectric layer A first lead (156; 110; 164a; 166a; 176; 412) having a first outer metal layer, the first outer metal layer being connected to ground or a first ground plane;
A second metal core having a second metal core diameter; a second dielectric layer having a second dielectric thickness covering said second metal core; and covering said second dielectric layer A second lead (156; 112; 164b; 166b; 176; 414) having a second outer metal layer, the second outer metal layer being connected to ground or a second ground plane; Prepared,
A die package (150; 100; 160; 180; 182; 410; 440; 1100) with reduced susceptibility to EMI and crosstalk between the first lead and the second lead.
前記ダイパッケージは、第1のダイと第2のダイとを有し、前記第1のダイと前記第2のダイは、それぞれ複数の接続パッドを有し、
前記第1のリード線は、前記第1のダイから前記ダイ基板上の前記複数の接続要素のうちの1つに延出するか、または、前記第2のダイの前記複数の接続パッドのうちの1つに延出し、前記第2のリード線は、前記第2のダイから前記ダイ基板上の前記複数の接続要素のうちの1つに延出、または、前記第1のダイの前記複数の接続パッドのうちの1つに延出することを特徴とする請求項1に記載のダイパッケージ。
The die package has a first die and a second die, and each of the first die and the second die has a plurality of connection pads,
The first lead wire extends from the first die to one of the plurality of connection elements on the die substrate, or of the plurality of connection pads of the second die And the second lead extends from the second die to one of the plurality of connecting elements on the die substrate, or the plurality of the first die. The die package of claim 1, wherein the die package extends to one of the connection pads.
前記ダイパッケージは、スタックドダイパッケージであることを特徴とする請求項2に記載のダイパッケージ。   The die package according to claim 2, wherein the die package is a stacked die package. 前記第1のリード線(1110、1112)は、第1のダイから前記ダイ基板(1102)上の前記複数の接続要素のうちの1つに延出し、前記第2のリード線(1114)は、第2のダイから前記ダイ基板(1102)上の前記複数の接続要素のうちの1つに延出し、前記第1のグランドプレーン(1130、1136)は、前記第1の外側金属層に取り付けられ、前記第2のグランドプレーン(1132、1134)は、前記第2の外側金属層に取り付けられる請求項1から3のいずれかに記載のダイパッケージ(1100)。   The first lead (1110, 1112) extends from a first die to one of the plurality of connection elements on the die substrate (1102), and the second lead (1114) is Extending from the second die to one of the plurality of connection elements on the die substrate (1102), the first ground plane (1130, 1136) being attached to the first outer metal layer The die package (1100) according to any of claims 1 to 3, wherein the second ground plane (1132, 1134) is attached to the second outer metal layer. 前記第2のグランドプレーン(1134)は、好ましくは仲介層(1138)が前記第1のグランドプレーンと前記第2のグランドプレーンとの間の電気絶縁を維持しながら前記第1のグランドプレーン(1136)に重なり合っている請求項4に記載のダイパッケージ(1100)。   The second ground plane (1134) is preferably configured such that the intermediate layer (1138) maintains the electrical insulation between the first ground plane and the second ground plane, while the first ground plane (1136) is maintained. The die package (1100) of claim 4, wherein 前記第1の金属コア径は、前記第2の金属コア径とは異なる請求項1から5のいずれか一項に記載のダイパッケージ。   The die package according to claim 1, wherein the first metal core diameter is different from the second metal core diameter. 前記第1の金属コア径は、前記第2の金属コア径と同じである請求項1から5のいずれか一項に記載のダイパッケージ。   The die package according to claim 1, wherein the first metal core diameter is the same as the second metal core diameter. 前記第1の誘電体厚は、前記第2の誘電体厚とは異なる請求項1から7のいずれか一項に記載のダイパッケージ。   The die package according to claim 1, wherein the first dielectric thickness is different from the second dielectric thickness. 前記第1の誘電体厚は、前記第2の誘電体厚と同じである請求項1から7のいずれか一項に記載のダイパッケージ。   The die package according to claim 1, wherein the first dielectric thickness is the same as the second dielectric thickness. 前記ダイ基板は、BGAパッケージの形成を可能にする充填されたビアを有する請求項1から9のいずれか一項に記載のダイパッケージ。   10. The die package according to any one of claims 1 to 9, wherein the die substrate has a filled via that allows formation of a BGA package. 前記ダイ基板は、リードフレームパッケージを形成するリードフレームを有する請求項1から9のいずれか一項に記載のダイパッケージ。   The die package according to any one of claims 1 to 9, wherein the die substrate includes a lead frame that forms a lead frame package. 前記第1のリード線は、前記第2のリード線に交差する、および/または、前記第2のリード線の上にある請求項1から11のいずれか一項に記載のダイパッケージ。   The die package according to any one of claims 1 to 11, wherein the first lead wire intersects the second lead wire and / or is on the second lead wire. 前記第1のリード線は、第1の長さと第1のインピーダンスとを有し、前記第2のリード線は、第2の長さと第2のインピーダンスとを有し、
前記第1の長さは前記第2の長さとは異なり、および/または、前記第1のインピーダンスは前記第2のインピーダンスとは異なる請求項1から12のいずれか一項に記載のダイパッケージ。
The first lead has a first length and a first impedance; the second lead has a second length and a second impedance;
The die package according to any one of claims 1 to 12, wherein the first length is different from the second length and / or the first impedance is different from the second impedance.
前記第1の金属コアおよび/または前記第2の金属コアは、誘電体層と導電金属層とで逐次被覆される請求項1から13のいずれか一項に記載のダイパッケージ。   The die package according to any one of claims 1 to 13, wherein the first metal core and / or the second metal core are sequentially covered with a dielectric layer and a conductive metal layer. 前記リード線は、ダイからダイへの接続および/またはダイから基板への接続のための電気的伝達を提供する請求項1から14のいずれか一項に記載のダイパッケージ。   15. A die package according to any one of the preceding claims, wherein the lead wire provides electrical communication for die-to-die connection and / or die-to-substrate connection. 複数の前記リード線は、少なくとも1つのディファレンシャルペアを有する請求項1から15のいずれか一項に記載のダイパッケージ。   The die package according to any one of claims 1 to 15, wherein the plurality of lead wires have at least one differential pair. 複数の前記リード線は、クロストークが低減された、クロスオーバー型の長ループ面外リード線を有する請求項1から16のいずれか一項に記載のダイパッケージ。   The die package according to claim 1, wherein the plurality of lead wires have crossover type long loop out-of-plane lead wires with reduced crosstalk. 請求項1から17のいずれか一項に記載のダイパッケージを有する優れたEMI性能のBGAパッケージであって、前記ダイパッケージは、複数のリード線を有し、それぞれの前記リード線は、金属コアと、前記金属コアを被覆する誘電体層と、接地接続された外側金属層とを有し、前記金属コアを被覆する外側金属層を持つ誘電体層がないリード線よりもクロストークノイズが少なくとも5dB低減されるBGAパッケージ。   18. A BGA package with excellent EMI performance comprising the die package according to any one of claims 1 to 17, wherein the die package has a plurality of lead wires, each lead wire having a metal core. And a dielectric layer that covers the metal core, and an outer metal layer that is connected to ground, and at least crosstalk noise is lower than a lead wire that does not have a dielectric layer that has an outer metal layer that covers the metal core. BGA package reduced by 5 dB.
JP2016522338A 2013-07-03 2014-07-02 Die package with low electromagnetic interference wiring Active JP6285021B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361842944P 2013-07-03 2013-07-03
US201361842943P 2013-07-03 2013-07-03
US61/842,944 2013-07-03
US61/842,943 2013-07-03
PCT/EP2014/001825 WO2015000596A1 (en) 2013-07-03 2014-07-02 Die package with low electromagnetic interference interconnection

Publications (2)

Publication Number Publication Date
JP2016524338A true JP2016524338A (en) 2016-08-12
JP6285021B2 JP6285021B2 (en) 2018-02-28

Family

ID=51134004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016522338A Active JP6285021B2 (en) 2013-07-03 2014-07-02 Die package with low electromagnetic interference wiring

Country Status (9)

Country Link
US (1) US9824997B2 (en)
EP (1) EP3017471B1 (en)
JP (1) JP6285021B2 (en)
KR (1) KR101812594B1 (en)
CN (1) CN105474388B (en)
CA (1) CA2915900C (en)
HK (1) HK1217569A1 (en)
TW (1) TWM509429U (en)
WO (1) WO2015000596A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019181373A1 (en) * 2018-03-22 2019-09-26 日本電信電話株式会社 Wire bonding structure

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101815754B1 (en) * 2016-03-10 2018-01-08 앰코 테크놀로지 코리아 주식회사 Semiconductor device
JP2018201138A (en) * 2017-05-29 2018-12-20 セイコーエプソン株式会社 Electronic component, and electronic equipment
CN110088893B (en) * 2017-08-02 2023-10-03 住友电工光电子器件创新株式会社 Method for assembling semiconductor device
WO2019241737A1 (en) * 2018-06-14 2019-12-19 Caprice Gray Haley Coaxial wire
US11676922B2 (en) * 2019-10-28 2023-06-13 Qualcomm Incorporated Integrated device comprising interconnect structures having an inner interconnect, a dielectric layer and a conductive layer
CN112652886B (en) * 2020-12-15 2022-10-25 江苏惠通集团有限责任公司 Lead structure and forming method thereof

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0412538A (en) * 1990-05-01 1992-01-17 Hitachi Ltd Semiconductor device
JPH05508057A (en) * 1991-03-26 1993-11-11 トムソン―セーエスエフ Methods of making coaxial connections of electronic components and component packages containing such connections
JPH0613421A (en) * 1992-02-25 1994-01-21 American Teleph & Telegr Co <Att> Integrated circuit device
JPH06120286A (en) * 1992-10-02 1994-04-28 Matsushita Electron Corp Semiconductor device
JPH0766236A (en) * 1993-08-31 1995-03-10 Tanaka Denshi Kogyo Kk Multilayer-coated bonding wire for semiconductor element and semiconductor device
US5625235A (en) * 1995-06-15 1997-04-29 National Semiconductor Corporation Multichip integrated circuit module with crossed bonding wires
US20020140112A1 (en) * 2001-03-30 2002-10-03 Pon Harry Q. Insulated bond wire assembly process technology for integrated circuits
US20060185892A1 (en) * 2005-01-19 2006-08-24 Volker Guengerich Semiconductor device with micro connecting elements and method for producing the same
JP2008227126A (en) * 2007-03-13 2008-09-25 National Institute Of Advanced Industrial & Technology Fine coaxial wire, its manufacturing method, and semiconductor device
US20090159320A1 (en) * 2007-12-19 2009-06-25 Bridgewave Communications, Inc. Low Cost High Frequency Device Package and Methods
US8377749B1 (en) * 2009-09-15 2013-02-19 Applied Micro Circuits Corporation Integrated circuit transmission line

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5921818A (en) * 1997-06-23 1999-07-13 Lucent Technologies Inc. Low crosstalk electrical connector
US20020079572A1 (en) * 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US6770822B2 (en) * 2002-02-22 2004-08-03 Bridgewave Communications, Inc. High frequency device packages and methods
JP4316607B2 (en) * 2006-12-27 2009-08-19 株式会社東芝 ANTENNA DEVICE AND WIRELESS COMMUNICATION DEVICE
JP2009111010A (en) * 2007-10-26 2009-05-21 Renesas Technology Corp Semiconductor device and method of manufacturing the same
TWI484616B (en) * 2011-10-06 2015-05-11 Adl Engineering Inc Package module with emi shielding
JP5752026B2 (en) * 2011-12-16 2015-07-22 ルネサスエレクトロニクス株式会社 Semiconductor device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0412538A (en) * 1990-05-01 1992-01-17 Hitachi Ltd Semiconductor device
JPH05508057A (en) * 1991-03-26 1993-11-11 トムソン―セーエスエフ Methods of making coaxial connections of electronic components and component packages containing such connections
JPH0613421A (en) * 1992-02-25 1994-01-21 American Teleph & Telegr Co <Att> Integrated circuit device
JPH06120286A (en) * 1992-10-02 1994-04-28 Matsushita Electron Corp Semiconductor device
JPH0766236A (en) * 1993-08-31 1995-03-10 Tanaka Denshi Kogyo Kk Multilayer-coated bonding wire for semiconductor element and semiconductor device
US5625235A (en) * 1995-06-15 1997-04-29 National Semiconductor Corporation Multichip integrated circuit module with crossed bonding wires
US20020140112A1 (en) * 2001-03-30 2002-10-03 Pon Harry Q. Insulated bond wire assembly process technology for integrated circuits
US20060185892A1 (en) * 2005-01-19 2006-08-24 Volker Guengerich Semiconductor device with micro connecting elements and method for producing the same
JP2008227126A (en) * 2007-03-13 2008-09-25 National Institute Of Advanced Industrial & Technology Fine coaxial wire, its manufacturing method, and semiconductor device
US20090159320A1 (en) * 2007-12-19 2009-06-25 Bridgewave Communications, Inc. Low Cost High Frequency Device Package and Methods
US8377749B1 (en) * 2009-09-15 2013-02-19 Applied Micro Circuits Corporation Integrated circuit transmission line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019181373A1 (en) * 2018-03-22 2019-09-26 日本電信電話株式会社 Wire bonding structure

Also Published As

Publication number Publication date
HK1217569A1 (en) 2017-01-13
CN105474388B (en) 2018-06-19
CA2915900C (en) 2020-01-21
EP3017471B1 (en) 2020-03-11
CN105474388A (en) 2016-04-06
JP6285021B2 (en) 2018-02-28
US9824997B2 (en) 2017-11-21
WO2015000596A1 (en) 2015-01-08
EP3017471A1 (en) 2016-05-11
KR101812594B1 (en) 2018-01-30
KR20160029760A (en) 2016-03-15
TWM509429U (en) 2015-09-21
CA2915900A1 (en) 2015-01-08
US20160379954A1 (en) 2016-12-29

Similar Documents

Publication Publication Date Title
JP6285021B2 (en) Die package with low electromagnetic interference wiring
JP6556707B2 (en) Thermal insulation structure for high bandwidth wiring
JP2016524336A (en) Die packaging with fully or partially deposited dielectric leads
JP6450378B2 (en) Electronic equipment having leads with selectively modified electrical characteristics
JP6457505B2 (en) Substrateless die package having wire coated with dielectric and metal and method of manufacturing the same
KR102038022B1 (en) Coated bond wires for die packages and methods of manufacturing said coated bond wires
JP6395822B2 (en) Mixed impedance bond wire bonding and manufacturing method thereof

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160511

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160722

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170529

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170613

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170906

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20171107

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171221

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180116

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180131

R150 Certificate of patent or registration of utility model

Ref document number: 6285021

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250