US8307166B2 - Information processing program, information processing device and information processing method - Google Patents

Information processing program, information processing device and information processing method Download PDF

Info

Publication number
US8307166B2
US8307166B2 US12/725,980 US72598010A US8307166B2 US 8307166 B2 US8307166 B2 US 8307166B2 US 72598010 A US72598010 A US 72598010A US 8307166 B2 US8307166 B2 US 8307166B2
Authority
US
United States
Prior art keywords
program
shared area
memory
management
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US12/725,980
Other languages
English (en)
Other versions
US20100250866A1 (en
Inventor
Hisashi Kojima
Masahiro Nakada
Tetsuya Shioda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIODA, TETSUYA, KOJIMA, HISASHI, NAKADA, MASAHIRO
Publication of US20100250866A1 publication Critical patent/US20100250866A1/en
Application granted granted Critical
Publication of US8307166B2 publication Critical patent/US8307166B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Definitions

  • the above-described technique of allowing exclusive access to the shared memory making use of a lock function of the OS generally needs cooperation of the client and server processes, so that the technique lacks efficacy if the client process contains malicious code.
  • an information processing device includes: a memory; a management memory for storing first virtual addresses used by the first program, second virtual addresses used by the second program and management information indicative of association between first and second virtual addresses and physical addresses of the memory; and a processor for executing the first, the second and a management programs, the management program including: receiving a request to assign a shared area to be shared by the first and second programs from the second program; determining a physical address of the shared area corresponding to one of the first and one of the second virtual addresses; transmitting a notification of data writing by the first program to the second program; locking the shared area so as to prevent the second program from writing data after the notification; and unlocking the shared area after the second program has read data from the shared area.
  • FIG. 1 is a drawing illustrating a configuration of an information processing device of a first embodiment
  • FIG. 2A and FIG. 2B are drawings illustrating a process flow executed by the information processing device of the first embodiment
  • FIG. 3 is a drawing illustrating an exemplary configuration of a page table in the first embodiment.
  • FIG. 4 is a drawing illustrating an exemplary system call which requests assignment of the shared memory in the first embodiment
  • FIG. 5 is a drawing illustrating an exemplary configuration of memory management information in the first embodiment
  • FIG. 6 is a drawing illustrating an exemplary system call used for notifying a virtual address in the first embodiment
  • FIG. 7 is a drawing illustrating an exemplary system call used for notifying writing of data into the shared memory in the first embodiment
  • FIG. 8 is a drawing illustrating an exemplary system call used for requesting access control with respect to the shared memory in the first embodiment
  • FIG. 9 is a drawing illustrating an exemplary system call used for notifying the end of process in the first embodiment.
  • FIG. 10 is a drawing illustrating an exemplary system call used for releasing the shared memory in the first embodiment.
  • operation for example, inter-process operation
  • a so-called shared memory shared area
  • the information processing device of the first embodiment is explained below.
  • an access restriction request with respect to the shared memory issued by a program on the user side of the shared memory (program A, for example) is accepted, whether the access restriction request is issued by a program on the owner side of the shared memory (program B, for example) or not is judged. If the access restriction request is judged as being issued by the program on the owner side of the shared memory (program B, for example), access to the shared memory by the program on the user side of the shared memory (program A, for example) is restricted.
  • the information processing device of the first embodiment will more specifically be explained below.
  • FIG. 1 is a drawing illustrating a configuration of the information processing device of the first embodiment.
  • an information processing device 200 of the first embodiment has a CPU 210 , a storage 220 , a register 230 , an MMU 240 and a memory 250 .
  • the CPU 210 has an internal memory for storing a predetermined control program, programs which specify various processing procedures, and necessary data, and executes various processes such as control of the information processing device, data calculation, and data processing.
  • the CPU 210 also has execution modes such as a privileged mode capable of operating the MMU 240 , an unprivileged mode incapable of operating the MMU 240 , and so forth, and can restrict memory access in the unprivileged mode. Any programs running in the unprivileged mode cannot enter the privileged mode without being authorized by the program running in the privileged mode.
  • the storage 220 stores data, programs and so forth.
  • the register 230 holds the states of calculation and processing executed by the CPU 210 .
  • the MMU (Memory Management Unit) 240 manages the memory 250 .
  • the memory 250 allows the memory management program, the program A, the program B and so forth to be loaded thereon.
  • the memory 250 also contains a shared memory, memory management information, memory management program page table, program A page table, program B page table, program A non-shared memory, and program B non-shared memory.
  • the memory management program controls access to the shared memory by the program A and program B.
  • the memory management program functions as a process of executing processing with respect to the memory management, after being read from the memory 250 by the CPU 210 and loaded on the memory 250 . Specific contents of processing by the memory management program will be explained later in relation to the process flow ( FIG. 2A and FIG. 2B ) by the information processing device 200 .
  • the program A and the program B run in the unprivileged mode, and have virtual address spaces corresponded to physical address regions different from each other.
  • the shared memory is a common physical address region to which a part of a virtual address space owned by the program A and a part of a virtual address space owned by program B correspond.
  • the memory management information is information for managing the memory 250 .
  • the memory management program page table, the program A page table and the program B page table are tables used for mutual conversion between the virtual address and the physical address.
  • the program A non-shared memory is a memory used solely by the program A.
  • the program B non-shared memory is a memory used solely by the program B.
  • FIG. 2A and FIG. 2B are drawings illustrating a process flow by the information processing device of the first embodiment.
  • the description below will explain the process flow, mainly for the individual programs (memory management program, program A and program B) running on the information processing device 200 .
  • the individual programs function as processes, after being read out from the memory 250 by the CPU 210 and loaded on the memory 250 .
  • the program A is initiated (step S 1 ).
  • a program file of the program A is stored in a data storage device such as the storage 220 , and executed after being loaded on the memory 250 by the CPU 210 .
  • the program A herein is now assumed to be data on the client side, and is a program that is not trustworthy from the viewpoint of the program B.
  • the program A is given a specific process ID by the OS (Operating System) running on the CPU 210 . Also a page table for program A is prepared in the memory 250 .
  • the program B is initiated (step S 2 ).
  • the program B is, for example, on the server side which receives data, and is given a specific process ID by the OS (Operating System) running on the CPU 210 .
  • a page table for the program B is prepared in the memory 250 .
  • the page tables for the programs A and B typically store virtual addresses, physical addresses, and information representing attributes of the access control with respect to the virtual addresses, in a correlated manner.
  • FIG. 3 is a drawing illustrating an exemplary configuration of the page table in the first embodiment.
  • the program B issues a request to the memory management program to assign the shared memory to the program A (step S 3 ).
  • the request from the program B to the memory management program herein is executed typically using a system call of a general OS, typically as illustrated in FIG. 4 .
  • FIG. 4 is a drawing illustrating an exemplary system call which requests assignment of the shared memory in the first embodiment.
  • the shared memory is embodied by making a part of the memory region assigned to the program B accessible also by the program A.
  • the program B issues a request to the memory management program to assign the shared memory to the program A
  • the program B specifies a virtual address and so forth of a region of the memory which is desired to be shared, as an argument of the system call. Also an attribute of the access control, such that whether the shared memory is made readable/writable or only writable by the program A, is selected.
  • the memory management program Upon receiving the request by the program B, the memory management program rewrites the page table of the program A, to thereby make the shared memory readable/writable (step S 4 ).
  • a physical address of the memory region is acquired on the basis of the page table of the program B, and a preliminarily acquired physical address is added to the page table of the program A.
  • the memory management program assigns an appropriate virtual address corresponding to the thus-added physical address, and adds the attributes of the access control.
  • the memory management program Upon completion of addition of the attributes of the access control, the memory management program then returns the virtual address for the program A as a return value of the system call to the program B.
  • the memory management program also records that the program B prepared the shared memory for the program A, in memory management information in the memory 250 .
  • the memory management information stores, typically as illustrated in FIG. 5 , the process ID (for example, process ID given to the program B) of the owner of the shared memory, the virtual address, the size, the process ID (for example, process ID given to the program A) of the user, and the virtual address in a correlated manner.
  • FIG. 5 is a drawing illustrating an exemplary configuration of the memory management information in the first embodiment.
  • the program B Upon rewriting of the page table for the program A by the memory management program, the program B notifies the program A of the virtual address (shared memory), accepted as a return value of the system call from the memory management program, to the program A by a system call (step S 5 ).
  • FIG. 6 illustrates an exemplary system call used when the program B notifies the program A of the virtual address.
  • FIG. 6 is a drawing illustrating an exemplary system call used for notifying the virtual address in the first embodiment.
  • the program A Upon being notified of the virtual address (shared memory), the program A writes data into the shared memory (step S 6 ), and notifies the program B of completion of the writing of data into the shared memory (step S 7 ).
  • FIG. 7 illustrates an exemplary system call for notifying the writing of data into the shared memory, from the program A to the program B.
  • FIG. 7 is a drawing illustrating an exemplary system call used for notifying the writing of data into the shared memory in the first embodiment.
  • FIG. 8 illustrates an exemplary system call issued by the program B for requesting the memory management program to execute access control with respect to access to the shared memory by the program A.
  • FIG. 8 is a drawing illustrating an exemplary system call used for requesting access control with respect to the shared memory in the first embodiment.
  • the memory management program Upon being requested by the program B, the memory management program checks whether the request for the access control with respect to the access to the shared memory by the program A was issued by the program B, which is the owner of the shared memory (step S 9 ).
  • the memory management program refers to the memory management information ( FIG. 5 ) of the program B which is the requester of the access control, and then checks whether the process ID of the program B contained in the system call of the access control request, and the specified virtual address are contained as the owner of the shared memory in the memory management information.
  • step S 9 the memory management program rewrites the page table for the program A, and sets write lock (or read/write lock) to the shared memory (step S 10 ).
  • the program B Upon completion of the re-writing of the page table for the program A by the memory management program, the program B reads the shared memory, and executes necessary processing operations (for example, output of text data and picture data, replay of movie data, and so forth) (step S 11 ).
  • the program B Upon completion of the processing operations, the program B requests the memory management program to recover the attributes of the access control with respect to access to the shared memory by the program A so as to allow reading/writing, using the system call (see FIG. 7 , for example) (step S 12 ).
  • the memory management program checks, similarly to as in step S 9 described above, whether the request of access control with respect to access to the shared memory by the program A was issued by the program B, which is the owner of the shared memory (step S 13 ).
  • step S 13 If it was found by the check that the request of access control with respect to access to the shared memory by the program A was issued by the program B, which is the owner of the shared memory (YES in step S 13 ), the memory management program rewrites the page table for the program A, and sets the shared memory readable/writable (step S 14 ).
  • the program B Upon completion of the re-writing of the page table for the program A by the memory management program, the program B notifies the program A of the end of processing using the system call (step S 15 ).
  • FIG. 9 illustrates an exemplary system call issued by the program B for notifying the program A of the end of processing.
  • FIG. 9 is a drawing illustrating an exemplary system call used for notifying the end of processing in the first embodiment.
  • the program A Upon being notified of the end of processing, the program A reads data from the shared memory, and executes necessary processing operations (step S 16 ).
  • FIG. 10 illustrates an exemplary system call used for requesting release of the shared memory.
  • FIG. 10 is a drawing illustrating an exemplary system call used for requesting release of the shared memory in the first embodiment.
  • the memory management program Upon being requested by the program B, the memory management program checks, in a manner similar to steps S 9 and S 13 described above, whether the request of release of the shared memory was issued by the program B, which is the owner of the shared memory (step S 18 ).
  • step S 18 If it was found by the check that the request of release of the shared memory was issued by the program B, which is the owner of the shared memory (YES in step S 18 ), the memory management program rewrites, in a manner similar to step S 10 described above, the page table for the program A, and sets write lock (or read/write lock) to the shared memory (step S 19 ).
  • step S 9 if it was found by the check that the request of access control with respect to access to the shared memory by the program A was not issued by the program B, which is the owner of the shared memory (NO in step S 9 ), the memory management program returns an error to indicate an illegal request (step S 20 ), and terminates the processing.
  • step S 13 if it was found by the check that the request of access control with respect to access to the shared memory by the program A was issued but not by the program B, which is the owner of the shared memory (NO in step S 13 ), the memory management program returns an error to indicate an illegal request (step S 21 ), and terminates the processing.
  • step S 18 if it was found by the check that the request of release of the shared memory was issued but not by the program B, which is the owner of the shared memory (NO in step S 18 ), the memory management program returns an error to indicate an illegal request (step S 22 ), and terminates the processing.
  • the access restriction request upon receiving the access restriction request with respect to access to the shared memory by the program on the user side of the shared memory (for example, program A), whether the access restriction request was issued by the program on the owner side of the shared memory (for example, program B) or not is judged. If the access restriction request is found to be issued by the program on the owner side of the shared memory (for example, program B), access to the shared memory by the program on the user side of the shared memory (for example, program A) is restricted.
  • efficient access control may be achieved, while maintaining data integrity (while preventing overwriting of the shared memory by the program A during processing by the program B).
  • the above-described program B may safely process data written by the program A (for example, client process) into the shared memory.
  • the first embodiment is efficient in terms of processing speed and memory consumption. As has been described above, data safety may be improved while maintaining the performance of the information processing device 200 .
  • OS determine access control with respect to a shared memory in a static manner, allowing no transition of the state of access control once the shared memory is set between the processes. Also no function of allowing forced transition of the state of access control with respect to the shared memory from one process to the other process has been achieved.
  • access control with respect to a shared memory may be achieved seemingly in a dynamic manner, and thereby efficient access control may be achieved.
  • the first embodiment which has been described in the above referring to the case where memory management program enables access control of the program by re-writing the attributes of the access control in the program page table, is not limited thereto.
  • the memory management program may re-write the page table, so that the physical address, which corresponds to the virtual address space of the program to be controlled in the access control, may have an address different from that of the physical address of the shared memory.
  • This strategy raises an effect of preventing data written in the shared memory from being re-written, just like re-writing of the attributes of the access control.
  • the individual constituents of the information processing device 200 illustrated in FIG. 1 are those conceptually representing the functions thereof, so that it is not always necessary to physically configure the information processing device 200 as illustrated in the drawing. In other words, specific embodiments of distribution/integration of the information processing device 200 are not limited to that illustrated in the drawing.
  • the CPU 210 may be distributed on a functional or physical basis, depending on the details of processing.
  • the entire portion or a part of the information processing device 200 may be configured by arbitrary units which are functionally or physically distributed or, integrated, depending on various loads and states of use.
  • the individual process functions executed by the information processing device 200 may be embodied by the CPU 210 and by a program analyzed and executed by the CPU 210 , or may be embodied as hardware based on wired logic.
  • Information processing information as described below may be embodied by the information processing device 200 previously explained in the first embodiment.
  • an information processing method which includes a shared region generation procedure which makes, upon being requested by a first program (for example, program A), a part of a virtual address space assigned to the first program (for example, program A) and a part of a virtual address space assigned to a second program correspond to a common physical address space, to thereby generate a shared region accessible by the first program and the second program (see step S 3 and step S 4 in FIG. 2A ); a request judgment procedure which judges, upon receiving an access restriction request with respect to the shared region issued by the second program, whether the access restriction request is legal or not (see step S 9 in FIG. 2A , for example); and an access restriction procedure which restricts access to the shared memory by the first program, if the access restriction request is judged as legal by the request judgment procedure (see step S 10 in FIG. 2A , for example).
  • a shared region generation procedure which makes, upon being requested by a first program (for example, program A), a part of a virtual address space assigned to the first program (for example, program A
  • the management program executed by the processor may be provided in computer readable recording media.
  • the computer readable recording media is a non-transitory medium.
  • Such recording media include a flexible disk, CDs (CD-ROM, CD-R, CD-RW, etc.), DVDs (DVD-ROM, DVD-RAM, DVD-R, DVD+R, DVD-RW, DVD+RW, etc.), a magnetic disk, an optical disk, a magneto-optical disk, etc.
  • the information processing device reads the program from such a recording medium, and transfers the program, onto one of an internal recording device and an external recording device for storage.
  • the management program may be recorded on a recording device (recording medium) such as a magnetic disk, an optical disk, or a magneto-optical disk, and then the management program may be supplied to the information processing device from the recording device via a communication line.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
US12/725,980 2009-03-31 2010-03-17 Information processing program, information processing device and information processing method Expired - Fee Related US8307166B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009088382A JP5338435B2 (ja) 2009-03-31 2009-03-31 情報処理プログラム、情報処理装置および情報処理方法
JP2009-088382 2009-03-31

Publications (2)

Publication Number Publication Date
US20100250866A1 US20100250866A1 (en) 2010-09-30
US8307166B2 true US8307166B2 (en) 2012-11-06

Family

ID=42562417

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/725,980 Expired - Fee Related US8307166B2 (en) 2009-03-31 2010-03-17 Information processing program, information processing device and information processing method

Country Status (4)

Country Link
US (1) US8307166B2 (ja)
EP (1) EP2237155B1 (ja)
JP (1) JP5338435B2 (ja)
KR (1) KR101139195B1 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101532397B1 (ko) * 2011-08-31 2015-06-29 후아웨이 테크놀러지 컴퍼니 리미티드 컴퓨터 시스템의 메모리 관리 방법, 메모리 관리 유닛 및 컴퓨터 시스템
JP5821723B2 (ja) * 2012-03-15 2015-11-24 富士通株式会社 情報処理装置及び制御プログラム
WO2013191606A1 (en) * 2012-06-21 2013-12-27 Saab Ab Dynamic memory access management
US9652270B2 (en) 2014-03-21 2017-05-16 Intel Corporation Apparatus and method for virtualized computing
US10628192B2 (en) * 2015-12-24 2020-04-21 Intel Corporation Scalable techniques for data transfer between virtual machines
WO2017155523A1 (en) 2016-03-09 2017-09-14 Hewlett Packard Enterprise Development Lp Server virtual address space
US10585412B2 (en) * 2017-02-13 2020-03-10 Rockwell Automation Technologies, Inc. Safety controller using hardware memory protection
CN109756704A (zh) * 2018-11-30 2019-05-14 安徽清新互联信息科技有限公司 一种嵌入式音视频监控系统的进程间通信方法及系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205362A (ja) 1988-02-12 1989-08-17 Sanyo Electric Co Ltd バス制御装置
US5123094A (en) 1990-01-26 1992-06-16 Apple Computer, Inc. Interprocessor communications includes second CPU designating memory locations assigned to first CPU and writing their addresses into registers
US20040068563A1 (en) 2002-10-08 2004-04-08 International Business Machines Corporation Method, system, and program for managing locks enabling access to a shared resource
US20080104337A1 (en) 2006-10-31 2008-05-01 Velureunni Ramesh RDMA copy-on-write

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100766666B1 (ko) * 2005-06-15 2007-10-11 후지쯔 가부시끼가이샤 멀티프로세서 시스템
US7536517B2 (en) * 2005-07-29 2009-05-19 Microsoft Corporation Direct-update software transactional memory
JP2007310834A (ja) * 2006-05-22 2007-11-29 Hitachi Ltd データ保護方法、情報処理装置及びオペレーティングシステム
US9274859B2 (en) * 2006-05-25 2016-03-01 Nvidia Corporation Multi processor and multi thread safe message queue with hardware assistance
JP4930078B2 (ja) 2007-01-31 2012-05-09 富士通株式会社 情報処理方法、情報処理装置、情報処理プログラムおよび該プログラムを記録した記録媒体
JP5308629B2 (ja) * 2007-03-26 2013-10-09 ルネサスエレクトロニクス株式会社 マルチプロセッサシステム及びマルチプロセッサシステムにおけるアクセス保護方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205362A (ja) 1988-02-12 1989-08-17 Sanyo Electric Co Ltd バス制御装置
US5123094A (en) 1990-01-26 1992-06-16 Apple Computer, Inc. Interprocessor communications includes second CPU designating memory locations assigned to first CPU and writing their addresses into registers
US20040068563A1 (en) 2002-10-08 2004-04-08 International Business Machines Corporation Method, system, and program for managing locks enabling access to a shared resource
US20080104337A1 (en) 2006-10-31 2008-05-01 Velureunni Ramesh RDMA copy-on-write

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
European Search Report for corresponding European Application 10156651.1-1243; date Apr. 27, 2012.

Also Published As

Publication number Publication date
JP2010238193A (ja) 2010-10-21
EP2237155B1 (en) 2017-07-26
JP5338435B2 (ja) 2013-11-13
EP2237155A2 (en) 2010-10-06
US20100250866A1 (en) 2010-09-30
EP2237155A3 (en) 2012-05-30
KR20100109403A (ko) 2010-10-08
KR101139195B1 (ko) 2012-04-26

Similar Documents

Publication Publication Date Title
US8307166B2 (en) Information processing program, information processing device and information processing method
US7979631B2 (en) Method of prefetching data in hard disk drive, recording medium including program to execute the method, and apparatus to perform the method
US7500093B2 (en) Startup program execution method, device, storage medium, and program
US8161128B2 (en) Sharing of data across disjoint clusters
CN106104502B (zh) 用于存储系统事务的系统、方法和介质
US20060136779A1 (en) Object-based storage device with low process load and control method thereof
JPH0242528A (ja) Ｉｃメモリカード
JP4521865B2 (ja) ストレージシステム、計算機システムまたは記憶領域の属性設定方法
JP2004334870A5 (ja)
CN103870210A (zh) 具有多个处理栈的存储控制器中使用区域锁定转移i/o请求的方法和结构
JP2004234053A (ja) コンピュータシステム、コンピュータ装置、記憶装置のデータ保護方法、およびプログラム
US8832388B2 (en) Managing shared memory used by compute nodes
KR101624005B1 (ko) 소프트웨어 컴포넌트 상태에 대한 접근 제어
US11003577B2 (en) Information processing apparatus, information processing method, and non-transitory computer-readable storage medium for storing program of access control with respect to semiconductor device memory
US7043602B2 (en) Diskarray system
US20010014932A1 (en) Multi-processor system
CN109144947A (zh) 一种虚拟化系统的集群文件系统的控制方法和装置
US8028142B2 (en) Controller of storage device, storage device, and control method of storage device
US10430287B2 (en) Computer
US9323476B2 (en) Hardware based cache scan with divert node handling
US11567666B2 (en) Handling the migration of pages of memory accessible by input-output devices
US11307904B2 (en) Configurable peripherals
JPS5848289A (ja) バツフアメモリ制御方式
KR100696322B1 (ko) 하드웨어 매체 접근제어 시스템 및 이를 이용한 하드웨어매체 접근제어 방법
US20070005918A1 (en) Methods and apparatus to provide interface access control

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOJIMA, HISASHI;NAKADA, MASAHIRO;SHIODA, TETSUYA;SIGNING DATES FROM 20100125 TO 20100126;REEL/FRAME:024100/0434

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20201106