US8058718B2 - Package substrate embedded with semiconductor component - Google Patents
Package substrate embedded with semiconductor component Download PDFInfo
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- US8058718B2 US8058718B2 US12/340,405 US34040508A US8058718B2 US 8058718 B2 US8058718 B2 US 8058718B2 US 34040508 A US34040508 A US 34040508A US 8058718 B2 US8058718 B2 US 8058718B2
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- passivation layer
- package substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Definitions
- the present invention relates to a semiconductor package substrate, and more particularly, to a package substrate embedded with a semiconductor component.
- one type of semiconductor component allows a semiconductor chip having an integrated circuit (IC) to be embedded in and electrically integrated with a package substrate.
- This semiconductor component may desirably reduce the overall size and improve the electrical functionality thereof, and thereby becomes widely adopted.
- FIGS. 1A to 1L a method for fabricating a conventional package substrate embedded with a semiconductor chip disclosed in U.S. Pat. No. 6,586,276 is shown.
- a wafer 10 having a plurality of electrode pads 101 is provided.
- a passivation layer is formed on the wafer 10 .
- a first opening 110 is formed in the passivation layer 11 to expose the electrode pads 101 .
- the passivation layer 11 and the exposed electrode pads 101 are covered with an adhesion layer 12 .
- a protection layer 13 is then formed on the adhesion layer 12 .
- FIG. 1A a wafer 10 having a plurality of electrode pads 101 is provided.
- a passivation layer is formed on the wafer 10 .
- a first opening 110 is formed in the passivation layer 11 to expose the electrode pads 101 .
- the passivation layer 11 and the exposed electrode pads 101 are covered with an adhesion layer 12 .
- a protection layer 13 is then formed on the adhesion layer 12
- the wafer 10 is cut to form a plurality of semiconductor chips 10 a .
- a substrate 14 having an opening 140 is provided, and then one semiconductor chip 10 a is placed into the opening 140 of the substrate 14 and secured there by a bonding material 15 formed in the gaps between the opening 140 of the substrate 14 and the semiconductor chip 10 a .
- a conductive layer 16 is formed on top of the protection layer 13 of the semiconductor chip 10 a , the bonding material 15 and the substrate 14 .
- a resist layer 17 is then formed on the conductive layer 16 having resist openings 170 at locations corresponding to those of the electrode pads 101 .
- FIG. 1G a substrate 14 having an opening 140 is provided, and then one semiconductor chip 10 a is placed into the opening 140 of the substrate 14 and secured there by a bonding material 15 formed in the gaps between the opening 140 of the substrate 14 and the semiconductor chip 10 a .
- a conductive layer 16 is formed on top of the protection layer 13 of the semiconductor chip 10 a , the bonding material 15 and the substrate
- expanded pads 18 are electroplated onto portions of the conductive layer 16 within the resist openings 170 .
- the resist layer 17 and the underlying conductive layer 16 , protection layer 13 and adhesion layer 12 are removed to expose the expanded pads and the passivation layer 11 , wherein the expanded pads 18 are larger than the electrode pads 101 to facilitate alignment during subsequent lamination of a dielectric layer(s) and a circuit layer(s).
- a circuit build-up structure 19 is then formed on the electrode pads 18 , the passivation layer 11 and the substrate 14 .
- the circuit build-up structure 19 includes at least a dielectric layer 191 , a circuit layer 192 laminated on the dielectric layer and conductive vias 193 in the dielectric layer electrically connected with the expanded pads 18 .
- the circuit build-up structure 19 further includes a plurality of conductive pads 194 on the surface thereof for electrically connecting the circuit layer 192 .
- An insulating protective layer 195 is also formed on the circuit build-up structure 19 having a plurality of openings 1950 that correspondingly expose the conductive pads 194 .
- an adhesion layer 12 has to be formed on the passivation layer 11 and the electrode pads 101 , and then a protection layer 13 is formed on the adhesion layer 12 .
- the adhesion layer 12 and the protection layer 13 facilitate subsequent processes of the semiconductor chip in the substrate, the exposed portions of the adhesion layer 12 and the protection layer 13 have to be removed before lamination of the dielectric layer 191 and the circuit layer 192 can be performed.
- the formation of the expanded pads 18 and electrically connection cannot be performed at the same time, which increases manufacturing cost and time.
- the electrically connecting structure including the expanded pads 18 and the conductive vias 192 is a complicated structure.
- an objective of the present invention is to provide a package substrate embedded with a semiconductor component.
- Another objective of the present invention is to provide a package substrate embedded with a semiconductor component directly connecting vias with electrode pads of the semiconductor chip.
- the present invention discloses a package substrate embedded with a semiconductor component, comprising: a substrate having at least one opening; a semiconductor chip secured in the opening of the substrate having an active face with a plurality of electrode pads and a passivation layer disposed thereon and an inactive face opposite to the active face, wherein the passivation layer includes a first passivation layer with openings for exposing the electrode pads and a second passivation layer disposed on the first passivation layer and the electrode pads exposed from the openings; a first dielectric layer provided on the substrate and the passivation layer a plurality of vias penetrating the first dielectric layer and the second passivation layer, and being within the openings to thereby expose the electrode pads; a first circuit layer provided on the first dielectric layer; and a plurality of first conductive vias formed in the vias for electrically connecting the electrode pads and the first circuit layer.
- the package substrate further comprises a bonding material disposed in gaps between the opening of the substrate and the semiconductor chip for securing the semiconductor in the opening.
- the substrate includes a first substrate body and a second substrate body having a respective opening for receiving the semiconductor chip secured therein by a bonding material disposed between the first and second substrate bodies and the opening.
- the semiconductor chip is placed in a carrier plate, and an encapsulating gel is formed on the carrier plate and the semiconductor chip to the level of the passivation layer, exposing the passivation layer while securing the semiconductor chip in the opening of the substrate formed by the carrier plate and the encapsulating gel.
- the first dielectric layer is a thermosetting material.
- the passivation layer includes a first passivation layer with openings for exposing electrode pads and a second passivation layer on the first passivation layer and the electrode pads exposed from the openings.
- the first passivation layer is silicon nitride (Si 3 N 4 ).
- the second passivation layer is polyimide.
- the package substrate further comprises a bonding material disposed in gaps between the opening of the substrate and the semiconductor chip for securing the semiconductor in the opening.
- the substrate includes a first substrate body and a second substrate body having a respective opening for receiving the semiconductor chip secured therein by a bonding material disposed between the first and second substrate bodies and the opening.
- the semiconductor chip is placed in a carrier plate, and an encapsulating gel is formed on the carrier plate and the semiconductor chip to the level of the passivation layer, exposing the passivation layer while securing the semiconductor chip in the opening of the substrate formed by the carrier plate and the encapsulating gel.
- the first dielectric layer is a thermosetting material and the laser has a wavelength in the infrared range.
- the passivation layer includes a first passivation layer with openings for exposing electrode pads and a second passivation layer on the first passivation layer and the electrode pads exposed from the openings.
- the first passivation layer is silicon nitride (Si 3 N 4 ).
- the second passivation layer is polyimide.
- the passivation layer includes a first passivation layer with openings for exposing electrode pads and a second passivation layer on the first passivation layer and the electrode pads exposed from the openings.
- the first passivation layer is silicon nitride (Si 3 N 4 ).
- the second passivation layer is polyimide.
- the vias are consisting of down-part openings penetrating the second passivation layer and up-part openings penetrating the first dielectric layer, and the size of the down-part opening is smaller than that of the up-part opening.
- the method for fabricating a package substrate embedded with a semiconductor chip of the present invention includes dicing a wafer having a plurality of electrode pads and covered by a passivation layer into a plurality of semiconductor chips and one semiconductor chip is placed in the substrate for subsequent processes.
- the passivation layer includes a first passivation layer with openings for exposing electrode pads and a second passivation layer on the first passivation layer and the electrode pads exposed from the openings.
- a first dielectric layer is formed on the semiconductor chip and the substrate, wherein a plurality of vias penetrate the first dielectric layer and the second passivation layer are formed by laser drilling, or the plurality of vias consist of up-part openings first formed in the dielectric layer by photolithography techniques and down-part openings further formed in the second passivation layer by laser drilling, thereby exposing the electrode pads, wherein the semiconductor chip is placed into the substrate before exposing the electrode pads, thus avoiding oxidation of the pads during processing.
- the laser has a wavelength in the infrared range, which avoids damage of the electrode pads since infrared laser has relatively lower energy
- the second passivation layer is selected to be a material that easily absorbs laser energy, such as polyimide.
- a lower-energy laser can be used in forming vias or openings in the passivation layer without damaging the electrode pads. Thereafter, first conductive vias directly connected to the electrode pads are formed.
- the present invention enables protection of the electrode pads of the semiconductor chip, direct electrical connection and reduction of process steps.
- FIG. 1A is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1B is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1C is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1D is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1E is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1F is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1G is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1H is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1I is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1J is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1K is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 1L is a cross-sectional view of a method for fabricating a traditional package substrate embedded with a semiconductor chip
- FIG. 2A is a cross-sectional view showing a method for fabricating a passivation layer on an active face of a wafer according to an embodiment of the present invention
- FIG. 2B is a cross-sectional view showing a method for fabricating a passivation layer on an active face of a wafer according to an embodiment of the present invention
- FIG. 2C is a cross-sectional view showing a method for fabricating a passivation layer on an active face of a wafer according to an embodiment of the present invention
- FIG. 3A is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3B is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3C is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3D is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3E is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3F is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3G is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3H is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention
- FIG. 3 B′ is the other implementation of FIG. 3B ;
- FIG. 3 B′′ is the other implementation of FIG. 3B ;
- FIG. 4A is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention
- FIG. 4B is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention.
- FIG. 4C is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention.
- FIG. 4D is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention.
- FIG. 4E is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention.
- FIG. 4F is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention.
- FIG. 4G is a cross-sectional view of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention.
- FIGS. 2A to 2C and 3 A to 3 H a method for fabricating a package substrate embedded with a semiconductor component according to a first embodiment of the present invention are shown.
- FIGS. 2A to 2C a method for fabricating a passivation layer on a wafer is shown.
- a wafer 20 having an active face 20 a and an inactive face 20 b opposite to each other is provided.
- a plurality of electrode pads 201 are formed on the active face 20 a.
- a first passivation layer 22 a such as silicon nitride (Si 3 N 4 ), is formed on the active face 20 a of the wafer 20 having a plurality of openings 220 a to expose partial surfaces of the electrode pads 202 .
- a second passivation layer 22 b such as polyimide, is formed on the electrode pads 201 and the first passivation layer 22 a .
- the first and second passivation layers 22 a and 22 b constitute a passivation layer 22 .
- FIGS. 3A to 3H cross-sectional views illustrating a semiconductor chip embedded in a package substrate are shown.
- a wafer 20 as shown in FIG. 2C is provided, which is diced into a plurality of semiconductor chips 20 ′.
- Each semiconductor chip 20 ′ has an active face 20 a and an inactive face 20 b opposite to each other.
- a plurality of electrode pads 201 and the passivation layer 22 are formed on the active face 20 a.
- a substrate 30 having an opening 300 is provided.
- the semiconductor chip 20 ′ is secured in the opening 300 by a bonding material 31 as depicted in FIG. 3B .
- the bonding material 31 is applied between a first substrate body 30 a and a second substrate body 30 b constituting the substrate body 30 , each body having a respective opening 300 for receiving the semiconductor chip 20 ′, and the bodies are squeezed such that the bonding material 31 are forced into the openings 300 to secure the chip 20 ′ in the openings 300 , as indicated in FIG. 3 B′.
- a carrier plate 30 c is provided for placing the semiconductor chip 20 ′ thereon.
- a packing gel 30 d is then formed on the carrier plate 30 c to the level of the passivation layer 22 of the semiconductor chip 20 ′, so as to encapsulate the chip 20 ′ in the gel 30 d while exposing the passivation layer 22 .
- the chip 20 ′ is secured in an opening 300 of a substrate 30 formed by the carrier plate 30 c and the encapsulating gel 30 d , as shown in FIG. 3 B′′. Descriptions will be made in the context of the structure in FIG. 3B hereinafter.
- a first dielectric layer 23 is formed on top of the substrate 30 and the passivation layer 22 .
- a plurality of vias 250 penetrating the first dielectric layer 23 and the second passivation layer 22 b are formed by, for example, laser drilling, thereby exposing partial surfaces of the electrode pads 201 .
- the vias 250 each have a down-part opening 220 b penetrating the second passivation layer 22 b and an up-part opening 230 penetrating the first dielectric layer 23 , and the size of the down-part opening 220 b is equal to that of the up-part opening 230 .
- the laser used has a wavelength in the infrared range.
- the electrode pads 201 can be prevented from damaging by the laser, since such infrared laser has relative lower energy.
- the first dielectric layer 23 is a thermosetting material, such as polyimide, that absorbs laser energy readily, allowing the use of lower-energy laser to form vias 250 without damaging the electrode pads 201 .
- a conductive layer 24 is formed on the electrode pads 201 , the first dielectric layer 23 and the vias 250 . It is used mainly as an electrical conduction path for subsequent electroplating of metal materials. It can be constituted of a metal layer, an alloy layer, or a plurality of metal layers or conducting polymer materials.
- a resist layer 25 is formed on the conductive layer 24 .
- the resist layer 25 is a dry or wet photoresist that is printed, spin coated or adhered to the surface of the conductive layer and patterned through lithography techniques (e.g. exposure and development etc.).
- First openings 251 and second openings 252 are formed in the resist layer 25 , wherein the second openings 252 correspond to the locations of the electrode pads 201 , and the size of the second openings 252 is larger than that of the vias 250 , exposing the conductive layer 24 on top of the electrode pads 201 .
- the first openings 251 are connected with the second openings 252 .
- an electroplating process is performed on the conductive layer 24 in the first and second openings 251 and 252 , using the conductive layer 24 as an electrical conduction path, thereby forming a first circuit layer 26 on the conductive layer 24 in the first openings 251 , and forming first conductive vias 261 on the conductive layer in the second openings 252 and vias 250 .
- the conductive vias 261 are electrically connected to the electrode pads 201 of the semiconductor chip 20 ′.
- the first circuit layer 26 is electrically connected to the first conductive vias 261 .
- the resist layer 25 and the underlying conductive layer 24 are removed to expose the first circuit layer 26 and the first dielectric layer 23 .
- a circuit build-up structure 27 is further formed on the first circuit layer 26 and the first dielectric layer 23 , including at least a second dielectric layer 271 , a second circuit layer 272 disposed on the second dielectric layer and conductive vias 273 in the second dielectric layer electrically connected with the first and second circuit layers.
- the circuit build-up structure further includes a plurality of conductive pads 274 on the surface thereof for electrically connecting to the second circuit layer 272 .
- An insulating protective layer 28 is also formed on the circuit build-up structure 27 having a plurality of openings 280 that correspondingly expose the conductive pads 274 .
- the present invention discloses a package substrate embedded with a semiconductor component, which includes: a substrate 30 having at least one opening 300 ; a semiconductor chip 20 ′ secured in the opening 300 of the substrate 30 by a bonding material 31 in gaps between the semiconductor chip 20 ′ and the opening 300 ; or the semiconductor chip 20 ′ received in the opening 300 of the substrate 30 constituted from a first substrate body 30 a and a second substrate body 30 b and secured by a bonding material 31 provided between the first and second substrate bodies 30 a and 30 b and the opening 300 ; or the semiconductor chip 20 ′ secured in the opening 300 formed by a carrier plate 30 c and an encapsulating gel 30 a , wherein the semiconductor chip 20 ′ is placed on the carrier plate 30 c and encapsulated by the encapsulating gel 30 a ; the semiconductor chip 20 ′ having an active face 20 a with a plurality of electrode pads 201 and a passivation layer 22 disposed on the active face 20 a of the chip 20 ′
- FIGS. 4A to 4G cross-sectional views of a method for fabricating a package substrate embedded with a semiconductor component according to a second embodiment of the present invention are shown.
- the second embodiment is similar to the first embodiment, but the main difference lies in the dielectric layer and its openings on the substrate and the semiconductor chip.
- FIG. 4A a structure shown in FIGS. 3B , 3 B′ or 3 B′′ is provided.
- the structure shown in FIG. 3B is used for illustration purpose.
- a first dielectric layer 23 ′ made of a photosensitive material is formed on top of the substrate 30 and the passivation layer 22 by printing, spin coating or adhesion. Up-part openings 230 ′ of the first dielectric layer 23 are formed at locations corresponding to those of the electrode pads 201 by lithography techniques such as exposure and development.
- down-part openings 220 b are then formed in the second passivation layer 22 b within the up-part openings 230 ′ to expose the electrode pads 201 , wherein the laser has a wavelength in the infrared range. Therefore, vias 250 ′ are formed, consisting of the down-part opening 220 b penetrating the second passivation layer 22 b and the up-part opening 230 ′ penetrating the first dielectric layer 23 , and the size of the down-part opening 220 b is smaller than that of the up-part opening 230 ′.
- a conductive layer 24 is formed on the electrode pads 201 , the first dielectric layer 23 ′, the up-part openings 230 ′ and the down-part openings 220 b .
- a resist layer 25 is formed on the conductive layer 24 having first openings 251 to expose partial conductive layer 24 on the substrate 30 and second openings 252 to expose the electrode pads 201 , the up-part openings 230 ′ of the first dielectric layer 23 and portions of the conductive layer 24 in the down-part openings 220 b of the second passivation layer 22 b , wherein the first and second openings 251 , 252 are connected to each other.
- a first build-up layer 26 is electroplated in the first openings 251 , and first conductive vias 261 are electroplated onto the conductive layer 24 in the second openings 252 to electrically connect with the electrode pads 201 .
- the first circuit layer 26 is electrically connected to the first conductive vias 261 .
- the resist layer 25 and the underlying conductive layer 24 are removed to expose the first circuit layer 26 and the first dielectric layer 23 ′.
- a circuit build-up structure 27 is further formed on the first circuit layer 26 and the first dielectric layer 23 , including at least a second dielectric layer 271 , a second circuit layer 272 disposed on the second dielectric layer 271 and conductive vias 273 in the second dielectric layer 271 electrically connected with the first and second circuit layers 26 , 272 .
- the circuit build-up structure 27 further includes a plurality of conductive pads 274 on the surface thereof for electrically connecting to the second circuit layer 272 .
- An insulating protective layer 28 is also formed on the circuit build-up structure 27 having a plurality of openings 280 that correspondingly expose the conductive pads 274 .
- the present invention discloses a package substrate embedded with a semiconductor component, which includes: a substrate 30 having at least one opening 300 ; a semiconductor chip 20 ′ secured in the opening 300 of the substrate 30 by a bonding material 31 in gaps between the semiconductor chip 20 ′ and the opening 300 ; or the semiconductor chip 20 ′ received in the opening 300 of the substrate 30 constituted from a first substrate body 30 a and a second substrate body 30 b and secured by a bonding material 31 provided between the first and second substrate bodies 30 a and 30 b and the opening 300 ; or the semiconductor chip 20 ′ secured in the opening 300 formed by a carrier plate 30 c and an encapsulating gel 30 a , wherein the semiconductor chip 20 ′ is placed on the carrier plate 30 c and encapsulated by the encapsulating gel 30 a ; the semiconductor chip 20 ′ having an active face 20 a with a plurality of electrode pads 201 and a passivation layer 22 disposed on the active face 20 a of the chip 20
- the vias 250 ′ consist of the down-part opening 220 b penetrating the second passivation layer 22 b and the up-part opening 230 ′ penetrating the first dielectric layer 23 , and the size of the down-part opening 220 b is smaller than that of the up-part opening 230 ′.
- the method for fabricating a package substrate embedded with a semiconductor chip of the present invention includes dicing a wafer having a plurality of electrode pads and covered by a passivation layer into a plurality of semiconductor chips and one semiconductor chip is placed in the substrate for subsequent processes.
- the passivation layer includes a first passivation layer with openings for exposing electrode pads and a second passivation layer on the first passivation layer and the electrode pads exposed from the openings.
- a first dielectric layer is formed on the semiconductor chip and the substrate, wherein a plurality of vias penetrate the first dielectric layer and the second passivation layer are formed by laser drilling, or the plurality of vias consist of up-part openings first formed in the dielectric layer by photolithography techniques and own-part openings further formed in the second passivation layer by laser drilling, thereby exposing the electrode pads, wherein the semiconductor chip is placed into the substrate before exposing the electrode pads, thus avoiding oxidation of the pads during processing.
- the laser has a wavelength in the infrared range, which avoids damage of the electrode pads since infrared laser has relatively lower energy
- the second passivation layer is selected to be a material that easily absorbs laser energy, such as polyimide.
- a lower-energy laser can be used in forming vias or openings in the passivation layer without damaging the electrode pads. Thereafter, first conductive vias directly connected to the electrode pads are formed.
- the present invention enables protection of the electrode pads of the semiconductor chip, direct electrical connection and reduction of process steps.
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Abstract
Description
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Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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TW096150713A TWI368304B (en) | 2007-12-28 | 2007-12-28 | Package substrate having embedded semiconductor element and fabrication method thereof |
TW96150713A | 2007-12-28 | ||
TW096150713 | 2007-12-28 |
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US20090166841A1 US20090166841A1 (en) | 2009-07-02 |
US8058718B2 true US8058718B2 (en) | 2011-11-15 |
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US12/340,405 Active 2029-09-07 US8058718B2 (en) | 2007-12-28 | 2008-12-19 | Package substrate embedded with semiconductor component |
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US20110042796A1 (en) * | 2009-08-20 | 2011-02-24 | Shu-Ming Chang | Chip package and fabrication method thereof |
US9299651B2 (en) | 2013-11-20 | 2016-03-29 | Bridge Semiconductor Corporation | Semiconductor assembly and method of manufacturing the same |
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US8354304B2 (en) * | 2008-12-05 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant |
US8552540B2 (en) * | 2011-05-10 | 2013-10-08 | Conexant Systems, Inc. | Wafer level package with thermal pad for higher power dissipation |
US20140299356A1 (en) * | 2013-04-04 | 2014-10-09 | Chong Zhang | Protective film with dye materials for laser absorption enhancement for via drilling |
US9953911B2 (en) | 2016-07-01 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package structure and method |
DE102020128994A1 (en) | 2020-05-27 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of manufacturing the same |
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US20040004284A1 (en) * | 2002-07-05 | 2004-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectronic device with a redistribution layer having a step shaped portion and method of making the same |
US20060087037A1 (en) * | 2004-10-22 | 2006-04-27 | Phoenix Precision Technology Corporation | Substrate structure with embedded chip of semiconductor package and method for fabricating the same |
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US20110042796A1 (en) * | 2009-08-20 | 2011-02-24 | Shu-Ming Chang | Chip package and fabrication method thereof |
US8633582B2 (en) * | 2009-08-20 | 2014-01-21 | Shu-Ming Chang | Chip package and fabrication method thereof |
US9299651B2 (en) | 2013-11-20 | 2016-03-29 | Bridge Semiconductor Corporation | Semiconductor assembly and method of manufacturing the same |
Also Published As
Publication number | Publication date |
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TWI368304B (en) | 2012-07-11 |
US20090166841A1 (en) | 2009-07-02 |
TW200929471A (en) | 2009-07-01 |
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