US8003526B2 - Low resistance metal silicide local interconnects and a method of making - Google Patents
Low resistance metal silicide local interconnects and a method of making Download PDFInfo
- Publication number
- US8003526B2 US8003526B2 US12/720,716 US72071610A US8003526B2 US 8003526 B2 US8003526 B2 US 8003526B2 US 72071610 A US72071610 A US 72071610A US 8003526 B2 US8003526 B2 US 8003526B2
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- US
- United States
- Prior art keywords
- layer
- metal
- metal silicide
- silicide
- angstroms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- FIG. 9 is a schematic diagram of an SRAM array having a plurality of memory cells arranged in rows and columns;
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (23)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/720,716 US8003526B2 (en) | 1997-08-21 | 2010-03-10 | Low resistance metal silicide local interconnects and a method of making |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/915,658 US7701059B1 (en) | 1997-08-21 | 1997-08-21 | Low resistance metal silicide local interconnects and a method of making |
US12/720,716 US8003526B2 (en) | 1997-08-21 | 2010-03-10 | Low resistance metal silicide local interconnects and a method of making |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/915,658 Continuation US7701059B1 (en) | 1997-08-21 | 1997-08-21 | Low resistance metal silicide local interconnects and a method of making |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100167528A1 US20100167528A1 (en) | 2010-07-01 |
US8003526B2 true US8003526B2 (en) | 2011-08-23 |
Family
ID=25436078
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/915,658 Expired - Fee Related US7701059B1 (en) | 1997-08-21 | 1997-08-21 | Low resistance metal silicide local interconnects and a method of making |
US09/522,086 Expired - Lifetime US6294464B1 (en) | 1997-08-21 | 2000-03-10 | Low resistance metal silicide local interconnects and a method of making |
US09/877,280 Expired - Lifetime US6605533B2 (en) | 1997-08-21 | 2001-06-08 | Process for forming low resistance metal silicide local interconnects |
US12/720,716 Expired - Fee Related US8003526B2 (en) | 1997-08-21 | 2010-03-10 | Low resistance metal silicide local interconnects and a method of making |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/915,658 Expired - Fee Related US7701059B1 (en) | 1997-08-21 | 1997-08-21 | Low resistance metal silicide local interconnects and a method of making |
US09/522,086 Expired - Lifetime US6294464B1 (en) | 1997-08-21 | 2000-03-10 | Low resistance metal silicide local interconnects and a method of making |
US09/877,280 Expired - Lifetime US6605533B2 (en) | 1997-08-21 | 2001-06-08 | Process for forming low resistance metal silicide local interconnects |
Country Status (1)
Country | Link |
---|---|
US (4) | US7701059B1 (en) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6284316B1 (en) * | 1998-02-25 | 2001-09-04 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
FR2828766B1 (en) * | 2001-08-16 | 2004-01-16 | St Microelectronics Sa | INTEGRATED CIRCUIT COMPRISING ACTIVE ELEMENTS AND AT LEAST ONE PASSIVE ELEMENT, IN PARTICULAR DRAM MEMORY CELLS AND MANUFACTURING METHOD |
DE10158798A1 (en) * | 2001-11-30 | 2003-06-18 | Infineon Technologies Ag | Capacitor and method of making a capacitor |
KR100564617B1 (en) * | 2004-03-05 | 2006-03-28 | 삼성전자주식회사 | Forming method for metal salicide layer and manufacturing method for semiconductor device using the forming method |
US7229920B2 (en) * | 2005-01-11 | 2007-06-12 | United Microelectronics Corp. | Method of fabricating metal silicide layer |
US20060270224A1 (en) * | 2005-02-08 | 2006-11-30 | Seung-Chul Song | Methods for forming metal-silicon layer using a silicon cap layer |
US20070120199A1 (en) * | 2005-11-30 | 2007-05-31 | Advanced Micro Devices, Inc. | Low resistivity compound refractory metal silicides with high temperature stability |
KR100645221B1 (en) * | 2005-12-28 | 2006-11-10 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
US7557424B2 (en) * | 2007-01-03 | 2009-07-07 | International Business Machines Corporation | Reversible electric fuse and antifuse structures for semiconductor devices |
US7791109B2 (en) * | 2007-03-29 | 2010-09-07 | International Business Machines Corporation | Metal silicide alloy local interconnect |
US8129764B2 (en) * | 2008-06-11 | 2012-03-06 | Aptina Imaging Corporation | Imager devices having differing gate stack sidewall spacers, method for forming such imager devices, and systems including such imager devices |
KR101069645B1 (en) * | 2008-12-26 | 2011-10-04 | 주식회사 하이닉스반도체 | Phase Changeable Memory Device Being Able To Decrease of Thermal Burden And Method of Manufacturing The Same |
JP2012193445A (en) * | 2011-02-28 | 2012-10-11 | Tokyo Electron Ltd | Method of forming titanium nitride film, apparatus for forming titanium nitride film, and program |
US8581348B2 (en) * | 2011-12-13 | 2013-11-12 | GlobalFoundries, Inc. | Semiconductor device with transistor local interconnects |
KR20130066945A (en) * | 2011-12-13 | 2013-06-21 | 에스케이하이닉스 주식회사 | Test pattern for semiconductor device, method for manufacturing the pattern, and method for testing the device using the test pattern |
US9536830B2 (en) | 2013-05-09 | 2017-01-03 | Globalfoundries Inc. | High performance refractory metal / copper interconnects to eliminate electromigration |
US9305879B2 (en) | 2013-05-09 | 2016-04-05 | Globalfoundries Inc. | E-fuse with hybrid metallization |
US9171801B2 (en) | 2013-05-09 | 2015-10-27 | Globalfoundries U.S. 2 Llc | E-fuse with hybrid metallization |
US10446546B2 (en) * | 2016-11-17 | 2019-10-15 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structures and methods of forming the same |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61188932A (en) | 1985-02-18 | 1986-08-22 | Toshiba Corp | Manufacture of semiconductor device |
US4910578A (en) | 1985-06-25 | 1990-03-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a metal electrode interconnection film with two layers of silicide |
US5094981A (en) | 1990-04-17 | 1992-03-10 | North American Philips Corporation, Signetics Div. | Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C. |
US5221853A (en) | 1989-01-06 | 1993-06-22 | International Business Machines Corporation | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region |
US5227333A (en) | 1992-02-27 | 1993-07-13 | International Business Machines Corporation | Local interconnection having a germanium layer |
US5468662A (en) | 1992-10-02 | 1995-11-21 | Texas Instruments Incorporated | Method of making thin film transistor and a silicide local interconnect |
US5635765A (en) | 1996-02-26 | 1997-06-03 | Cypress Semiconductor Corporation | Multi-layer gate structure |
US5646070A (en) | 1990-12-19 | 1997-07-08 | Philips Electronics North American Corporation | Method of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such region |
US5911144A (en) | 1997-04-23 | 1999-06-08 | Sun Microsystems, Inc. | Method and apparatus for optimizing the assignment of hash values to nodes residing in a garbage collected heap |
US5981372A (en) * | 1994-03-17 | 1999-11-09 | Fujitsu Limited | Method for manufacturing a semiconductor device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5911114A (en) | 1997-03-21 | 1999-06-08 | National Semiconductor Corporation | Method of simultaneous formation of salicide and local interconnects in an integrated circuit structure |
-
1997
- 1997-08-21 US US08/915,658 patent/US7701059B1/en not_active Expired - Fee Related
-
2000
- 2000-03-10 US US09/522,086 patent/US6294464B1/en not_active Expired - Lifetime
-
2001
- 2001-06-08 US US09/877,280 patent/US6605533B2/en not_active Expired - Lifetime
-
2010
- 2010-03-10 US US12/720,716 patent/US8003526B2/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61188932A (en) | 1985-02-18 | 1986-08-22 | Toshiba Corp | Manufacture of semiconductor device |
US4910578A (en) | 1985-06-25 | 1990-03-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a metal electrode interconnection film with two layers of silicide |
US5221853A (en) | 1989-01-06 | 1993-06-22 | International Business Machines Corporation | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region |
US5094981A (en) | 1990-04-17 | 1992-03-10 | North American Philips Corporation, Signetics Div. | Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C. |
US5646070A (en) | 1990-12-19 | 1997-07-08 | Philips Electronics North American Corporation | Method of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such region |
US5227333A (en) | 1992-02-27 | 1993-07-13 | International Business Machines Corporation | Local interconnection having a germanium layer |
US5468662A (en) | 1992-10-02 | 1995-11-21 | Texas Instruments Incorporated | Method of making thin film transistor and a silicide local interconnect |
US5981372A (en) * | 1994-03-17 | 1999-11-09 | Fujitsu Limited | Method for manufacturing a semiconductor device |
US5635765A (en) | 1996-02-26 | 1997-06-03 | Cypress Semiconductor Corporation | Multi-layer gate structure |
US5911144A (en) | 1997-04-23 | 1999-06-08 | Sun Microsystems, Inc. | Method and apparatus for optimizing the assignment of hash values to nodes residing in a garbage collected heap |
Non-Patent Citations (2)
Title |
---|
Dao, T.; Svejda, F.J.. A dual-port SRAM compiler for 0.8-mm 110K BiCMOS gate arrays. Custom Integrated Circuits Conference, 1991, Proceedings of the IEEE, 1991 pp. 22.4/1-22.4. |
Pierson, H.O.; Handbook of Chemical Vapor Deposition (CVD) Principles, Technology and Applications. Noyes Publications, 1992. pp. 1-3, 135-136, 145-148, 243-248. |
Also Published As
Publication number | Publication date |
---|---|
US7701059B1 (en) | 2010-04-20 |
US6605533B2 (en) | 2003-08-12 |
US6294464B1 (en) | 2001-09-25 |
US20100167528A1 (en) | 2010-07-01 |
US20010026960A1 (en) | 2001-10-04 |
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