US8001505B2 - Method and apparatus for merging EDA coverage logs of coverage data - Google Patents

Method and apparatus for merging EDA coverage logs of coverage data Download PDF

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Publication number
US8001505B2
US8001505B2 US12/210,887 US21088708A US8001505B2 US 8001505 B2 US8001505 B2 US 8001505B2 US 21088708 A US21088708 A US 21088708A US 8001505 B2 US8001505 B2 US 8001505B2
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coverage
merging
logs
responsive
verification
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US20100070940A1 (en
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Manoj Bist
Sandeep Mehrotra
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Synopsys Inc
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Synopsys Inc
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Priority to US12/210,887 priority Critical patent/US8001505B2/en
Assigned to SYNOPSYS, INC. reassignment SYNOPSYS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BIST, MANOJ, MEHROTRA, SANDEEP
Priority to PCT/US2009/052354 priority patent/WO2010030450A2/en
Priority to TW098125909A priority patent/TWI534643B/zh
Priority to CN200910169199XA priority patent/CN101676919B/zh
Publication of US20100070940A1 publication Critical patent/US20100070940A1/en
Priority to US13/189,314 priority patent/US8904319B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
US12/210,887 2008-09-15 2008-09-15 Method and apparatus for merging EDA coverage logs of coverage data Active 2029-09-10 US8001505B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US12/210,887 US8001505B2 (en) 2008-09-15 2008-09-15 Method and apparatus for merging EDA coverage logs of coverage data
PCT/US2009/052354 WO2010030450A2 (en) 2008-09-15 2009-07-31 Method and apparatus for merging eda coverage logs of coverage data
TW098125909A TWI534643B (zh) 2008-09-15 2009-07-31 用於合併覆蓋率資料的電子設計自動化（ｅｄａ）覆蓋率記錄的方法和裝置
CN200910169199XA CN101676919B (zh) 2008-09-15 2009-09-15 用于合并覆盖数据的eda覆盖日志的方法和装置
US13/189,314 US8904319B2 (en) 2008-09-15 2011-07-22 Method and apparatus for merging EDA coverage logs of coverage data

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Application Number Priority Date Filing Date Title
US12/210,887 US8001505B2 (en) 2008-09-15 2008-09-15 Method and apparatus for merging EDA coverage logs of coverage data

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US13/189,314 Continuation US8904319B2 (en) 2008-09-15 2011-07-22 Method and apparatus for merging EDA coverage logs of coverage data

Publications (2)

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US20100070940A1 US20100070940A1 (en) 2010-03-18
US8001505B2 true US8001505B2 (en) 2011-08-16

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US12/210,887 Active 2029-09-10 US8001505B2 (en) 2008-09-15 2008-09-15 Method and apparatus for merging EDA coverage logs of coverage data
US13/189,314 Active US8904319B2 (en) 2008-09-15 2011-07-22 Method and apparatus for merging EDA coverage logs of coverage data

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US (2) US8001505B2 (zh)
CN (1) CN101676919B (zh)
TW (1) TWI534643B (zh)
WO (1) WO2010030450A2 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8560985B1 (en) * 2007-06-07 2013-10-15 Cadence Design Systems, Inc. Configuration-based merging of coverage data results for functional verification of integrated circuits
US8601415B2 (en) * 2012-04-13 2013-12-03 International Business Machines Corporation Planning for hardware-accelerated functional verification
US8904319B2 (en) 2008-09-15 2014-12-02 Synopsys, Inc. Method and apparatus for merging EDA coverage logs of coverage data
US9069782B2 (en) 2012-10-01 2015-06-30 The Research Foundation For The State University Of New York System and method for security and privacy aware virtual machine checkpointing
US20150276871A1 (en) * 2014-03-31 2015-10-01 Mediatek Singapore Pte. Ltd. Integrated circuit and method for establishing scan test architecture in integrated circuit
US9767284B2 (en) 2012-09-14 2017-09-19 The Research Foundation For The State University Of New York Continuous run-time validation of program execution: a practical approach
US9767271B2 (en) 2010-07-15 2017-09-19 The Research Foundation For The State University Of New York System and method for validating program execution at run-time

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US7886242B1 (en) * 2006-12-12 2011-02-08 Cadence Design Systems, Inc. Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs
US8413088B1 (en) * 2007-06-07 2013-04-02 Cadence Design Systems, Inc. Verification plans to merging design verification metrics
US8676966B2 (en) * 2009-12-28 2014-03-18 International Business Machines Corporation Detecting and monitoring server side states during web application scanning
US8145949B2 (en) * 2010-06-16 2012-03-27 Plx Technology, Inc. Automated regression failure management system
US9098637B1 (en) * 2011-10-21 2015-08-04 Cadence Design Systems, Inc. Ranking process for simulation-based functional verification
CN103198007A (zh) * 2012-01-06 2013-07-10 腾讯科技（深圳）有限公司 多进程的日志输出方法及系统
US9021349B1 (en) * 2012-04-25 2015-04-28 Cadence Design Systems, Inc. System, method, and computer program product for identifying differences in a EDA design
US10387593B2 (en) * 2015-02-24 2019-08-20 Mentor Graphics Corporation Code coverage reconstruction
US9934343B2 (en) 2016-05-27 2018-04-03 International Business Machines Corporation System and method for generation of an integrated circuit design
US10546083B1 (en) * 2017-05-10 2020-01-28 Cadence Design Systems, Inc. System, method, and computer program product for improving coverage accuracy in formal verification
US10915430B2 (en) 2017-07-17 2021-02-09 Red Hat Israel, Ltd. Source code test consolidation
DE102017127276A1 (de) 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek
US10741539B2 (en) 2017-08-30 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Standard cells and variations thereof within a standard cell library
US10515169B1 (en) * 2018-01-06 2019-12-24 Cadence Design Systems, Inc. System, method, and computer program product for computing formal coverage data compatible with dynamic verification
US10796051B1 (en) 2019-04-30 2020-10-06 Cadence Design Systems, Inc. Adaptive model interface for a plurality of EDA programs
US11036906B1 (en) * 2020-01-24 2021-06-15 Cadence Design Systems, Inc. Method and apparatus to accelerate verification signoff by selective re-use of integrated coverage models
CN112329273B (zh) * 2020-12-17 2023-10-24 芯天下技术股份有限公司 一种提升芯片验证效率的方法、装置、存储介质和终端
CN116663492B (zh) * 2023-07-26 2023-10-13 北京云枢创新软件技术有限公司 交叉仓所覆盖的交叉项数量的获取方法、电子设备和介质

Citations (4)

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US6718521B1 (en) 2000-08-14 2004-04-06 International Business Machines Corporation Method and system for measuring and reporting test coverage of logic designs
US20040154002A1 (en) 2003-02-04 2004-08-05 Ball Michael S. System & method of linking separately compiled simulations
US20040225973A1 (en) * 2003-05-10 2004-11-11 Johnson Tyler James Post-silicon test coverage verification
US20080147373A1 (en) 2006-12-14 2008-06-19 Thomas Roessler Method for analyzing the design of an integrated circuit

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US6272668B1 (en) * 1994-12-14 2001-08-07 Hyundai Electronics America, Inc. Method for cell swapping to improve pre-layout to post-layout timing
KR100434240B1 (ko) 2001-02-27 2004-06-04 (주)다이나릿시스템 고수준 프로그래밍 언어를 이용한 회로내 에뮬레이션을위한 장치 및 방법
US6598211B2 (en) * 2001-03-30 2003-07-22 Intel Corporation Scaleable approach to extracting bridges from a hierarchically described VLSI layout
US7181376B2 (en) 2003-06-03 2007-02-20 International Business Machines Corporation Apparatus and method for coverage directed test
TW200719661A (en) 2005-11-04 2007-05-16 Univ Nat Taiwan Digital rights management framework(DRM) for SOC IP
US8001505B2 (en) 2008-09-15 2011-08-16 Synopsys, Inc. Method and apparatus for merging EDA coverage logs of coverage data

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US6718521B1 (en) 2000-08-14 2004-04-06 International Business Machines Corporation Method and system for measuring and reporting test coverage of logic designs
US20040154002A1 (en) 2003-02-04 2004-08-05 Ball Michael S. System & method of linking separately compiled simulations
US20040225973A1 (en) * 2003-05-10 2004-11-11 Johnson Tyler James Post-silicon test coverage verification
US20080147373A1 (en) 2006-12-14 2008-06-19 Thomas Roessler Method for analyzing the design of an integrated circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
International Search Report mailed Mar. 16, 2010 for a PCT Family Member Application No. PCT/US2009/052354, 11 pages.
Michael Koch "Distributed VHDL Simulation Within a Workstation Cluster," Proceedings of the 27th Annual Hawaii International Conference on System Sciences, vol. II: Software Technology, pp. 313-322, Jan. 4-7, 1994.

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8560985B1 (en) * 2007-06-07 2013-10-15 Cadence Design Systems, Inc. Configuration-based merging of coverage data results for functional verification of integrated circuits
US8904319B2 (en) 2008-09-15 2014-12-02 Synopsys, Inc. Method and apparatus for merging EDA coverage logs of coverage data
US9767271B2 (en) 2010-07-15 2017-09-19 The Research Foundation For The State University Of New York System and method for validating program execution at run-time
US8601415B2 (en) * 2012-04-13 2013-12-03 International Business Machines Corporation Planning for hardware-accelerated functional verification
US9767284B2 (en) 2012-09-14 2017-09-19 The Research Foundation For The State University Of New York Continuous run-time validation of program execution: a practical approach
US9069782B2 (en) 2012-10-01 2015-06-30 The Research Foundation For The State University Of New York System and method for security and privacy aware virtual machine checkpointing
US9552495B2 (en) 2012-10-01 2017-01-24 The Research Foundation For The State University Of New York System and method for security and privacy aware virtual machine checkpointing
US10324795B2 (en) 2012-10-01 2019-06-18 The Research Foundation for the State University o System and method for security and privacy aware virtual machine checkpointing
US20150276871A1 (en) * 2014-03-31 2015-10-01 Mediatek Singapore Pte. Ltd. Integrated circuit and method for establishing scan test architecture in integrated circuit
US9535120B2 (en) * 2014-03-31 2017-01-03 Mediatek Singapore Pte. Ltd. Integrated circuit and method for establishing scan test architecture in integrated circuit

Also Published As

Publication number Publication date
US8904319B2 (en) 2014-12-02
CN101676919A (zh) 2010-03-24
TW201015364A (en) 2010-04-16
US20100070940A1 (en) 2010-03-18
WO2010030450A2 (en) 2010-03-18
US20110283246A1 (en) 2011-11-17
CN101676919B (zh) 2013-03-13
WO2010030450A3 (en) 2010-05-06
TWI534643B (zh) 2016-05-21

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