TW200719661A - Digital rights management framework(DRM) for SOC IP - Google Patents

Digital rights management framework(DRM) for SOC IP

Info

Publication number
TW200719661A
TW200719661A TW094138742A TW94138742A TW200719661A TW 200719661 A TW200719661 A TW 200719661A TW 094138742 A TW094138742 A TW 094138742A TW 94138742 A TW94138742 A TW 94138742A TW 200719661 A TW200719661 A TW 200719661A
Authority
TW
Taiwan
Prior art keywords
identification
soc
vendor
core
digital rights
Prior art date
Application number
TW094138742A
Other languages
Chinese (zh)
Other versions
TWI295133B (en
Inventor
Yu-Cheng Fan
Hen-Wai Tsao
Original Assignee
Univ Nat Taiwan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Taiwan filed Critical Univ Nat Taiwan
Priority to TW094138742A priority Critical patent/TW200719661A/en
Publication of TW200719661A publication Critical patent/TW200719661A/en
Application granted granted Critical
Publication of TWI295133B publication Critical patent/TWI295133B/zh

Links

Abstract

In this pattern, we invent a "digital rights management framework for SOC IP." The framework considers the relation between designer, IP vendor, foundry, customer and electronic design automation (EDA) vendor and establishs a fair IP protection and management machine. First of all, we design an IP identification that includes general identification and secure identification. The IP identification is embedded into behavior design level in IP core. Then, we present the SOC IP public key cryptography technique to protect IP core. After encryption, customer is unaware the existence of IP identification. If illegal copy of IP is distributed, IP vendor can trace the source of illegal customer according to the IP fingerprinting in IP core.
TW094138742A 2005-11-04 2005-11-04 Digital rights management framework(DRM) for SOC IP TW200719661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094138742A TW200719661A (en) 2005-11-04 2005-11-04 Digital rights management framework(DRM) for SOC IP

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094138742A TW200719661A (en) 2005-11-04 2005-11-04 Digital rights management framework(DRM) for SOC IP

Publications (2)

Publication Number Publication Date
TW200719661A true TW200719661A (en) 2007-05-16
TWI295133B TWI295133B (en) 2008-03-21

Family

ID=45068350

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094138742A TW200719661A (en) 2005-11-04 2005-11-04 Digital rights management framework(DRM) for SOC IP

Country Status (1)

Country Link
TW (1) TW200719661A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102542191A (en) * 2010-12-31 2012-07-04 深圳市证通电子股份有限公司 RTL (register transfer level) IP (intellectual property) core protecting method
TWI759943B (en) * 2020-05-27 2022-04-01 台灣積體電路製造股份有限公司 Method of certifying safety levels of semiconductor memories in integrated circuits and computer-readable medium storing executable code

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8001505B2 (en) 2008-09-15 2011-08-16 Synopsys, Inc. Method and apparatus for merging EDA coverage logs of coverage data
CN109145527B (en) * 2018-06-22 2020-10-09 芯启源(上海)半导体科技有限公司 IP soft core property protection and infringement identification method based on USB3.1 protocol TS2 training sequence
US11313810B2 (en) 2019-11-14 2022-04-26 International Business Machines Corporation Secure semiconductor wafer inspection utilizing film thickness

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102542191A (en) * 2010-12-31 2012-07-04 深圳市证通电子股份有限公司 RTL (register transfer level) IP (intellectual property) core protecting method
TWI759943B (en) * 2020-05-27 2022-04-01 台灣積體電路製造股份有限公司 Method of certifying safety levels of semiconductor memories in integrated circuits and computer-readable medium storing executable code
US11651134B2 (en) 2020-05-27 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method of certifying safety levels of semiconductor memories in integrated circuits

Also Published As

Publication number Publication date
TWI295133B (en) 2008-03-21

Similar Documents

Publication Publication Date Title
Colombier et al. Survey of hardware protection of design data for integrated circuits and intellectual properties
Abdel-Hamid et al. A survey on IP watermarking techniques
US8732468B2 (en) Protecting hardware circuit design by secret sharing
Lach et al. FPGA fingerprinting techniques for protecting intellectual property
Jain et al. Zero overhead watermarking technique for FPGA designs
CN101996293B (en) Software authentication method based on softdog
CN105303069B (en) A kind of system for numeral copyright management and method
WO2005043283A3 (en) Secure exchange of information in electronic design automation
CN103809956B (en) Automatic software auditing system and automatic software auditing method
Chang et al. A blind dynamic fingerprinting technique for sequential circuit intellectual property protection
TW200719661A (en) Digital rights management framework(DRM) for SOC IP
CN101246527B (en) Method and system for providing and using copyright description
CN107169325A (en) Copyright information protection, really power method, device, system and content editing device
Saha et al. SoC: a real platform for IP reuse, IP infringement, and IP protection
CN101694685A (en) Safety product license management method based on XML encryption and digital certificate
WO2007123646A3 (en) Secure exchange of information in electronic design automation with license-related key generation
Roy et al. Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis
US20070174638A1 (en) Method used for digital right management of system-on-chip IP by making use of system platform
CN101882297A (en) Digital watermarking method
Yuan et al. Soft IP protection: Watermarking HDL codes
CN201552816U (en) Electronic and physical combined seal
JP2011022690A (en) Simulation model generation device
WO2009061171A3 (en) Secure software licensing control mechanism
Kumar et al. A flexible pay-per-device licensing scheme for FPGA IP cores
Potkonjak et al. 20 years of research on intellectual property protection