US7982204B2 - Using unstable nitrides to form semiconductor structures - Google Patents

Using unstable nitrides to form semiconductor structures Download PDF

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US7982204B2
US7982204B2 US12/788,603 US78860310A US7982204B2 US 7982204 B2 US7982204 B2 US 7982204B2 US 78860310 A US78860310 A US 78860310A US 7982204 B2 US7982204 B2 US 7982204B2
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nitride
metal
substrate
layer
copper
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Juan E. Dominguez
Adrien R. Lavoie
John J. Plombon
Joseph H. Han
Harsono S. Simka
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Tahoe Research Ltd
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less

Definitions

  • This invention relates generally to the fabrication of integrated circuits.
  • incompatible it is intended to mean that the upper material cannot be deposited onto the lower layer with sufficient adherence to the lower layer to avoid delamination.
  • FIG. 1 is an enlarged, cross-sectional view at an early stage of manufacture according to one embodiment
  • FIG. 2 is an enlarged, cross-sectional view at a subsequent stage of manufacture according to one embodiment
  • FIG. 3 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in FIG. 1 according to one embodiment
  • FIG. 4 is an enlarged, cross-sectional view at a subsequent stage to FIG. 3 in accordance with one embodiment of the present invention
  • FIG. 5 is an enlarged, cross-sectional view of another embodiment of the present invention.
  • FIG. 6 is an enlarged, cross-sectional view of still another embodiment of the present invention.
  • a layer of a first material 12 may receive on its upper surface a deposit of a second material 14 .
  • the material 14 and the material 12 may be sufficiently compatible that adequate adherence can be obtained between the materials 12 and 14 in some embodiments.
  • the material 14 now adhered to the material 12 , may then be converted to another material incompatible with the material 12 if directly deposited on the material 12 .
  • the incompatible material may be successfully adhered to the first material 12 .
  • the material 12 may be a nitrided barrier layer such as titanium nitride or tungsten nitride.
  • the material 14 in one embodiment, may be an unstable metal nitride, such as Cu 3 N or Cu 4 N, as two examples.
  • the material 14 may be Ni 3 N.
  • the material 14 is deposited by a atomic layer deposition (ALD) and/or chemical vapor deposition (CVD).
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • Precursors may be used to deposit the unstable metal nitrides by ALD or CVD, including, but not limited to, copper amidinate variants, betadiketiminates, azaallyis, betadiketonates, pyridines, cyclic arenes, and alkenes.
  • Deposition of the material 14 may take place at a substrate temperature between 80° C. and 150° C., under chamber pressures between 100 mTorr to 10 Torr, in some embodiments.
  • Co-reactants may be pulsed or flown to form unstable metal nitrides such as Cu 3 N or Cu/Cu 3 N mixtures.
  • the co-reactants may include, but are not limited to, NH 3 , primary amines, secondary amines, tertiary amines, hydrazine, BR3-amine adducts (where R is alkyl, proton or both and the amine is primary, secondary, tertiary), azides, as well as pure nitrogen, nitrogen plasma, or N 2 /H 2 plasma, as well as any plasma and combinations from aforementioned chemicals.
  • the material 14 may be decomposed to form a pure or substantially nitride free metal layer 16 .
  • the layer 16 is decomposed to pure copper, in one embodiment, or pure nickel, in another embodiment, where Ni 3 N is used.
  • Methods for decomposing the material 14 include thermal annealing in pure hydrogen gas, diluted hydrogen gas in an inert gas, annealing in NH 3 or nitrogen gas, at temperatures ranging from 200° C. to 500° C., for times ranging between five minutes to 120 minutes.
  • the Cu 3 N material 14 may transform into near bulk copper conductivity within about one hour.
  • an electron beam may be used to decompose the Cu 3 N into copper.
  • Other thermal decomposition techniques may be used, including rapid thermal annealing in vacuum and joule heating using a resistive underlayer.
  • Non-thermal decomposition may also be used, including ion implantation, ion bombardment, light, and plasma (remote and near) annealing.
  • the material 14 may be converted entirely into a pure metal layer 16 .
  • the conversion may be incomplete, leaving a thin layer of material 14 between the pure metal layer 16 and the material 12 .
  • the material 14 remains in contact with the first material 12 over a substrate 10 , such as a silicon substrate.
  • the material 14 may serve as an adhesion layer to the nitrided barrier material 12 .
  • the conversion of the material 14 allows the deposition of two consecutive ALD or CVD layers for barrier and seed, all in one deposition step in some embodiments.
  • a nitrided barrier material 12 may also act as a getterer of nitrogen and may not allow the formation of CuN layers in the pure copper film.
  • a preferred embodiment uses ALD TaN as the nitrided barrier with Cu-nitride deposition.
  • the Cu 3 N material may be deposited directly on silicon or carbon doped silicon to form SiCN, which may act as a barrier to copper diffusion.
  • the Cu 3 N layer is deposited on porous low dielectric constant material and can serve as a dual sacrificial pore sealing/adhesion layer.
  • a Cu 3 N layer 14 a may be used as a sacrificial/morphing non-reflective coating on a copper metal layer 16 to permit further patterning using optical techniques.
  • a Cu 3 N layer 14 a may first be deposited and post-treated to pure copper metal layer 16 , as indicated in FIG. 3 .
  • a second Cu 3 N layer 14 a may be deposited over the reflective metal layer 16 .
  • the Cu 3 N layer 14 a acts as a non-reflective layer for patterning an overlying resist and etching.
  • the Cu 3 N . layer 14 a can act as an adhesion layer or be reverted back to a conductive or pure metal layer.
  • copper and Cu 3 N may be used as selective etching layers, or Cu 3 N can be selectively etched over copper to produce conductive copper lines.
  • an atomic layer deposition metal nitride material 14 may be formed over a nitrided barrier material 12 on top of a substrate 10 , such as a silicon substrate.
  • the material 14 may be selectively converted into pure or substantially nitride free copper metal strip 16 a by the use of an electron beam E or other methods already mentioned.
  • a nano-patterned metal strip 16 a shown in FIG. 6 , may be obtained by placing the nanometer sized (i.e., of a width on the order of a billionth of a meter) electron beam E at exact locations using a reticle or precise beam location.
  • a nanowire may be formed by moving the electron beam over the material 14 .
  • the surrounding unconverted dielectric material 14 can be used as an encapsulating material to avoid line shorting.
  • the present invention it is possible to deposit films with precise thickness and composition control.
  • the deposition of conformal, uniform, and nanometer-sized films may be achieved in some embodiments with a nitrided cap and sidewalls to prevent full line oxidation.
  • Conductive lines or layers may be precisely located in some cases and improved adhesion to silicon or nitrided substrates may be achieved.
  • low reflectivity enabling patterning may be accomplished in some cases.
  • deposition and patterning of ultra-thin lines may be achieved with width and height less than ten nanometers or to a size enabled by electron beams or scanning tunneling microscopy (STM) resolution.
  • STM scanning tunneling microscopy
  • references throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.

Abstract

Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser. No. 11/359,060, filed on Feb. 22, 2006 now U.S. Pat. No. 7,749,906.
BACKGROUND
This invention relates generally to the fabrication of integrated circuits.
In the fabrication of integrated circuits, it is desirable to use a variety of different materials over a variety of different substrates. Sometimes materials that an engineer would like to use over a given substrate are incompatible with that substrate. By “incompatible” it is intended to mean that the upper material cannot be deposited onto the lower layer with sufficient adherence to the lower layer to avoid delamination.
Thus, commonly, in order to adhere these incompatible layers to one another, special deposition techniques are required or adhesion layers must be provided between the incompatible layers.
It is also desirable in a variety of applications to form nanowires or very small electrical conductors in semiconductor integrated circuits. Commonly, the deposition of such small conductors is extremely difficult. Moreover, to form a conductor, such as a copper conductor buried in other material, involves a large and cost ineffective number of process steps.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an enlarged, cross-sectional view at an early stage of manufacture according to one embodiment;
FIG. 2 is an enlarged, cross-sectional view at a subsequent stage of manufacture according to one embodiment;
FIG. 3 is an enlarged, cross-sectional view at a stage subsequent to the stage shown in FIG. 1 according to one embodiment;
FIG. 4 is an enlarged, cross-sectional view at a subsequent stage to FIG. 3 in accordance with one embodiment of the present invention;
FIG. 5 is an enlarged, cross-sectional view of another embodiment of the present invention; and
FIG. 6 is an enlarged, cross-sectional view of still another embodiment of the present invention.
 DETAILED DESCRIPTION
Referring to FIG. 1, a layer of a first material 12, over a substrate or wafer 10, may receive on its upper surface a deposit of a second material 14. The material 14 and the material 12 may be sufficiently compatible that adequate adherence can be obtained between the materials 12 and 14 in some embodiments. However, the material 14, now adhered to the material 12, may then be converted to another material incompatible with the material 12 if directly deposited on the material 12. By depositing the material 14 in a first form and then converting it into a second form, the incompatible material may be successfully adhered to the first material 12.
As an example, the material 12 may be a nitrided barrier layer such as titanium nitride or tungsten nitride. The material 14, in one embodiment, may be an unstable metal nitride, such as Cu3N or Cu4N, as two examples. As another example, the material 14 may be Ni3N.
In one embodiment, the material 14 is deposited by a atomic layer deposition (ALD) and/or chemical vapor deposition (CVD). Precursors may be used to deposit the unstable metal nitrides by ALD or CVD, including, but not limited to, copper amidinate variants, betadiketiminates, azaallyis, betadiketonates, pyridines, cyclic arenes, and alkenes. Deposition of the material 14 may take place at a substrate temperature between 80° C. and 150° C., under chamber pressures between 100 mTorr to 10 Torr, in some embodiments. Co-reactants may be pulsed or flown to form unstable metal nitrides such as Cu3N or Cu/Cu3N mixtures. The co-reactants may include, but are not limited to, NH3, primary amines, secondary amines, tertiary amines, hydrazine, BR3-amine adducts (where R is alkyl, proton or both and the amine is primary, secondary, tertiary), azides, as well as pure nitrogen, nitrogen plasma, or N2/H2 plasma, as well as any plasma and combinations from aforementioned chemicals.
Then, referring to FIG. 2, the material 14 may be decomposed to form a pure or substantially nitride free metal layer 16. After deposition of on patterned wafers, the layer 16 is decomposed to pure copper, in one embodiment, or pure nickel, in another embodiment, where Ni3N is used. Methods for decomposing the material 14 include thermal annealing in pure hydrogen gas, diluted hydrogen gas in an inert gas, annealing in NH3 or nitrogen gas, at temperatures ranging from 200° C. to 500° C., for times ranging between five minutes to 120 minutes. The Cu3N material 14 may transform into near bulk copper conductivity within about one hour.
In another embodiment, an electron beam, with appropriate diameter and energy, may be used to decompose the Cu3N into copper. Other thermal decomposition techniques may be used, including rapid thermal annealing in vacuum and joule heating using a resistive underlayer. Non-thermal decomposition may also be used, including ion implantation, ion bombardment, light, and plasma (remote and near) annealing.
In some embodiments, as shown in FIG. 3, the material 14 may be converted entirely into a pure metal layer 16. In other embodiments, as shown in FIG. 2, the conversion may be incomplete, leaving a thin layer of material 14 between the pure metal layer 16 and the material 12. Thus, the material 14 remains in contact with the first material 12 over a substrate 10, such as a silicon substrate.
The material 14 may serve as an adhesion layer to the nitrided barrier material 12. The conversion of the material 14 allows the deposition of two consecutive ALD or CVD layers for barrier and seed, all in one deposition step in some embodiments.
The presence of a nitrided barrier material 12 may also act as a getterer of nitrogen and may not allow the formation of CuN layers in the pure copper film. A preferred embodiment uses ALD TaN as the nitrided barrier with Cu-nitride deposition. In addition, the Cu3N material may be deposited directly on silicon or carbon doped silicon to form SiCN, which may act as a barrier to copper diffusion. In still another embodiment, the Cu3N layer is deposited on porous low dielectric constant material and can serve as a dual sacrificial pore sealing/adhesion layer.
Referring to FIG. 4, in some embodiments, a Cu3N layer 14 a may be used as a sacrificial/morphing non-reflective coating on a copper metal layer 16 to permit further patterning using optical techniques. In such case, a Cu3N layer 14 a may first be deposited and post-treated to pure copper metal layer 16, as indicated in FIG. 3. Then a second Cu3N layer 14 a may be deposited over the reflective metal layer 16. The Cu3N layer 14 a acts as a non-reflective layer for patterning an overlying resist and etching. After the patterning is complete, the Cu3N. layer 14 a can act as an adhesion layer or be reverted back to a conductive or pure metal layer.
In a further embodiment, copper and Cu3N may be used as selective etching layers, or Cu3N can be selectively etched over copper to produce conductive copper lines.
Moving to FIG. 5, in accordance with one embodiment of the present invention, an atomic layer deposition metal nitride material 14 may be formed over a nitrided barrier material 12 on top of a substrate 10, such as a silicon substrate. The material 14 may be selectively converted into pure or substantially nitride free copper metal strip 16 a by the use of an electron beam E or other methods already mentioned. A nano-patterned metal strip 16 a, shown in FIG. 6, may be obtained by placing the nanometer sized (i.e., of a width on the order of a billionth of a meter) electron beam E at exact locations using a reticle or precise beam location. For example, a nanowire may be formed by moving the electron beam over the material 14. The surrounding unconverted dielectric material 14 can be used as an encapsulating material to avoid line shorting.
In some embodiments of the present invention, it is possible to deposit films with precise thickness and composition control. The deposition of conformal, uniform, and nanometer-sized films may be achieved in some embodiments with a nitrided cap and sidewalls to prevent full line oxidation. Conductive lines or layers may be precisely located in some cases and improved adhesion to silicon or nitrided substrates may be achieved. Also, low reflectivity enabling patterning may be accomplished in some cases. In some embodiments, deposition and patterning of ultra-thin lines may be achieved with width and height less than ten nanometers or to a size enabled by electron beams or scanning tunneling microscopy (STM) resolution.
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (6)

1. A semiconductor structure comprising:
a substrate;
a substantially nitride free metal nanowire over said substrate; and
a metal nitride over said nanowire, said metal nitride including at least three metal atoms per nitrogen atom.
2. The structure of claim 1 wherein said nanowire is copper.
3. The structure of claim 1 wherein said substrate is a nitride.
4. The structure of claim 3 wherein said substrate includes tungsten or titanium nitride.
5. A semiconductor structure comprising:
a substrate;
a metal nanowire nitride layer over said substrate; and
a region of substantially nitride free metal formed in said layer.
6. The structure of claim 5 wherein said metal nitride includes the same metal as said substantially nitride free metal.
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