US7920412B2 - Magnetic random access memory and method of manufacturing the same - Google Patents

Magnetic random access memory and method of manufacturing the same Download PDF

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US7920412B2
US7920412B2 US12/605,072 US60507209A US7920412B2 US 7920412 B2 US7920412 B2 US 7920412B2 US 60507209 A US60507209 A US 60507209A US 7920412 B2 US7920412 B2 US 7920412B2
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insulating film
wiring
forming
formed
contact
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US20100047930A1 (en
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Keiji Hosotani
Yoshiaki Asao
Akihiro Nitayama
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Toshiba Corp
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Toshiba Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/22Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
    • H01L27/222Magnetic non-volatile memory structures, e.g. MRAM
    • H01L27/226Magnetic non-volatile memory structures, e.g. MRAM comprising multi-terminal components, e.g. transistors
    • H01L27/228Magnetic non-volatile memory structures, e.g. MRAM comprising multi-terminal components, e.g. transistors of the field-effect transistor type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1653Address circuits or decoders
    • G11C11/1657Word-line or row circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1659Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1673Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1675Writing or programming circuits or methods

Abstract

A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 11/839,265 filed Aug. 15, 2007, and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application No. 2006-269334 filed Sep. 29, 2006, the entire contents of each of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a magnetic random access memory (MRAM) using the magnetoresistive effect, and a method of manufacturing the same.

2. Description of the Related Art

Recently, many types of memory for storing information by the application of new principles have been proposed. One such type, as proposed by Roy Scheuerlein et al., is the magnetic random access memory using the tunneling magnetoresistive (TMR) effect. (See non-patent reference 1.)

A magnetic random access memory stores a binary value in a magnetic tunnel junction (MTJ) element. The MTJ element has a structure in which two magnetic layers (ferromagnetic layers) sandwich an insulating layer (tunnel barrier). Whether value stored in the MTJ element is binary 1 or 0 is determined in accordance with whether the spin directions in the two magnetic layers are parallel or antiparallel.

Data written in the MTJ element is read as follows. Switching elements are connected in series with MTJ elements, and only a switching element connected to a selected read word line is turned on to form a current path. Since a current flows to only the selected MTJ element, data can be read from the MTJ element.

When a MOSFET is used as the switching element, the cell size is 12F2 if the short side (the width in the magnetic hard axis direction) of the MTJ element is F (Feature size) and the long side (the width in the magnetic easy axis direction) is 2F. Accordingly, the cell size of the magnetic random access memory is larger than those of a DRAM and flash memory. The cell size becomes 10F2, therefore, if an easy axis write bit line is formed below the MTJ element and the lower electrode of the MTJ element and the fringe of the contact of the lower electrode are self-aligned. However, the decrease in cell size is still unsatisfactory.

[Non-patent reference 1] Roy Scheuerlein et al., ISSCC2000 Technical Digest p. 128, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”

[Patent reference 1] Jpn. Pat. Appln. KOKAI Publication No. 2005-175357

BRIEF SUMMARY OF THE INVENTION

A magnetic random access memory according to the first aspect of the present invention comprises a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

A magnetic random access memory according to the second aspect of the present invention comprises a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, connected to the second wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a first side insulating film formed on a side surface of the first wiring, a first top insulating film formed on an upper surface of the first wiring, and a first contact formed below the magnetoresistive effect element, having a side surface in contact with a side surface of the first side insulating film, and electrically connected to the magnetoresistive effect element.

A magnetic random access memory manufacturing method according to the third aspect of the present invention comprises forming a switching element on a semiconductor substrate, forming a first wiring above the switching element, forming, on the first wiring, a magnetoresistive effect element having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, forming a metal layer on the magnetoresistive effect element, forming a first side insulating film on side surfaces of the first wiring, the magnetoresistive effect element, and the metal layer, forming a first interlayer insulating film covering the metal layer, exposing the metal layer by planarizing the first interlayer insulating film, forming a contact hole which exposes a portion of the first side insulating film, forming, in the contact hole, a first contact connecting to the switching element, forming a second wiring on the first contact and the metal layer to electrically connect the metal layer and the switching element by the second wiring, forming a second interlayer insulating film on the second wiring, and forming a third wiring on the second interlayer insulating film.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a sectional view showing a basic example of a magnetic random access memory according to the first embodiment of the present invention;

FIG. 2A is a plan view showing the periphery of an MTJ element according to the first embodiment of the present invention;

FIG. 2B is a plan view showing the periphery of a gate electrode according to the first embodiment of the present invention;

FIGS. 3 to 9 are sectional views showing the manufacturing steps of the basic example of the magnetic random access memory according to the first embodiment of the present invention;

FIG. 10 is a sectional view showing a modification example of the magnetic random access memory according to the first embodiment of the present invention;

FIG. 11 is a sectional view showing the manufacturing step, following FIG. 5, of the modification example of the magnetic random access memory according to the first embodiment of the present invention;

FIG. 12 is a sectional view showing the manufacturing step, following FIG. 11, of the modification example of the magnetic random access memory according to the first embodiment of the present invention;

FIG. 13 is a sectional view showing the MTJ element according to the first embodiment of the present invention;

FIG. 14A is a view showing the parallel arrangement of a parallel magnetization type MTJ element according to the first embodiment of the present invention;

FIG. 14B is a view showing the antiparallel arrangement of the parallel magnetization type MTJ element according to the first embodiment of the present invention;

FIG. 15A is a view showing the parallel arrangement of a perpendicular magnetization type MTJ element according to the first embodiment of the present invention;

FIG. 15B is a view showing the antiparallel arrangement of the perpendicular magnetization type MTJ element according to the first embodiment of the present invention;

FIG. 16 is a sectional view showing a basic example of a magnetic random access memory according to the second embodiment of the present invention;

FIG. 17A is a plan view showing the periphery of an MTJ element according to the second embodiment of the present invention;

FIG. 17B is a plan view showing the periphery of a gate electrode according to the second embodiment of the present invention;

FIGS. 18 to 22 are sectional views showing the manufacturing steps of the basic example of the magnetic random access memory according to the second embodiment of the present invention;

FIG. 23 is a sectional view showing modification example 1 of the magnetic random access memory according to the second embodiment of the present invention;

FIGS. 24 to 28 are sectional views showing the manufacturing steps of modification example 1 of the magnetic random access memory according to the second embodiment of the present invention;

FIG. 29 is a sectional view showing modification example 2 of the magnetic random access memory according to the second embodiment of the present invention;

FIG. 30 is a sectional view showing a magnetic random access memory according to the third embodiment of the present invention;

FIGS. 31 to 33 are sectional views showing magnetic random access memories according to the third embodiment of the present invention;

FIGS. 34 and 35 are sectional views showing magnetic random access memories according to the fourth embodiment of the present invention;

FIGS. 36A to 36C are schematic sectional views showing magnetic random access memory manufacturing steps using a via hole process according to the fifth embodiment of the present invention; and

FIGS. 37A to 37D are schematic sectional views showing magnetic random access memory manufacturing steps using a dual damascene process according to the fifth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be explained below with reference to the accompanying drawing. The same reference numerals denote the same parts throughout the drawing.

[1] First Embodiment [1-1] Basic Example of a Magnetic Random Access Memory

FIG. 1 is a sectional view showing a basic example of a magnetic random access memory according to the first embodiment of the present invention. FIG. 2A is a plan view showing the periphery of an MTJ element according to the first embodiment of the present invention. FIG. 2B is a plan view showing the periphery of a gate electrode according to the first embodiment of the present invention. The basic example of the magnetic random access memory according to the first embodiment will be explained below.

As shown in FIG. 1, a gate electrode 13 is formed on a semiconductor substrate 11 via a gate insulating film 12. Source/drain diffusion layers 15 are formed in the semiconductor substrate 11 on the two sides of the gate electrode 13, thereby forming a metal oxide semiconductor (MOS) transistor Tr as a switching element. Side insulating films 16 are formed on the side surfaces of the gate electrode 13, and a top insulating film 14 is formed on the upper surface of the gate electrode 13. The gate electrode 13 functions as a read word line RWL.

A contact 18 is connected to each source/drain diffusion layer 15. The contact 18 is formed in self-alignment with the gate electrode 13 and side insulating film 16. Therefore, the contact 18 is in direct contact with the side surface of the side insulating film 16. A portion of the contact 18 covers the upper portion of the side insulating film 16.

A write word line WWL is formed above the gate electrode 13. An MTJ element MTJ is formed on the write word line WWL. A conductive hard mask HM (metal layer) is formed on the MTJ element MTJ so as to be integrated with it to form stacked layers. The planar shape of the hard mask HM is, for example, the same as that of the MTJ element MTJ. The side surfaces in the magnetic easy axis direction of the MTJ element MTJ are aligned with the side surfaces of the hard mask HM and bit lint BL. Side insulating films 24 are formed on the side surfaces of the hard mask HM, the side surfaces in the magnetic easy axis direction of the MTJ element MTJ, and the side surfaces of the write word line WWL.

A wiring 27 is formed on the hard mask HM. A contact 26 is formed below the wiring 27. The contact 26 is formed in self-alignment with the hard mask HM, MTJ element MTJ, write word line WWL, and side insulating film 24. Accordingly, the contact 26 is in direct contact with the side surface of the side insulating film 24. A portion of the contact 26 covers the upper portion of the side insulating film 24. One side surface in the magnetic easy axis direction of the wiring 27 is aligned with the side surface of the contact 26, and the other side surface is aligned with the side surface of the side insulating film 24. A bit line BL is formed above the MTJ element MTJ so as to be spaced apart from the wiring 27.

Desirable examples of the material of the hard mask HM are metals (for example, Ru) that remain conductive even when oxidized, refractory metals (for example, Ta, Ti, and W) that relatively stably remain conductive even when oxidized, and refractory metal compounds (for example, TiN, TaN, and WN) having high oxidation resistance.

The material of the side insulating film 24 is desirably different from that of an interlayer insulating film 25. This is to increase the etching selectivity between the two materials during the formation of the contact 26. For example, when the interlayer insulating film 25 is silicon oxide (SiO2), the side insulating film 24 is preferably silicon nitride (SiN) or alumina (AlxOy).

The material of the side insulating film 16 and top insulating film 14 is desirably different from that of an interlayer insulating film 17. This is to increase the etching selectivity during the formation of the contact 18. For example, when the interlayer insulating film 17 is SiO2, the side insulating film 16 and top insulating film 14 are preferably SiN or AlxOy. Note that the side insulating film 16 and top insulating film 14 are desirably the same material in view of the adhesion of the material and the like, but they may also be different materials.

The thickness Tt1 of the top insulating film 14 is desirably greater than the thickness Ts1 of the side insulating film 16. This is to allow the top insulating film 14 to adequately protect the upper end portion and the like of the gate electrode 13 from being etched away during the formation of the contact 18.

The relationship between the film thickness Tt1 of the top insulating film 14 and the film thickness Ts1 of the side insulating film 16 desirably satisfies, for example, Tt1×⅓≦Ts1≦Tt1×½. The lower limit is mainly defined on the basis of the etching selectivity during the formation of the contact 18 and the insulation breakdown voltage. The upper limit is defined so as to ensure a minimum necessary width of the contact hole (particularly, the side width of the contact hole) when the contact 18 is formed by etching.

The film thickness of the side insulating film 16 is, for example, about 10 to 50 nm. The film thickness of the side insulating film 24 is, for example, about 10 to 50 nm. The film thicknesses of the side insulating films 16 and 24 are adjusted by damage absorption during etching and the dielectric breakdown voltage.

FIGS. 3 to 9 are sectional views showing the manufacturing steps of the basic example of the magnetic random access memory according to the first embodiment of the present invention. A method of manufacturing the basic example of the magnetic random access memory according to the first embodiment will be explained below.

First, as shown in FIG. 3, element isolation regions STI having an STI (Shallow Trench Isolation) structure are formed in a semiconductor substrate (for example, a silicon substrate) 11. Then, a gate insulating film 12 is formed on the semiconductor substrate 11, and a gate electrode 13 made of polysilicon or the like is formed on the gate insulating film 12. A top insulating film 14 is formed on the gate electrode 13. The top insulating film 14 is, for example, SiN. After that, the gate insulating film 12, gate electrode 13, and top insulating film 14 are patterned into a desired shape. Subsequently, source/drain diffusion layers 15 are formed in the semiconductor substrate 11. The gate electrodes 13 function as, for example, read word lines RWL.

As shown in FIG. 4, a side insulating film 16 is formed on the semiconductor substrate 11 and top insulating films 14, and patterned to remain on the side surfaces of the gate insulating films 12, gate electrodes 13, and top insulating films 14. The side insulating film 16 is, for example, SiN.

As shown in FIG. 5, an interlayer insulating film 17 of SiO2 or the like is formed on the semiconductor substrate 11 and top insulating films 14. Contact holes are formed in the interlayer insulating film 17 by reactive ion etching (RIE) or the like, and filled with tungsten (W) or the like to form contacts 18. Each contact 18 can be formed in self-alignment with the side insulating film 16 and gate electrode 13 by forming the contact hole so as to expose the side surface of the side insulting film 16.

As shown in FIG. 6, wirings 19 connecting to the contacts 18 are formed and buried with an interlayer insulating film 20. The interlayer insulating film 20 is then planarized until the wirings 19 are exposed. Subsequently, an interlayer insulating film 21 of SiO2 or the like is formed on the wirings 19 and interlayer insulating film 20. A wiring 22 of, for example, AlCu is formed on the interlayer insulating film 21. An MTJ element film 23 and hard mask HM are formed on the wiring 22. After the hard mask HM is patterned, the wiring 22 and MTJ element film 23 are patterned into a desired shape. In this manner, bit lines BL and MTJ elements MTJ are formed.

As shown in FIG. 7, side insulating films 24 are formed on the side surfaces of the bit lines BL, MTJ elements MTJ, and hard masks HM. The side insulating film 24 is, for example, SiN.

As shown in FIG. 8, an interlayer insulating film 25 of, for example, SiO2 is formed to cover the hard masks HM, and planarized until the hard masks HM are exposed. After that, contact holes are formed in the interlayer insulating films 21 and 25 by RIE or the like, thereby partially exposing the side insulating films 24. In this step, the hard masks HM are sometimes partially exposed when the contact holes are formed. Contacts 26 are formed by burying W or the like in the contact holes. The contacts 26 are connected to the wirings 19.

Since the side insulating film 24 (for example, an SiN film) and the interlayer insulating film 25 (for example, an SiO2 film) are of different materials, the etching selectivity between them is high. Each contact hole is formed adjacent to the MTJ element MTJ so as to expose the side surface of the side insulating film 24. In this manner, the contact 26 can be formed in self-alignment with the side insulating film 24, write word line WWL, MTJ element MTJ, and hard mask HM.

As shown in FIG. 9, a wiring 27 is formed on the hard masks HM and contacts 26, and patterned into a desired shape. The wirings 27 electrically connect the hard masks HM and transistors Tr.

Finally, as shown in FIG. 1, the wirings 27 are buried with an interlayer insulating film 28, and a wiring 29 having a desired shape is formed on the interlayer insulating film 28. The wiring 29 functions as a bit line BL.

[1-2] Modification Example of Magnetic Random Access Memory

FIG. 10 is a sectional view showing a modification example of the magnetic random access memory according to the first embodiment of the present invention. This modification example of the magnetic random access memory according to the first embodiment will be explained below.

As shown in FIG. 10, the hard mask HM and wiring 27 need not be in direct contact with each other, but can also be connected via a contact 32. In this case, a top insulating film 31 is desirably formed on the upper surface of the hard mask HM. This is to protect the hard mask HM and the MTJ element MTJ from being partially etched away during the formation of the contact 26.

The top insulating film 31 and a side insulating film 24 desirably consist of a material that increases the etching selectivity to the interlayer insulating films 21 and 25 around them. Therefore, when the interlayer insulating films 21 and 25 are, for example, SiO2, the top insulating film 31 and side insulating film 24 are preferably, for example, SiN or AlxOy. Note that while the top insulting film 31 and side insulating film 24 are desirably the same material in view of the adhesion of the material and the like, they may also be different materials.

The top insulating film 31 is desirably thicker than the side insulating film 24. This is to allow the top insulating film 31 to adequately protect the upper end portions and the like of the hard mask HM and MTJ element MTJ from being etched away during the formation of the contact 26.

FIGS. 11 and 12 are sectional views showing the manufacturing steps of the modification example of the magnetic random access memory according to the first embodiment of the present invention. A method of manufacturing the modification example of the magnetic random access memory according to the first embodiment will be explained below.

First, after the steps shown in FIGS. 3 to 5 described above are performed, as shown in FIG. 11, the wirings 19 connecting to the contacts 18 are formed and buried with the interlayer insulating film 20. The interlayer insulating film 20 is then planarized until the wirings 19 are exposed. Subsequently, the interlayer insulating film 21 is formed on the wirings 19 and interlayer insulating film 20. The wiring 22 made of, for example, AlCu is formed on the interlayer insulating film 21. The MTJ element film 23 is formed on the wiring 22, and the hard mask HM is formed on the MTJ element film 23. A top insulating film 31 is formed on the hard mask HM. The top insulating film 31 consists of, for example, SiN. After that, the wiring 22, MTJ element film 23, hard mask HM, and top insulating film 31 are patterned into a desired shape. In this way, the bit lines BL and MTJ elements MTJ are formed. The side insulating films 24 are formed on the side surfaces of the bit lines BL, MTJ elements MTJ, hard masks HM, and top insulating films 31. The side insulating film 24 consists of, for example, SiN.

As shown in FIG. 12, an interlayer insulating film 25 of SiO2 or the like is formed and selectively removed by RIE, and the top insulating films 31 are also selectively removed by RIE. This forms contact holes that expose the hard masks HM. Contacts 32 connecting to the MTJ elements MTJ are formed by burying W or the like in these contact holes. After that, the contacts 26, wirings 27, and a bit line BL are sequentially formed following the same procedures as above.

The modification example as described above can achieve the same effect as in the structure shown in FIG. 1, and can also achieve the following effects by forming the contacts 32. That is, this modification example can make the contact area between the MTJ element MTJ (hard mask HM) and wiring 27 smaller than that in the structure shown in FIG. 1. This alleviates the influence of stress, and facilitates magnetic design. It is also possible to suppress etching damage to the MTJ element MTJ when the wiring 27 is processed.

[1-3] MTJ Element (1) Structure

FIG. 13 is a sectional view of the MTJ element according to the first embodiment of the present invention. This MTJ element will be explained below.

As shown in FIG. 13, the MTJ element MTJ has a fixed layer PF in which magnetization is fixed in one axial direction, a recording layer FF in which magnetization reverses, a nonmagnetic layer NF sandwiched between the fixed layer PF and recording layer FF, and an antiferromagnetic layer (not shown) that fixes magnetization in the fixed layer PF.

Each of the fixed layer PF and recording layer FF is not limited to a single layer as shown in FIG. 13. For example, each of the fixed layer PF and recording layer FF may also be a stacked film made up of a plurality of ferromagnetic layers. At least one of the fixed layer PF and recording layer FF can have an antiferromagnetic coupling structure which includes three layers, i.e., a first ferromagnetic layer/nonmagnetic layer/second ferromagnetic layer, and in which the first and second ferromagnetic layers magnetically couple with each other (interlayer exchange coupling) such that the magnetization directions in these layers are antiparallel, or a ferromagnetic coupling structure in which the first and second ferromagnetic layers magnetically couple with each other (interlayer exchange coupling) such that the magnetization directions in these layers are parallel.

The nonmagnetic layer NF is not limited to a single-junction structure including one nonmagnetic layer as shown in FIG. 13. For example, the MTJ element MTJ may also have a double-junction structure having two nonmagnetic layers. The MTJ element MTJ having this double-junction structure has a first fixed layer, a second fixed layer, a recording layer formed between the first and second fixed layers, a first nonmagnetic layer formed between the first fixed layer and recording layer, and a second nonmagnetic layer formed between the second fixed layer and recording layer.

The planar shape of the MTJ element MTJ is not limited to a rectangle and can be variously changed. Examples are an ellipse, circle, hexagon, rhomb, parallelogram, cross, and bean (recessed shape). To decrease the cell size, however, the planar shape of the MTJ element MTJ is preferably a rectangle of F (short side)×2F (long side).

The fixed layer PF, nonmagnetic layer NF, and recording layer FF of the MTJ element MTJ are simultaneously processed to have the same planar shape. However, the present invention is not limited to this embodiment. For example, it is also possible to give the fixed layer PF and nonmagnetic layer NF a rectangular shape and only the recording layer FF a cross shape.

(2) Materials

The following ferromagnetic materials are used as the materials of the fixed layer PF and recording layer FF. Favorable examples are Fe, Co, Ni, and their stacked films and alloys, magnetite having a high spin polarization ratio, oxides such as CrO2 and RXMnO3-y (R; rare earth element, X; Ca, Ba, and Sr), and Heusler alloys such as NiMnSb and PtMnSb. These magnetic materials can more or less contain nonmagnetic elements such as Ag, Cu, Au, Al, Mg, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Ir, W, Mo, and Nb, provided that the materials do not loose ferromagnetism.

As the material of the nonmagnetic layer NF, it is possible to use various dielectrics such as Al2O3, SiO2, MgO, AlN, Bi2O3, MgF2, CaF2, SrTiO2, and AlLaO3. These dielectrics may have oxygen, nitrogen, and fluorine deficiencies.

When an insulator such as MgO (magnesium oxide) or AlO (aluminum oxide, for example, Al2O3) is used as the nonmagnetic layer NF, the MTJ element MTJ has the TMR (Tunneling Magneto Resistive) effect. When a metal such as Cu or Pt is used as the nonmagnetic layer NF, the MTJ element MTJ has the GMR (Giant Magneto Resistive) effect.

(3) Magnetization Arrangement

FIGS. 14A, 14B, 15A, and 15B are views showing parallel and antiparallel magnetization arrangements of the MTJ element according to the first embodiment of the present invention.

As shown in FIGS. 14A and 15A, the tunnel resistance of the nonmagnetic layer NF is a minimum when the magnetization directions in the fixed layer PF and recording layer FF of the MTJ element MTJ are parallel (the same). This state is regarded as, for example, a “1” state.

On the other hand, as shown in FIGS. 14B and 15B, the tunnel resistance of the nonmagnetic layer NF is a maximum when the magnetization directions in the fixed layer PF and recording layer FF of the MTJ element MTJ are antiparallel (opposite). This state is regarded as, for example, a “0” state.

Note that the magnetization stabilizing directions in the fixed layer PF and recording layer FF can be a parallel magnetization type, i.e., parallel to the film surface as shown in FIGS. 14A and 14B, or a perpendicular magnetization type, i.e., perpendicular to the film surface as shown in FIGS. 15A and 15B.

[1-4] Write Method (1) Magnetic Field Write

When using magnetic field write as a write method, data write to the MTJ element MTJ is performed as follows.

A bit line BL and write word line WWL corresponding to the MTJ element MTJ of a selected cell are selected, and write currents are supplied to the selected bit line BL and write word line WWL. A synthetic magnetic field generated by the write currents is applied to the MTJ element MTJ to make the magnetization directions in the MTJ element MTJ parallel or antiparallel.

For example, the write current in the bit line BL flows in one direction, and the write current in the write word line WWL flows in both directions. In this case, the magnetization direction in the recording layer of the MTJ element MTJ is changed by changing the direction of the write current flowing through the write word line WWL. Note that the write current in the bit line BL may also flow in both directions.

(2) Spin-Transfer Write

Spin-transfer write will be explained below with reference to FIGS. 14A and 14B. Note that the flow directions of electrons e1 and e2 are of course opposite to those of electric currents.

First, as shown in FIG. 14A, when the write current is supplied from the fixed layer PF to the recording layer FF, electrons that are spin-polarized (to be referred to as spin-polarized electrons hereinafter) e1 flow from the recording layer FF to the fixed layer PF. Electrons having spins parallel to the fixed layer PF are transmitted through it, and electrons having spins antiparallel to the fixed layer PF are reflected by it. Consequently, the magnetization directions in the recording layer FF and fixed layer PF form an antiparallel magnetization arrangement.

On the other hand, as shown in FIG. 14B, when the write current is supplied from the recording layer FF to the fixed layer PF, spin-polarized electrons e2 are injected from the fixed layer PF into the recording layer FF. As a consequence, the magnetization directions in the fixed layer PF and recording layer FF form a parallel magnetization arrangement.

Note that data write to the MTJ element MTJ can also be performed by combining (1) magnetic field write and (2) spin-transfer write.

[1-5] Read Method

Data read from the MTJ element MTJ is performed by applying a voltage (or current) between the write word line WWL and read word line RWL, and detecting a current (or voltage) by a sense amplifier (not shown), thereby determining whether the MTJ element MTJ is in the “1” or “0” state.

The resistance is low if the magnetization arrangement in the MTJ element MTJ is parallel (for example, the “1” state), and high if the magnetization arrangement is antiparallel (for example, the “0” state). Accordingly, whether the MTJ element is “1” or “0” can be determined by reading the difference between these resistance values.

[1-6] Effect

The first embodiment described above forms the contact 26, which connects the MTJ element MTJ and switching element, in self-alignment with the write word line WWL and MTJ element MTJ, thereby implementing the structure in which the contact 26 is in direct contact with the side insulating film 24 of the write word line WWL and MTJ element MTJ. That is, the first embodiment can decrease the cell size because the contact 26 that connects the MTJ element MTJ and MOS transistor Tr can be formed adjacent to the MTJ element MTJ. More specifically, as shown in FIG. 2A, letting F (Feature size) be the short side (the width in the magnetic hard axis direction) of the MTJ element MTJ and 2F be the long side (the width in the magnetic easy axis direction), a cell of 2F×4F=8F2 can be implemented. This makes it possible to decrease the cell size.

[2] Second Embodiment

In the first embodiment, the contact connecting to the switching element is formed beside an MTJ element. The second embodiment further decreases the cell size by forming a contact connecting to a switching element below the MTJ element.

[2-1] Basic Example of Magnetic Random Access Memory

FIG. 16 is a sectional view showing a basic example of a magnetic random access memory according to the second embodiment of the present invention. FIG. 17A is a plan view showing the periphery of an MTJ element according to the second embodiment of the present invention. FIG. 17B is a plan view showing the periphery of a gate electrode according to the second embodiment of the present invention. The basic example of the magnetic random access memory according to the second embodiment will be explained below.

As shown in FIG. 16, the difference of the second embodiment from the first embodiment is the peripheral structure of an MTJ element MTJ explained below.

A wiring 27 is formed on a contact 26 connecting to a source/drain diffusion layer 15 of a MOS transistor Tr. The MTJ element MTJ is formed in contact with the upper surface of the wiring 27. The MTJ element MTJ has the same planar shape as the wiring 27. The side surfaces in the magnetic easy axis direction of the MTJ element MTJ are aligned with the side surfaces in the magnetic easy axis direction of the wiring 27, and the side surfaces in the magnetic hard axis direction of the MTJ element MTJ are aligned with the side surfaces in the magnetic hard axis direction of the wiring 27. A hard mask HM is formed on the MTJ element MTJ, and a bit line BL is formed on the hard mask HM.

A write word line WWL is formed below the MTJ element MTJ so as to be spaced apart from the wiring 27. Side insulating films 42 are formed on the side surfaces in the magnetic easy axis direction of the write word line WWL, and a top insulating film 41 is formed on the upper surface of the write word line WWL. The contact 26 is formed in self-alignment with the write word line WWL and side insulating film 42. Therefore, the contact 26 is in direct contact with the side insulating film 42. A portion of the contact 26 covers the upper portion of the side insulating film 42.

Adjacent MOS transistors Tr share a source contact 18 of contacts 18 connected to the source/drain diffusion layers 15 of the MOS transistors Tr. Accordingly, the distance between adjacent gate electrodes 13 is about the sum of the width of the contact 18 and the film thickness of a side insulating film 16.

The material of the side insulating film 42 and top insulating film 41 is desirably different from that of an interlayer insulating film 25. This is to increase the etching selectivity between the two materials during the formation of the contact 26. For example, when the interlayer insulating film 25 is SiO2, the side insulating film 42 and top insulating film 41 are preferably SiN or AlxOy. Note that the top insulating film 41 and side insulating film 42 are desirably the same material in view of the adhesion of the material and the like, but they may also be different materials.

The thickness Ts2 of the side insulating film 42 is, for example, about 10 to 50 nm. The thickness Ts2 of the side insulating film 42 can be less than the thickness Tt2 of the top insulating film 41. For example, it is favorable to satisfy Tt2×⅓≦Ts2≦Tt2×½. The lower limit is mainly defined on the basis of the etching selectivity during the formation of the contact 26 and the insulation breakdown voltage. The upper limit is defined so as to ensure a minimum necessary width of the contact hole (particularly, the side width of the contact hole) when the contact 26 is formed by etching.

FIGS. 18 to 22 are sectional views showing the manufacturing steps of the basic example of the magnetic random access memory according to the second embodiment of the present invention. A method of manufacturing the basic example of the magnetic random access memory according to the second embodiment will be explained below.

First, contacts 18 are formed in self-alignment with side insulating films 16 and gate electrodes 13 through the steps shown in FIGS. 3 to 5 described previously.

As shown in FIG. 18, wirings 19 connecting to the contacts 18 are formed and buried with an interlayer insulating film 20. The interlayer insulating film 20 is then planarized until the wirings 19 are exposed. Subsequently, an interlayer insulating film 21 of SiO2 or the like is formed on the wirings 19 and interlayer insulating film 20. A wiring 22 made of, for example, AlCu is formed on the interlayer insulating film 21. A top insulating film 41 of, for example, SiN is formed on the wiring 22. After that, the wiring 22 and top insulating film 41 are patterned into a desired shape, thereby forming write word lines WWL.

As shown in FIG. 19, a side insulating film 42 is formed on the top insulating films 41 and interlayer insulating film 21. The side insulating film 42 is, for example, SiN.

As shown in FIG. 20, the side insulating film 42 is selectively removed by RIE or the like and left behind on the side surfaces of write word lines WWL and top insulating films 41.

As shown in FIG. 21, an interlayer insulating film 25 is formed on the top insulating films 41, side insulating films 42, and interlayer insulating film 21, thereby covering the top insulating films 41. The interlayer insulating film 25 is, for example, SiO2. The interlayer insulating film 25 is then planarized by CMP or the like to expose the top insulating films 41. In this step, the interlayer insulating film 25 may sometimes partially remain on the top insulating films 41. Subsequently, contact holes are formed in the interlayer insulating films 21 and 25 by RIE or the like, thereby partially exposing the side insulating films 42. Contacts 26 are formed by burying W or the like in the contact holes. The contacts 26 are connected to the wirings 19.

Since the top insulating film 41 and side insulating film 42 (for example, SiN films) and the interlayer insulating films 21 and 25 (for example, SiO2 films) are different materials, the etching selectivity between them is high. Each contact hole is formed adjacent to the write word line WWL so as to expose the side surface of the side insulating film 42. In this manner, the contact 26 can be formed in self-alignment with the side insulating film 42 and write word line WWL.

As shown in FIG. 22, a wiring 27 is formed on the contacts 26 and interlayer insulating film 25, and an MTJ element film 23 is formed on the wiring 27. A hard mask HM is formed on the MTJ element film 23 and patterned. After that, the wiring 27 and MTJ element film 23 are patterned into a desired shape. This forms wirings 27 and MTJ elements MTJ having the same planar shape.

Finally, as shown in FIG. 16, the MTJ elements MTJ are buried with an interlayer insulating film 28, and the interlayer insulating film 28 is planarized until the hard masks HM are exposed. Subsequently, a wiring 29 having a desired shape is formed on the interlayer insulating film 28 and MTJ elements MTJ. The wiring 29 functions as a bit line BL.

[2-2] Modification Examples of Magnetic Random Access Memory (1) Modification Example 1

FIG. 23 is a sectional view showing modification example 1 of the magnetic random access memory according to the second embodiment. Modification example 1 of the magnetic random access memory according to the second embodiment will be explained below.

As shown in FIG. 23, modification example 1 forms the write word line WWL by the damascene process. Therefore, while the side insulating films 42 are formed on only the side surfaces of the write word line WWL in the structure shown in FIG. 16, an insulating film 52 formed on the side surfaces of the write word line WWL is also formed on the bottom surface of the write word line WWL in the structure shown in FIG. 23.

In the structure shown in FIG. 23, a barrier metal film 53 is desirably formed between the write word line WWL and insulating film 52 in order to ensure the reliability of a wiring. However, the barrier metal film 53 need not always be formed. A top insulating film 54 is formed on the write word line WWL, barrier metal film 53, and insulating film 52. The upper surface of the top insulating film 54 and that of the contact 26 are in direct contact with the bottom surface of the wiring 27.

The contact 26 is formed in self-alignment with the insulating film 52 and a bit line BL. Therefore, the side surface of the contact 26 is in direct contact with that of the insulating film 52.

The top insulating film 54 and insulating film 52 are desirably a material which increases the etching selectivity to an interlayer insulating film 51 around them. Accordingly, when the interlayer insulating film 51 is, for example, SiO2, the top insulating film 54 and insulating film 52 are preferably, for example, SiN films, AlxOy films, stacked films of SiN/Ta/NiFe/Ta, or FexOy films.

The top insulating film 54 is desirably thicker than the insulating film 52. This is to allow the top insulating film 54 to adequately protect the upper end portions and the like of the write word line WWL from being etched away during the formation of the contact 26.

FIGS. 24 to 28 are sectional views showing the manufacturing steps of modification example 1 of the magnetic random access memory according to the second embodiment of the present invention. A method of manufacturing modification example 1 of the magnetic random access memory according to the second embodiment will be explained below. Although the damascene process of the write word line WWL will be explained, other manufacturing steps are the same as those of the basic example of the magnetic random access memory according to the second embodiment described above.

First, as shown in FIG. 24, trenches 50 are formed in an interlayer insulating film 51 of, for example, SiO2 by selectively removing it by RIE or the like. An insulating film 52 is formed in the trenches 50 and on the interlayer insulating film 51. A barrier metal film 53 is formed on the insulating film 52. The insulating film 52 is, for example, SiN, and the barrier metal film 53 is a Ta-based material such as TaN. A wiring 22 made of Cu or the like is formed on the barrier metal film 53. After that, the wiring 22, barrier metal film 53, and insulating film 52 are planarized by CMP or the like, thereby exposing the interlayer insulating film 51.

Then, as shown in FIG. 25, a recess 55 is formed in the upper portion of each trench 50 by removing the upper portions of the wiring 22, barrier metal film 53, and insulating film 52.

As shown in FIG. 26, a top insulting film 54 is formed on the recesses 55 and interlayer insulating film 51. The top insulating film 54 is, for example, SiN.

As shown in FIG. 27, the top insulating film 54 on the interlayer insulating film 51 is removed by CMP or the like, and left behind in only the recesses 55.

As shown in FIG. 28, contact holes are formed in the interlayer insulating film 51 by RIE or the like, and contacts 26 are formed by burying, for example, W in these contact holes. The contacts 26 are connected to wirings 19 (not shown).

Since the top insulating film 54 (for example, an SiN film) and insulating film 52 (for example, an SiN film) and the interlayer insulating film 51 (for example, an SiO2 film) are different materials, the etching selectivity between them is high. Each contact hole is formed adjacent to a write word line WWL so as to expose the side surface of the insulating film 52. In this manner, the contact 26 can be formed in self-alignment with the insulating film 52 and write word line WWL.

As described above, modification example 1 forms the write word line WWL by the damascene process. This makes the MTJ element MTJ and write word line WWL closer to each other than in FIG. 16. Accordingly, the write current in the write word line WWL can be reduced.

(2) Modification Example 2

FIG. 29 is a sectional view of modification example 2 of the magnetic random access memory according to the second embodiment of the present invention. Modification example 2 of the magnetic random access memory according to the second embodiment will be explained below.

As shown in FIG. 29, the hard mask HM and bit line BL need not be in direct contact with each other, but may also be connected via a contact 62. The contact 62 can be formed by forming a contact hole in an interlayer insulating film 61, and burying a metal material in this contact hole.

Note that the contact hole 62 and bit line BL need not always be formed by separately burying metal materials. For example, the contact 62 and bit line BL can also be formed by forming a contact hole of the contact 62 and a trench of the bit line BL, and simultaneously burying a metal material in these contact hole and trench.

Modification example 2 as described above can achieve the same effect as the structure shown in FIG. 16, and can also achieve the following effects by the formation of the contact 62. That is, modification example 2 can make the contact area between the MTJ element MTJ (hard mask HM) and bit line BL smaller than that in the structure shown in FIG. 16. This alleviates the influence of stress, and facilitates magnetic design. It is also possible to suppress etching damage to the MTJ element MTJ when the bit line BL is processed.

[2-3] MTJ Element

The MTJ element MTJ according to the second embodiment is the same as that according to the first embodiment described previously, so an explanation thereof will be omitted.

[2-4] Write Method

Similar to the write method according to the first embodiment, a write method according to the second embodiment uses one of magnetic field write and spin-transfer write.

The second embodiment differs from the first embodiment in the arrangement of the bit line BL and write word line WWL.

In the first embodiment, as shown in FIG. 2A, the bit line BL runs in the magnetic hard axis direction of the MTJ element MTJ, and the write word line WWL runs in the magnetic easy axis direction of the MTJ element MTJ. Since a write line running in the magnetic hard axis direction of the MTJ element MTJ is the bit line BL, therefore, a write current supplied to the bit line BL produces a magnetic field in the magnetic easy axis direction of the MTJ element MTJ. So, this write current in the bit line BL desirably flows in both directions.

On the other hand, in the second embodiment, as shown in FIG. 17A, the write word line WWL runs in the magnetic hard axis direction of the MTJ element MTJ, and the bit line BL runs in the magnetic easy axis direction of the MTJ element MTJ. Since a write line running in the magnetic hard axis direction of the MTJ element MTJ is the write word line WWL, therefore, a write current supplied to the write word line WWL produces a magnetic field in the magnetic easy axis direction of the MTJ element MTJ. So, this write current in the write word line WWL desirably flows in both directions.

[2-5] Read Method

A read method according to the second embodiment is the same as the read method according to the first embodiment described above, so an explanation thereof will be omitted.

[2-6] Effect

The second embodiment described above forms the contact 26, which connects the MTJ element MTJ and switching element, and the write word line WWL in a region below the MTJ element MTJ. Also, the second embodiment forms the contact 26 in self-alignment with the write word line WWL, thereby implementing the structure in which the contact 26 is in direct contact with the side insulating film 42 of the write word line WWL. That is, the second embodiment can decrease the cell size because the contact 26 that connects the MTJ element MTJ and MOS transistor Tr can be formed adjacent to the write word line WWL. More specifically, as shown in FIG. 17A, letting F be the short side (the width in the magnetic hard axis direction) of the MTJ element MTJ and 2F be the long side (the width in the magnetic easy axis direction), a cell of 2F×3F=6F2 can be implemented. This makes it possible to make the cell size smaller than that in the first embodiment.

[3] Third Embodiment

In the third embodiment, the side insulating films and the like in the first and second embodiments are magnetic insulating films. For example, a magnetic insulating material is used to form the side insulating films 24 shown in FIGS. 1 and 10, the side insulating films 42 shown in FIGS. 16 and 29, and the insulating film 52 shown in FIG. 23.

Examples of this magnetic insulating material are insulating ferrite, and (Fe, Co)—(B, Si, Hf, Zr, Sm, Ta, Al)—(F, O, N)-based metal-nonmetal nano-granular films. More specifically, the insulating ferrite is at least one of Mn—Zn-ferrite, Ni—Zn-ferrite, MnFeO, CuFeO, FeO, and NiFeO.

The third embodiment described above can achieve the same effects as the first and second embodiments.

In addition, in the third embodiment, a magnetic insulating film covers the side surfaces of a bit line BL or write word line WWL. This magnetic insulating film achieves the effect as a yoke, and makes it possible to efficiently apply to a selected cell a current magnetic field generated by the bit line BL or write word line WWL. Since this reduces the write current, the power consumption can be reduced.

Also, since the magnetic insulating film covers the side surfaces of the bit line BL or write word line WWL, it is possible to more efficiently interrupt a leakage magnetic field to an adjacent MTJ element MTJ. This suppresses write errors.

Note that it is also possible to form a magnetic insulating film 71 on the bottom surface of the write word line WWL as shown in FIGS. 30 and 31, or on the bottom surface of the bit line BL as shown in FIGS. 32 and 33. This makes it possible to more efficiently apply the write current to a selected cell, thereby increasing the write current reducing effect.

[4] Fourth Embodiment

The fourth embodiment is an example using a diode as a switching element.

FIGS. 34 and 35 are sectional views showing a magnetic random access memory according to the fourth embodiment of the present invention. This magnetic random access memory according to the fourth embodiment will be explained below.

As shown in FIGS. 34 and 35, the difference from each embodiment described above is that a diode D is used as a switching element instead of a MOS transistor. The diode D is, for example, a p-n junction diode and has a p-type diffusion layer 81 and n-type diffusion layer 82.

The above fourth embodiment can achieve the same effects as the individual embodiments described above. In addition, the use of the diode D as a switching element eliminates the influence of the size of a MOSFET, so the cell density can further increase.

[5] Fifth Embodiment

The fifth embodiment is an example using a so-called “via hole process” or “dual damascene process” as the method of forming the contacts 26 and wirings 27 in each embodiment described above.

FIGS. 36A to 36C are schematic sectional views showing magnetic random access memory manufacturing steps using the via hole process according to the fifth embodiment of the present invention. The via hole process according to the fifth embodiment will be briefly explained below.

As shown in FIG. 36A, a hole 26′ is formed in an interlayer insulating film 25. Then, as shown in FIG. 36B, a metal material 90 consisting of AlCu or the like is formed by sputtering to fill the hole 26′. As shown in FIG. 36C, the metal material 90 on the interlayer insulating film 25 is processed by RIE. Consequently, a contact 26 and wiring 27 are formed.

FIGS. 37A to 37D are schematic sectional views showing magnetic random access memory manufacturing steps using the dual damascene process according to the fifth embodiment of the present invention. The dual damascene process according to the fifth embodiment will be briefly explained below.

As shown in FIG. 37A, a wiring trench 27′ is formed in an interlayer insulating film 25. Then, as shown in FIG. 37B, a hole is formed in the interlayer insulating film 25 from the bottom surface of the wiring trench 27′, thereby forming a hole 26′. As shown in FIG. 37C, a metal material 90 consisting of Cu or the like is formed by sputtering to fill the wiring trench 27′ and hole 26′. As shown in FIG. 37D, the metal material 90 is planarized by CMP until the interlayer insulating film 25 is exposed. As a result, a contact 26 and wiring 27 are formed.

Note that FIGS. 36A to 36C and 37A to 37D are schematic views, so the shapes of the contact 26 and wiring 27 can be variously changed to be applicable to each embodiment. It is of course also possible to add, around the contact 26 and wiring 27, an element (for example, the bit line BL shown in FIG. 1) existing in each embodiment.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (5)

1. A magnetic random access memory manufacturing method comprising:
forming a switching element on a semiconductor substrate;
forming a first wiring above the switching element;
forming, on the first wiring, a magnetoresistive effect element having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer;
forming a first side insulating film on side surfaces of the first wiring, and the magnetoresistive effect element;
forming a first interlayer insulating film covering the magnetoresistive effect element;
forming a first contact hole which exposes a portion of the first side insulating film;
forming, in the first contact hole, a first contact connecting to the switching element;
forming a second wiring above the first contact and the magnetoresistive effect element to electrically connect the magnetoresistive effect element and the switching element by the second wiring; and
forming a second interlayer insulating film on the second wiring.
2. The method according to claim 1, wherein a side surface of the magnetoresistive effect element and the side surface of the first wiring are simultaneously processed.
3. The method according to claim 1, further comprising forming a second contact hole in the first interlayer insulating film above the magnetoresistive effect element to connect the magnetoresistive effect element with the second wiring.
4. A magnetic random access memory manufacturing method comprising:
forming a switching element on a semiconductor substrate;
forming a first wiring above the switching element;
forming a top insulating film on the first wiring;
forming a first side insulating film on side surfaces of the first wiring and the top insulating film;
forming a first interlayer insulating film covering the first side insulating film and the top insulating film;
exposing the top insulating film by planarizing the first interlayer insulating film;
forming a contact hole which exposes a portion of the first side insulating film;
forming, in the contact hole, a first contact connecting to the switching element;
forming a second wiring on the first contact and the top insulating film to electrically connect the second wiring and the switching element;
forming, on the second wiring, a magnetoresistive effect element having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer; and
forming a third wiring above the magnetoresistive effect element.
5. A magnetic random access memory manufacturing method comprising:
forming a switching element on a semiconductor substrate;
forming a first wiring above the switching element by a damascene process to form a first insulating film on side and bottom surfaces of the first wiring;
forming a top insulating film on the first wiring and the first insulating film;
forming a first interlayer insulating film covering the top insulating film;
exposing the top insulating film by planarizing the first interlayer insulating film;
forming a contact hole which exposes a portion of the first insulating film;
forming, in the contact hole, a first contact connecting to the switching element;
forming a second wiring on the first contact and the top insulating film to electrically connect the second wiring and the switching element;
forming, on the second wiring, a magnetoresistive effect element having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer; and
forming a third wiring above the magnetoresistive effect element.
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Cited By (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110317470A1 (en) * 2010-06-24 2011-12-29 The Regents Of The University Of Michigan Rectification element and method for resistive switching for non volatile memory device
US8374018B2 (en) 2010-07-09 2013-02-12 Crossbar, Inc. Resistive memory using SiGe material
US8391049B2 (en) 2010-09-29 2013-03-05 Crossbar, Inc. Resistor structure for a non-volatile memory device and method
US8394670B2 (en) 2011-05-31 2013-03-12 Crossbar, Inc. Vertical diodes for non-volatile memory device
US8404553B2 (en) 2010-08-23 2013-03-26 Crossbar, Inc. Disturb-resistant non-volatile memory device and method
US8441835B2 (en) 2010-06-11 2013-05-14 Crossbar, Inc. Interface control for improved switching in RRAM
US8450209B2 (en) 2010-11-05 2013-05-28 Crossbar, Inc. p+ Polysilicon material on aluminum for non-volatile memory device and method
US8450710B2 (en) 2011-05-27 2013-05-28 Crossbar, Inc. Low temperature p+ silicon junction material for a non-volatile memory device
US8467227B1 (en) 2010-11-04 2013-06-18 Crossbar, Inc. Hetero resistive switching material layer in RRAM device and method
US8492195B2 (en) 2010-08-23 2013-07-23 Crossbar, Inc. Method for forming stackable non-volatile resistive switching memory devices
US8519485B2 (en) 2010-06-11 2013-08-27 Crossbar, Inc. Pillar structure for memory device and method
US8558212B2 (en) 2010-09-29 2013-10-15 Crossbar, Inc. Conductive path in switching material in a resistive random access memory device and control
US8658476B1 (en) 2012-04-20 2014-02-25 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
US8659929B2 (en) 2011-06-30 2014-02-25 Crossbar, Inc. Amorphous silicon RRAM with non-linear device and operation
US8716098B1 (en) 2012-03-09 2014-05-06 Crossbar, Inc. Selective removal method and structure of silver in resistive switching device for a non-volatile memory device
US8765566B2 (en) 2012-05-10 2014-07-01 Crossbar, Inc. Line and space architecture for a non-volatile memory device
US8791010B1 (en) 2010-12-31 2014-07-29 Crossbar, Inc. Silver interconnects for stacked non-volatile memory device and method
US8796658B1 (en) 2012-05-07 2014-08-05 Crossbar, Inc. Filamentary based non-volatile resistive memory device and method
US8809831B2 (en) 2010-07-13 2014-08-19 Crossbar, Inc. On/off ratio for non-volatile memory device and method
US8815696B1 (en) 2010-12-31 2014-08-26 Crossbar, Inc. Disturb-resistant non-volatile memory device using via-fill and etchback technique
US8884261B2 (en) 2010-08-23 2014-11-11 Crossbar, Inc. Device switching using layered device structure
US8889521B1 (en) 2012-09-14 2014-11-18 Crossbar, Inc. Method for silver deposition for a non-volatile memory device
US8930174B2 (en) 2010-12-28 2015-01-06 Crossbar, Inc. Modeling technique for resistive random access memory (RRAM) cells
US8934280B1 (en) 2013-02-06 2015-01-13 Crossbar, Inc. Capacitive discharge programming for two-terminal memory cells
US8946669B1 (en) 2012-04-05 2015-02-03 Crossbar, Inc. Resistive memory device and fabrication methods
US8947908B2 (en) 2010-11-04 2015-02-03 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8946046B1 (en) 2012-05-02 2015-02-03 Crossbar, Inc. Guided path for forming a conductive filament in RRAM
US8946673B1 (en) 2012-08-24 2015-02-03 Crossbar, Inc. Resistive switching device structure with improved data retention for non-volatile memory device and method
US8982647B2 (en) 2012-11-14 2015-03-17 Crossbar, Inc. Resistive random access memory equalization and sensing
US9012307B2 (en) 2010-07-13 2015-04-21 Crossbar, Inc. Two terminal resistive switching device structure and method of fabricating
US9087576B1 (en) 2012-03-29 2015-07-21 Crossbar, Inc. Low temperature fabrication method for a three-dimensional memory device and structure
US9112145B1 (en) 2013-01-31 2015-08-18 Crossbar, Inc. Rectified switching of two-terminal memory via real time filament formation
US9153623B1 (en) 2010-12-31 2015-10-06 Crossbar, Inc. Thin film transistor steering element for a non-volatile memory device
US9191000B2 (en) 2011-07-29 2015-11-17 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US9252191B2 (en) 2011-07-22 2016-02-02 Crossbar, Inc. Seed layer for a p+ silicon germanium material for a non-volatile memory device and method
US9312483B2 (en) 2012-09-24 2016-04-12 Crossbar, Inc. Electrode structure for a non-volatile memory device and method
US9324942B1 (en) 2013-01-31 2016-04-26 Crossbar, Inc. Resistive memory cell with solid state diode
US9401475B1 (en) 2010-08-23 2016-07-26 Crossbar, Inc. Method for silver deposition for a non-volatile memory device
US9406379B2 (en) 2013-01-03 2016-08-02 Crossbar, Inc. Resistive random access memory with non-linear current-voltage relationship
US9412790B1 (en) 2012-12-04 2016-08-09 Crossbar, Inc. Scalable RRAM device architecture for a non-volatile memory device and method
US9460788B2 (en) 2014-07-09 2016-10-04 Crossbar, Inc. Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor
US9520557B2 (en) 2008-10-20 2016-12-13 The Regents Of The University Of Michigan Silicon based nanoscale crossbar memory
US9543359B2 (en) 2011-05-31 2017-01-10 Crossbar, Inc. Switching device having a non-linear element
US9564587B1 (en) 2011-06-30 2017-02-07 Crossbar, Inc. Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
US9570678B1 (en) 2010-06-08 2017-02-14 Crossbar, Inc. Resistive RAM with preferental filament formation region and methods
US9576616B2 (en) 2012-10-10 2017-02-21 Crossbar, Inc. Non-volatile memory with overwrite capability and low write amplification
US9583701B1 (en) 2012-08-14 2017-02-28 Crossbar, Inc. Methods for fabricating resistive memory device switching material using ion implantation
USRE46335E1 (en) 2010-11-04 2017-03-07 Crossbar, Inc. Switching device having a non-linear element
US9601692B1 (en) 2010-07-13 2017-03-21 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US9601690B1 (en) 2011-06-30 2017-03-21 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US9620206B2 (en) 2011-05-31 2017-04-11 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US9627443B2 (en) 2011-06-30 2017-04-18 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
US9633723B2 (en) 2011-06-23 2017-04-25 Crossbar, Inc. High operating speed resistive random access memory
US9633724B2 (en) 2014-07-07 2017-04-25 Crossbar, Inc. Sensing a non-volatile memory device utilizing selector device holding characteristics
US9685483B2 (en) 2014-07-09 2017-06-20 Crossbar, Inc. Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process
US9685608B2 (en) 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US9698201B2 (en) 2014-07-09 2017-07-04 Crossbar, Inc. High density selector-based non volatile memory cell and fabrication
US9729155B2 (en) 2011-07-29 2017-08-08 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US9735358B2 (en) 2012-08-14 2017-08-15 Crossbar, Inc. Noble metal / non-noble metal electrode for RRAM applications
US9741765B1 (en) 2012-08-14 2017-08-22 Crossbar, Inc. Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
US9761635B1 (en) 2014-03-11 2017-09-12 Crossbar, Inc. Selector device for two-terminal memory
US9768234B2 (en) 2014-05-20 2017-09-19 Crossbar, Inc. Resistive memory architecture and devices
US10056907B1 (en) 2011-07-29 2018-08-21 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US10096362B1 (en) 2017-03-24 2018-10-09 Crossbar, Inc. Switching block configuration bit comprising a non-volatile memory cell
US10115819B2 (en) 2015-05-29 2018-10-30 Crossbar, Inc. Recessed high voltage metal oxide semiconductor transistor for RRAM cell
US10211397B1 (en) 2014-07-07 2019-02-19 Crossbar, Inc. Threshold voltage tuning for a volatile selection device
US10290801B2 (en) 2014-02-07 2019-05-14 Crossbar, Inc. Scalable silicon based resistive memory device

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8141235B1 (en) 2006-06-09 2012-03-27 Western Digital (Fremont), Llc Method for manufacturing a perpendicular magnetic recording transducers
US7919826B2 (en) * 2007-04-24 2011-04-05 Kabushiki Kaisha Toshiba Magnetoresistive element and manufacturing method thereof
US8125040B2 (en) * 2008-04-18 2012-02-28 Qualcomm Incorporated Two mask MTJ integration for STT MRAM
US8264052B2 (en) * 2008-08-28 2012-09-11 Qualcomm Incorporated Symmetric STT-MRAM bit cell design
US7884433B2 (en) * 2008-10-31 2011-02-08 Magic Technologies, Inc. High density spin-transfer torque MRAM process
US8587993B2 (en) 2009-03-02 2013-11-19 Qualcomm Incorporated Reducing source loading effect in spin torque transfer magnetoresisitive random access memory (STT-MRAM)
JP2010225783A (en) * 2009-03-23 2010-10-07 Toshiba Corp Semiconductor memory device
US9099118B1 (en) 2009-05-26 2015-08-04 Western Digital (Fremont), Llc Dual damascene process for producing a PMR write pole
US8486285B2 (en) 2009-08-20 2013-07-16 Western Digital (Fremont), Llc Damascene write poles produced via full film plating
US8169816B2 (en) * 2009-09-15 2012-05-01 Magic Technologies, Inc. Fabrication methods of partial cladded write line to enhance write margin for magnetic random access memory
US8817531B2 (en) 2010-06-30 2014-08-26 International Business Machines Corporation Magnetic random access memory device and method for producing a magnetic random access memory device
US8730719B1 (en) 2010-12-03 2014-05-20 Iii Holdings 1, Llc MRAM with metal gate write conductors
EP3157060B1 (en) 2010-12-17 2018-03-07 Everspin Technologies, Inc. Magnetic random access memory integration having improved scaling
JP5740225B2 (en) 2011-06-29 2015-06-24 株式会社東芝 A method of manufacturing a resistance change memory
KR20130016827A (en) * 2011-08-09 2013-02-19 에스케이하이닉스 주식회사 Semiconductor device and method for fabricating the same
KR101713871B1 (en) 2013-03-14 2017-03-09 삼성전자주식회사 Magnetoresistive random access device and method of manufacturing the same
KR20140112672A (en) 2013-03-14 2014-09-24 삼성전자주식회사 Magnetoresistive random access device and method of manufacturing the same
KR20150015920A (en) * 2013-08-02 2015-02-11 삼성전자주식회사 Magnetic random access memory device and method of manufacturing the same
US9190260B1 (en) * 2014-11-13 2015-11-17 Globalfoundries Inc. Topological method to build self-aligned MTJ without a mask
JP2016181598A (en) * 2015-03-24 2016-10-13 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same
US10109331B2 (en) 2016-03-01 2018-10-23 Toshiba Memory Corporation Magnetic storage device with a wiring having a ferromagnetic layer

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030123199A1 (en) * 2001-12-28 2003-07-03 Nec Corporation Semiconductor memory device using tunneling magnetoresistive elements
JP2004080051A (en) 2003-11-04 2004-03-11 Oki Electric Ind Co Ltd Nonvolatile semiconductor memory device
JP2004179187A (en) 2002-11-22 2004-06-24 Toshiba Corp Magnetoresistive effect element and magnetic memory
JP2005175357A (en) 2003-12-15 2005-06-30 Nissan Motor Co Ltd Semiconductor device and method of manufacturing the same
US6947315B2 (en) 2003-04-04 2005-09-20 Kabushiki Kaisha Toshiba Magnetic random access memory device having write test mode
US6958932B2 (en) * 2002-01-22 2005-10-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and method of manufacturing the same
US20050270828A1 (en) * 2004-05-24 2005-12-08 Sony Corporation Magnetic memory device and manufacturing method thereof
US6977401B2 (en) 2001-12-18 2005-12-20 Kabushiki Kaisha Toshiba Magnetic memory device having magnetic shield layer, and manufacturing method thereof
US7046545B2 (en) 2002-08-07 2006-05-16 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device including magnetoresistive effect device and method of manufacturing the same
US7164599B2 (en) 2005-04-14 2007-01-16 Kabushiki Kaisha Toshiba Data read method of magnetic random access memory
US20070076469A1 (en) * 2005-09-16 2007-04-05 Fujitsu Limited Magnetoresistive effect element and magnetic memory device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100615600B1 (en) * 2004-08-09 2006-08-25 삼성전자주식회사 High density magnetic random access memory device and method of fabricating the smae

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247505B2 (en) 2001-12-18 2007-07-24 Kabushiki Kaisha Toshiba Magnetic memory device having magnetic shield layer, and manufacturing method thereof
US6977401B2 (en) 2001-12-18 2005-12-20 Kabushiki Kaisha Toshiba Magnetic memory device having magnetic shield layer, and manufacturing method thereof
US20030123199A1 (en) * 2001-12-28 2003-07-03 Nec Corporation Semiconductor memory device using tunneling magnetoresistive elements
US6958932B2 (en) * 2002-01-22 2005-10-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and method of manufacturing the same
US20050274984A1 (en) 2002-01-22 2005-12-15 Keiji Hosotani Semiconductor integrated circuit device and method of manufacturing the same
US7046545B2 (en) 2002-08-07 2006-05-16 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device including magnetoresistive effect device and method of manufacturing the same
JP2004179187A (en) 2002-11-22 2004-06-24 Toshiba Corp Magnetoresistive effect element and magnetic memory
US6947315B2 (en) 2003-04-04 2005-09-20 Kabushiki Kaisha Toshiba Magnetic random access memory device having write test mode
JP2004080051A (en) 2003-11-04 2004-03-11 Oki Electric Ind Co Ltd Nonvolatile semiconductor memory device
JP2005175357A (en) 2003-12-15 2005-06-30 Nissan Motor Co Ltd Semiconductor device and method of manufacturing the same
US20050270828A1 (en) * 2004-05-24 2005-12-08 Sony Corporation Magnetic memory device and manufacturing method thereof
US7164599B2 (en) 2005-04-14 2007-01-16 Kabushiki Kaisha Toshiba Data read method of magnetic random access memory
US20070076469A1 (en) * 2005-09-16 2007-04-05 Fujitsu Limited Magnetoresistive effect element and magnetic memory device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
M. Durlam et al., "90nm Toggle MRAM Array with 0.29mum2 Cells," 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 186-187.
M. Durlam et al., "90nm Toggle MRAM Array with 0.29μm2 Cells," 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 186-187.
Roy Scheuerlein et al., "A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell," ISSCC 2000/Session 7 / TD: Emerging Memory & Device Technologies / Paper TA 7.2, 2000 IEEE International Solid State Circuits Conference, Feb. 2000, pp. 128-129.

Cited By (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520557B2 (en) 2008-10-20 2016-12-13 The Regents Of The University Of Michigan Silicon based nanoscale crossbar memory
US9570678B1 (en) 2010-06-08 2017-02-14 Crossbar, Inc. Resistive RAM with preferental filament formation region and methods
US8519485B2 (en) 2010-06-11 2013-08-27 Crossbar, Inc. Pillar structure for memory device and method
US8599601B2 (en) 2010-06-11 2013-12-03 Crossbar, Inc. Interface control for improved switching in RRAM
US8441835B2 (en) 2010-06-11 2013-05-14 Crossbar, Inc. Interface control for improved switching in RRAM
US8993397B2 (en) 2010-06-11 2015-03-31 Crossbar, Inc. Pillar structure for memory device and method
US8351241B2 (en) * 2010-06-24 2013-01-08 The Regents Of The University Of Michigan Rectification element and method for resistive switching for non volatile memory device
US20110317470A1 (en) * 2010-06-24 2011-12-29 The Regents Of The University Of Michigan Rectification element and method for resistive switching for non volatile memory device
US9048658B2 (en) 2010-06-24 2015-06-02 The Regents Of The University Of Michigan Resistive switching for non volatile memory device using an integrated breakdown element
US8750020B2 (en) 2010-06-24 2014-06-10 The Regents Of The University Of Michigan Resistive switching for non volatile memory device using an integrated breakdown element
US9627614B2 (en) 2010-06-24 2017-04-18 The Regents Of The University Of Michigan Resistive switching for non volatile memory device using an integrated breakdown element
US9036400B2 (en) 2010-07-09 2015-05-19 Crossbar, Inc. Method and structure of monolithically integrated IC and resistive memory using IC foundry-compatible processes
US8374018B2 (en) 2010-07-09 2013-02-12 Crossbar, Inc. Resistive memory using SiGe material
US8750019B2 (en) 2010-07-09 2014-06-10 Crossbar, Inc. Resistive memory using SiGe material
US9012307B2 (en) 2010-07-13 2015-04-21 Crossbar, Inc. Two terminal resistive switching device structure and method of fabricating
US8809831B2 (en) 2010-07-13 2014-08-19 Crossbar, Inc. On/off ratio for non-volatile memory device and method
US9755143B2 (en) 2010-07-13 2017-09-05 Crossbar, Inc. On/off ratio for nonvolatile memory device and method
US9601692B1 (en) 2010-07-13 2017-03-21 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8884261B2 (en) 2010-08-23 2014-11-11 Crossbar, Inc. Device switching using layered device structure
US9035276B2 (en) 2010-08-23 2015-05-19 Crossbar, Inc. Stackable non-volatile resistive switching memory device
US10224370B2 (en) 2010-08-23 2019-03-05 Crossbar, Inc. Device switching using layered device structure
US8648327B2 (en) 2010-08-23 2014-02-11 Crossbar, Inc. Stackable non-volatile resistive switching memory devices
US8492195B2 (en) 2010-08-23 2013-07-23 Crossbar, Inc. Method for forming stackable non-volatile resistive switching memory devices
US9590013B2 (en) 2010-08-23 2017-03-07 Crossbar, Inc. Device switching using layered device structure
US8404553B2 (en) 2010-08-23 2013-03-26 Crossbar, Inc. Disturb-resistant non-volatile memory device and method
US9401475B1 (en) 2010-08-23 2016-07-26 Crossbar, Inc. Method for silver deposition for a non-volatile memory device
US9412789B1 (en) 2010-08-23 2016-08-09 Crossbar, Inc. Stackable non-volatile resistive switching memory device and method of fabricating the same
US9129887B2 (en) 2010-09-29 2015-09-08 Crossbar, Inc. Resistor structure for a non-volatile memory device and method
US8912523B2 (en) 2010-09-29 2014-12-16 Crossbar, Inc. Conductive path in switching material in a resistive random access memory device and control
US8391049B2 (en) 2010-09-29 2013-03-05 Crossbar, Inc. Resistor structure for a non-volatile memory device and method
US8558212B2 (en) 2010-09-29 2013-10-15 Crossbar, Inc. Conductive path in switching material in a resistive random access memory device and control
USRE46335E1 (en) 2010-11-04 2017-03-07 Crossbar, Inc. Switching device having a non-linear element
US8947908B2 (en) 2010-11-04 2015-02-03 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8467227B1 (en) 2010-11-04 2013-06-18 Crossbar, Inc. Hetero resistive switching material layer in RRAM device and method
US8659933B2 (en) 2010-11-04 2014-02-25 Crossbar, Inc. Hereto resistive switching material layer in RRAM device and method
US8450209B2 (en) 2010-11-05 2013-05-28 Crossbar, Inc. p+ Polysilicon material on aluminum for non-volatile memory device and method
US8930174B2 (en) 2010-12-28 2015-01-06 Crossbar, Inc. Modeling technique for resistive random access memory (RRAM) cells
US9153623B1 (en) 2010-12-31 2015-10-06 Crossbar, Inc. Thin film transistor steering element for a non-volatile memory device
US8815696B1 (en) 2010-12-31 2014-08-26 Crossbar, Inc. Disturb-resistant non-volatile memory device using via-fill and etchback technique
US9831289B2 (en) 2010-12-31 2017-11-28 Crossbar, Inc. Disturb-resistant non-volatile memory device using via-fill and etchback technique
US8791010B1 (en) 2010-12-31 2014-07-29 Crossbar, Inc. Silver interconnects for stacked non-volatile memory device and method
US8450710B2 (en) 2011-05-27 2013-05-28 Crossbar, Inc. Low temperature p+ silicon junction material for a non-volatile memory device
US8394670B2 (en) 2011-05-31 2013-03-12 Crossbar, Inc. Vertical diodes for non-volatile memory device
US9620206B2 (en) 2011-05-31 2017-04-11 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US9543359B2 (en) 2011-05-31 2017-01-10 Crossbar, Inc. Switching device having a non-linear element
US9633723B2 (en) 2011-06-23 2017-04-25 Crossbar, Inc. High operating speed resistive random access memory
US9564587B1 (en) 2011-06-30 2017-02-07 Crossbar, Inc. Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
US9601690B1 (en) 2011-06-30 2017-03-21 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US9627443B2 (en) 2011-06-30 2017-04-18 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
US8659929B2 (en) 2011-06-30 2014-02-25 Crossbar, Inc. Amorphous silicon RRAM with non-linear device and operation
US9570683B1 (en) 2011-06-30 2017-02-14 Crossbar, Inc. Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
US9252191B2 (en) 2011-07-22 2016-02-02 Crossbar, Inc. Seed layer for a p+ silicon germanium material for a non-volatile memory device and method
US9191000B2 (en) 2011-07-29 2015-11-17 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US10056907B1 (en) 2011-07-29 2018-08-21 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US9729155B2 (en) 2011-07-29 2017-08-08 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US8716098B1 (en) 2012-03-09 2014-05-06 Crossbar, Inc. Selective removal method and structure of silver in resistive switching device for a non-volatile memory device
US9087576B1 (en) 2012-03-29 2015-07-21 Crossbar, Inc. Low temperature fabrication method for a three-dimensional memory device and structure
US8946669B1 (en) 2012-04-05 2015-02-03 Crossbar, Inc. Resistive memory device and fabrication methods
US9673255B2 (en) 2012-04-05 2017-06-06 Crossbar, Inc. Resistive memory device and fabrication methods
US9685608B2 (en) 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US8658476B1 (en) 2012-04-20 2014-02-25 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
US9793474B2 (en) 2012-04-20 2017-10-17 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
US8946046B1 (en) 2012-05-02 2015-02-03 Crossbar, Inc. Guided path for forming a conductive filament in RRAM
US9972778B2 (en) 2012-05-02 2018-05-15 Crossbar, Inc. Guided path for forming a conductive filament in RRAM
US9385319B1 (en) 2012-05-07 2016-07-05 Crossbar, Inc. Filamentary based non-volatile resistive memory device and method
US8796658B1 (en) 2012-05-07 2014-08-05 Crossbar, Inc. Filamentary based non-volatile resistive memory device and method
US8765566B2 (en) 2012-05-10 2014-07-01 Crossbar, Inc. Line and space architecture for a non-volatile memory device
US10096653B2 (en) 2012-08-14 2018-10-09 Crossbar, Inc. Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
US9741765B1 (en) 2012-08-14 2017-08-22 Crossbar, Inc. Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
US9735358B2 (en) 2012-08-14 2017-08-15 Crossbar, Inc. Noble metal / non-noble metal electrode for RRAM applications
US9583701B1 (en) 2012-08-14 2017-02-28 Crossbar, Inc. Methods for fabricating resistive memory device switching material using ion implantation
US8946673B1 (en) 2012-08-24 2015-02-03 Crossbar, Inc. Resistive switching device structure with improved data retention for non-volatile memory device and method
US8889521B1 (en) 2012-09-14 2014-11-18 Crossbar, Inc. Method for silver deposition for a non-volatile memory device
US9312483B2 (en) 2012-09-24 2016-04-12 Crossbar, Inc. Electrode structure for a non-volatile memory device and method
US9576616B2 (en) 2012-10-10 2017-02-21 Crossbar, Inc. Non-volatile memory with overwrite capability and low write amplification
US8982647B2 (en) 2012-11-14 2015-03-17 Crossbar, Inc. Resistive random access memory equalization and sensing
US9412790B1 (en) 2012-12-04 2016-08-09 Crossbar, Inc. Scalable RRAM device architecture for a non-volatile memory device and method
US9406379B2 (en) 2013-01-03 2016-08-02 Crossbar, Inc. Resistive random access memory with non-linear current-voltage relationship
US9324942B1 (en) 2013-01-31 2016-04-26 Crossbar, Inc. Resistive memory cell with solid state diode
US9112145B1 (en) 2013-01-31 2015-08-18 Crossbar, Inc. Rectified switching of two-terminal memory via real time filament formation
US8934280B1 (en) 2013-02-06 2015-01-13 Crossbar, Inc. Capacitive discharge programming for two-terminal memory cells
US10290801B2 (en) 2014-02-07 2019-05-14 Crossbar, Inc. Scalable silicon based resistive memory device
US10121540B1 (en) 2014-03-11 2018-11-06 Crossbar, Inc. Selector device for two-terminal memory
US9761635B1 (en) 2014-03-11 2017-09-12 Crossbar, Inc. Selector device for two-terminal memory
US9847130B1 (en) 2014-03-11 2017-12-19 Crossbar, Inc. Selector device for two-terminal memory
US9768234B2 (en) 2014-05-20 2017-09-19 Crossbar, Inc. Resistive memory architecture and devices
US10211397B1 (en) 2014-07-07 2019-02-19 Crossbar, Inc. Threshold voltage tuning for a volatile selection device
US10079060B2 (en) 2014-07-07 2018-09-18 Crossbar, Inc. Sensing a non-volatile memory device utilizing selector device holding characteristics
US9633724B2 (en) 2014-07-07 2017-04-25 Crossbar, Inc. Sensing a non-volatile memory device utilizing selector device holding characteristics
US9460788B2 (en) 2014-07-09 2016-10-04 Crossbar, Inc. Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor
US9698201B2 (en) 2014-07-09 2017-07-04 Crossbar, Inc. High density selector-based non volatile memory cell and fabrication
US10210929B1 (en) 2014-07-09 2019-02-19 Crossbar, Inc. Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor
US9685483B2 (en) 2014-07-09 2017-06-20 Crossbar, Inc. Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process
US10115819B2 (en) 2015-05-29 2018-10-30 Crossbar, Inc. Recessed high voltage metal oxide semiconductor transistor for RRAM cell
US10096362B1 (en) 2017-03-24 2018-10-09 Crossbar, Inc. Switching block configuration bit comprising a non-volatile memory cell

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