JP3875627B2 - Magnetic storage device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic memory device and a method of manufacturing the same, and more particularly, a magnetic memory device that performs writing by a current magnetic field for each bit and reads information of “1” and “0” by resistance change depending on the magnetization state of the cell, It relates to the manufacturing method.
[0002]
[Prior art]
In recent years, MRAM (Magnetic Random Access Memory) using a magnetoresistive effect has been proposed as a memory element. The MRAM is characterized in that data is written to the memory cell by changing the magnetization direction of the ferromagnetic material using a current magnetic field. Among these MRAMs, an MTJ (Magnetic Tunneling Junction) element using a tunneling magnetoresistive (TMR) effect can extract information on each of “1” and “0” by a change in resistance value. Further, in this MTJ element, the MR (Magneto Resistive) ratio, which is a resistance difference between “1” and “0”, has reached nearly 50%, which is a driving force for greatly progressing the practical use of MRAM.
[0003]
Here, in order to generate a current magnetic field in which information can be written in a memory cell including a magnetoresistive element such as an MTJ element, it is necessary to flow a sufficiently large write current through the write wiring. At present, the write current reaches several mA to 10 mA per write wiring. However, if the miniaturization is advanced, the distance between the magnetoresistive elements is shortened. Therefore, when a large write current is generated, there is a problem that the adjacent cells other than the selected cell are affected.
[0004]
One technique for overcoming this problem is “magnetic shielding”. This is achieved by covering only the current magnetic field wiring or both the current magnetic field wiring and the magnetoresistive element with a magnetic material and concentrating the generated magnetic field of the current magnetic field wiring on the selected cell by the same effect as the yoke, thereby reducing the selected cell with a small write current. It is a technology that can write information in.
[0005]
A known example of such a technique is the technique disclosed in Patent Document 1. In Patent Document 1, as shown in FIG. 61, an element isolation oxide film 72 is selectively formed on a semiconductor substrate 71, and a MOSFET 73 is selectively formed between the element isolation oxide films 72. A GMR (Giant Magneto Resistive) element 80 is connected to the source / drain diffusion layer of the MOSFET 73 via contacts 74, 76, 78 and first to third wirings 75, 77, 79. Above and below the GMR element 80, an upper word line 81 and a lower word line 82 for writing to the GMR element 80 with a current magnetic field are disposed apart from the GMR element 80. A magnetic shield layer 83 made of a non-conductive ferrite material is formed as a passivation film that covers the entire surface of such a memory cell array.
[0006]
In the above prior art, the stray magnetic field outside the magnetic shield layer 83 can be shielded by the nonconductive ferrite material. Further, the magnetic field generated by the write wirings 81 and 82 can be concentrated on the magnetic layer of the GMR element 80 as a recording unit.
[0007]
[Patent Document 1]
Japanese Patent Application No. 11-238377
[0008]
[Problems to be solved by the invention]
However, in the above prior art, when miniaturization as a magnetic memory is advanced, the effect of preventing erroneous writing due to a magnetic field leaking between adjacent cells is weak, and the effect of concentrating the magnetic field due to the current magnetic field wiring on the magnetic material is sufficient There was a problem that was not.
[0009]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a magnetic memory device capable of suppressing erroneous writing and concentrating a magnetic field on a selected cell, and a method for manufacturing the same. .
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention uses the following means.
[0011]
A magnetic memory device according to a first aspect of the present invention includes a first wiring extending in a first direction, a memory element disposed above the first wiring, and a memory element disposed on the memory element. A second wiring extending in a second direction different from the first direction; a first magnetic shield layer formed on a side surface of the second wiring and a side surface of the memory element; A third wiring disposed on the same plane as the first wiring, extending in parallel with the first wiring, connected to the memory element, and used as a read wiring; It comprises.
[0012]
According to a second aspect of the present invention, there is provided a method of manufacturing a magnetic memory device, comprising: forming a first wiring extending in a first direction; and selectively forming a memory element above the first wiring. A step of forming a first insulating layer around the memory element, and a second extending on the first insulating layer and the memory element in a second direction different from the first direction. Forming the first wiring, using the second wiring as a mask, removing the first insulating layer not covered with the second wiring, the first and second wirings, and Forming a first magnetic shield layer across the second wiring so as to cover the memory element.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention relate to a magnetic storage device (MRAM) using an MTJ (Magnetic Tunneling Junction) element using a tunneling magnetoresistive (TMR) effect as a storage element. .
[0014]
Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.
[0015]
[First Embodiment]
The first embodiment is a structure in which the magnetic shield layer is formed across the adjacent second wiring so as to cover the MTJ element and the second wiring, and the switching element is not used.
[0016]
FIG. 1A is a perspective view of a magnetic memory device according to the first embodiment of the present invention. FIG. 1B is a sectional view of the magnetic memory device taken along line IB-IB shown in FIG. FIG. 1C is a cross-sectional view of the magnetic memory device along the line IC-IC shown in FIG. The structure of the magnetic memory device according to the first embodiment will be described below.
[0017]
As shown in FIGS. 1A, 1B, and 1C, in the magnetic memory device according to the first embodiment, the first wiring 13 and the second wiring 20 extend in different directions. The MTJ element 18 electrically connected to the first and second wirings 13 and 20 is located at the intersection of the first and second wirings 13 and 20 between the first and second wirings 13 and 20. Has been placed. A magnetic shield layer 21 is formed so as to cover the side surface of the MTJ element 18 and the upper surface and side surface of the second wiring 20, and the magnetic shield layer 21 is continuously formed across the adjacent second wiring 20. ing.
[0018]
Here, the width X of the MTJ element 18 in the extending direction of the first wiring 13 is equal to the width of the second wiring 20, and the width Y of the MTJ element 18 in the extending direction of the second wiring 20 is the first width. It is equal to the width of the wiring 13. Therefore, the side surface in the extending direction of the second wiring 20 of the MTJ element 18 and the side surface in the extending direction of the second wiring 20 are substantially flat surfaces. The magnetic shield layer 21 is formed so as to cover this plane. Further, the interlayer insulating film 19 is embedded between the MTJ elements 18, and the film thicknesses of the interlayer insulating film 19 and the MTJ element 18 are substantially equal.
[0019]
In the case of the first embodiment, since the magnetic shield layer 21 is continuously formed so as to straddle between the adjacent second wirings 20, it is desirable to use an insulating material for the magnetic shield layer 21. This is because, when the magnetic shield layer 21 made of a conductive material is continuously formed so as to straddle between the second wirings 20, the adjacent second wirings 20 are electrically connected via the magnetic shield layer 21. This is because the MTJ element 18 separated for each cell is electrically connected.
[0020]
That is, the magnetic shield layer 21 is an insulating magnetic layer. Examples of the material of the insulating magnetic layer include insulating ferrite, (Fe, Co)-(B, Si, Hf, Zr, Sm, Ta, Al)-(F, O, N) system, etc. And metal-nonmetal nanogranular films. Specifically, the insulating ferrite is made of, for example, at least one material of Mn—Zn—ferrite, Ni—Zn—ferrite, MnFeO, CuFeO, FeO, and NiFeO.
[0021]
In the first embodiment, the first and second wirings 13 and 20 are arranged so as to be orthogonal to each other and have a structure suitable for forming a large-scale cell array. As long as the wirings 13 and 20 extend in different directions, they do not have to be orthogonal.
[0022]
In addition, the MTJ element 18 includes a magnetization pinned layer (magnetic layer) 14 with a fixed magnetization direction, a tunnel junction layer (nonmagnetic layer) 15, and a magnetic recording layer (magnetic layer) 16 with a reversed magnetization direction. It consists of three layers. Here, the positions of the magnetization pinned layer 14 and the magnetic recording layer 16 may be interchanged, and the MTJ element 18 may have a double tunnel junction layer even if it has a single tunnel junction structure composed of one tunnel junction layer 15. A double tunnel junction structure made of 15 may be used. Hereinafter, examples of the MTJ element 18 having a single tunnel junction structure or a double tunnel junction structure will be described.
[0023]
The MTJ element 18 having a single tunnel junction structure shown in FIG. 2A includes a magnetization pinned layer 14 in which a template layer 101, an initial ferromagnetic layer 102, an antiferromagnetic layer 103, and a reference ferromagnetic layer 104 are sequentially stacked. A tunnel junction layer 15 formed on the magnetization pinned layer 14 and a magnetic recording layer 16 in which a free ferromagnetic layer 105 and a contact layer 106 are sequentially laminated on the tunnel junction layer 15.
[0024]
The MTJ element 18 having a single tunnel junction structure shown in FIG. 2B includes a template layer 101, an initial ferromagnetic layer 102, an antiferromagnetic layer 103, a ferromagnetic layer 104 ′, a nonmagnetic layer 107, and a ferromagnetic layer 104 ″. Are sequentially stacked, a tunnel junction layer 15 formed on the magnetization pinned layer 14, and a ferromagnetic layer 105 ′, a nonmagnetic layer 107, and a ferromagnetic layer 105 ″ on the tunnel junction layer 15. And the magnetic recording layer 16 in which the contact layer 106 is sequentially laminated.
[0025]
2B, the MTJ element 18 shown in FIG. 2B has a three-layer structure including the ferromagnetic layer 104 ′, the nonmagnetic layer 107, and the ferromagnetic layer 104 ″ in the magnetization fixed layer 14, and the strong in the magnetic recording layer 16. By introducing a three-layer structure including a magnetic layer 105 ′, a nonmagnetic layer 107, and a ferromagnetic layer 105 ″, the generation of magnetic poles inside the ferromagnetic layer can be suppressed more than in the MTJ element 18 shown in FIG. Thus, a cell structure suitable for further miniaturization can be provided.
[0026]
The MTJ element 18 having a double tunnel junction structure shown in FIG. 3A includes a first magnetization pinned layer in which a template layer 101, an initial ferromagnetic layer 102, an antiferromagnetic layer 103, and a reference ferromagnetic layer 104 are sequentially stacked. 14a, the first tunnel junction layer 15a formed on the first magnetization pinned layer 14a, the magnetic recording layer 16 formed on the first tunnel junction layer 15a, and the magnetic recording layer 16 A second tunnel junction layer 15b formed on the first tunnel junction layer, and a reference ferromagnetic layer 104, an antiferromagnetic layer 103, an initial ferromagnetic layer 102, and a contact layer 106 are sequentially stacked on the second tunnel junction layer 15b. 2 magnetization pinned layers 14b.
[0027]
In the MTJ element 18 having a double tunnel junction structure shown in FIG. 3B, a template layer 101, an initial ferromagnetic layer 102, an antiferromagnetic layer 103, and a reference ferromagnetic layer 104 are sequentially stacked, and a first magnetization pinned layer 14a. A first tunnel junction layer 15a formed on the first magnetization pinned layer 14a, and a ferromagnetic layer 16 ′, a nonmagnetic layer 107, and a ferromagnetic layer 16 ″ on the first tunnel junction layer 15a. A magnetic recording layer 16 sequentially stacked in a three-layer structure, a second tunnel junction layer 15b formed on the magnetic recording layer 16, and a ferromagnetic layer 104 'on the second tunnel junction layer 15b. The nonmagnetic layer 107, the ferromagnetic layer 104 ″, the antiferromagnetic layer 103, the initial ferromagnetic layer 102, and the second magnetization pinned layer 14b in which the contact layer 106 are sequentially stacked.
[0028]
In the MTJ element 18 shown in FIG. 3B, the three-layer structure of the ferromagnetic layer 16 ′, the nonmagnetic layer 107, and the ferromagnetic layer 16 ″ constituting the magnetic recording layer 16, and the second magnetization fixed layer 14b. By introducing a three-layer structure including a ferromagnetic layer 104 ′, a nonmagnetic layer 107, and a ferromagnetic layer 104 ″, the generation of magnetic poles inside the ferromagnetic layer can be generated more than the MTJ element 18 shown in FIG. Cell structure suitable for further miniaturization can be provided.
[0029]
The MTJ element 18 having such a double tunnel junction structure has an MR (Magneto Resistive) ratio ("1" and "0") when the same external bias is applied as compared with the MTJ element 18 having a single tunnel junction structure. It is possible to operate at a higher bias with little deterioration of the resistance change rate in the state of (2). That is, the double tunnel junction structure is advantageous when reading information in the cell.
[0030]
The MTJ element 18 having such a single tunnel junction structure or a double tunnel junction structure is formed using, for example, the following materials.
[0031]
Examples of the material of the magnetic pinned layers 14, 14a, 14b and the magnetic recording layer 16 include Fe, Co, Ni, or an alloy thereof, magnetite having a high spin polarizability, and CrO. ₂ , RXMnO _3-y In addition to oxides such as (R: rare earth, X: Ca, Ba, Sr), it is preferable to use Heusler alloys such as NiMnSb and PtMnSb. In addition, these magnetic materials include Ag, Cu, Au, Al, Mg, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Ir, W, and Mo as long as ferromagnetism is not lost. , Nb and other nonmagnetic elements may be included.
[0032]
The material of the antiferromagnetic layer 103 constituting a part of the magnetization pinned layers 14, 14a, 14b includes Fe-Mn, Pt-Mn, Pt-Cr-Mn, Ni-Mn, Ir-Mn, NiO, and Fe. ₂ O _Three Etc. are preferably used.
[0033]
The material of the tunnel junction layers 15, 15a, 15b is Al. ₂ O _Three , SiO ₂ , MgO, AlN, Bi ₂ O _Three , MgF ₂ , CaF ₂ , SrTiO ₂ , AlLaO _Three Various dielectrics such as can be used. These dielectrics may have oxygen, nitrogen, or fluorine deficiency.
[0034]
4 (a), 4 (b), 4 (c) to 9 (a), 9 (b), and 9 (c) show the manufacturing process of the magnetic memory device according to the first embodiment of the present invention. Show. A method for manufacturing the magnetic memory device according to the first embodiment will be described below.
[0035]
First, as shown in FIGS. 4A, 4 B, and 4 C, the first interlayer insulating film 12 and the first wiring 13 are formed on the semiconductor substrate 11. Specifically, after the first wiring 13 is formed in a desired pattern by using RIE (Reactive Ion Etching), the first interlayer insulating film 12 is formed on the first wiring 13. The one interlayer insulating film 12 is planarized using CMP (Chemical Mechanical Polish) or an etch back method until the surface of the first wiring 13 is exposed.
[0036]
Next, as shown in FIGS. 5A, 5B, and 5C, a magnetization pinned layer 14 is deposited on the first interlayer insulating film 12 and the first wiring 13, and this magnetization pinned layer. A tunnel junction layer 15 is deposited on 14, and a magnetic recording layer 16 is deposited on the tunnel junction layer 15. As a result, a TMR material layer 17 including the magnetization pinned layer 14, the tunnel junction layer 15, and the magnetic recording layer 16 is formed.
[0037]
Next, as shown in FIGS. 6A, 6B, and 6C, the TMR material layer 17 is selectively etched using a mask material (not shown) and separated into cells. An island-shaped MTJ element 18 is formed. Next, a second interlayer insulating film 19 is formed on the first interlayer insulating film 12, the MTJ element 18 and the first wiring 13, and the surface of the MTJ element 18 is exposed in the second interlayer insulating film 19. Until planarized using CMP or etchback.
[0038]
Next, as shown in FIGS. 7A, 7 B, and 7 C, the MTJ element 18 and the second interlayer insulating film 19 are orthogonal to the extending direction of the first wiring 13. Then, the second wiring 20 is formed.
[0039]
Next, as shown in FIGS. 8A, 8B, and 8C, the second interlayer insulation exposed between the second wirings 20 using the second wiring 20 as a mask. The film 19 is removed until the first interlayer insulating film 12 and the first wiring 13 are exposed.
[0040]
Next, as shown in FIGS. 9A, 9 B, and 9 C, the magnetic shield layer 21 is formed on the second wiring 20, the first interlayer insulating film 12, and the first wiring 13. It is formed. At this time, the film thickness of the magnetic shield layer 21 is desirably set to be ½ or less of the space S between the second wirings 20. This is to prevent the magnetic shield layer 21 covering the side surface of the adjacent second wiring 20 from coming into contact.
[0041]
Next, as shown in FIGS. 1A, 1 B, and 1 C, a third interlayer insulating film 22 is deposited on the magnetic shield layer 21. Thereby, the memory cell array portion of the MRAM is completed.
[0042]
In the MRAM using the MTJ element 18 as a storage element as described above, data writing and reading are performed as follows.
[0043]
First, in writing data, a write current is supplied to both of the selected first and second wirings 13 and 20 to generate current magnetic fields, respectively, and a combined magnetic field of the two current magnetic fields is set to the first and second lines. This is applied to the MTJ element 18 located at the intersection of the wirings 13 and 20. As a result, the magnetization of the magnetic recording layer 16 having a magnetization reversal threshold lower than that of the magnetization pinned layer 14 is reversed, and the magnetization directions of the magnetic pinned layer 14 and the magnetic recording layer 16 are parallel to each other (for example, “0”). State) or states that are antiparallel to each other (for example, a state of “1”).
[0044]
On the other hand, when reading data, a current is passed through the MTJ element 18 in which a “0” state or a “1” state is written. Is done.
[0045]
According to the first embodiment, the upper surface and the side surface of the second wiring 20 and the side surface of the MTJ element 18 into which data is written using the second wiring 20 are covered with the magnetic shield layer 21. For this reason, the magnetic shield layer 21 sufficiently exhibits the effect as a yoke, and the current magnetic field generated by the second wiring 20 can be efficiently applied to the selected cell. Therefore, since the write current can be reduced, an MRAM that can reduce power consumption can be provided.
[0046]
Further, by covering the second wiring 20 and the MTJ element 18 with the magnetic shield layer 21, the leakage magnetic field to the adjacent MTJ element 18 arranged in the extending direction of the first wiring 13 is more efficiently blocked. be able to. Accordingly, erroneous writing can be suppressed.
[0047]
Further, by using the insulating magnetic shield layer 21, it is not necessary to divide the magnetic shield layer 21 between the adjacent second wirings 20. Thereby, since it is not necessary to keep the distance between the second wirings 20 large, the memory cell can be miniaturized.
[0048]
Further, the MTJ element 18 is used as a memory element. For this reason, a larger read signal can be obtained than in the case of using a GMR (Giant Magneto Resistive) element composed of two magnetic layers and a conductor layer sandwiched between these magnetic layers, and the read operation can be speeded up. it can.
[0049]
Also, the first and second wirings 13 and 20, the MTJ element 18, and the second interlayer insulating film 19 are formed in a self-aligned manner, thereby providing an MRAM suitable for miniaturization. it can.
[0050]
[Second Embodiment]
The second embodiment has a structure in which the magnetic shield layer is formed so as to straddle the adjacent second wiring so as to cover the MTJ element and the second wiring, and a diode is used as the switching element.
[0051]
10A and 10B are sectional views of a magnetic memory device according to the second embodiment of the present invention. Here, FIG. 10A shows a cross-sectional view of the magnetic memory device along the extending direction of the first wiring, and FIG. 10B shows the magnetic memory along the extending direction of the second wiring. A sectional view of the device is shown. The structure of the magnetic memory device according to the second embodiment will be described below. Only the structure different from the first embodiment will be described.
[0052]
As shown in FIGS. 10A and 10B, in the second embodiment, a diode 32 is provided as a read current switching element between the first wiring 13 and the MTJ element 18. The diode 32 has substantially the same shape as the MTJ element 18. That is, the side surface in the extending direction of the second wiring 20 of the diode 32, the side surface in the extending direction of the second wiring 20 of the MTJ element 18, and the side surface in the extending direction of the second wiring 20 are substantially the same. It is a flat surface with no steps. The magnetic shield layer 21 is continuously formed on this plane and the upper surface of the second wiring 20 across the adjacent second wiring 20.
[0053]
The magnetic shield layer 21 only needs to be formed on at least the side surfaces of the second wiring 20 and the MTJ element 18, and is not necessarily formed on the side surfaces of the diode 32. Further, since the magnetic shield layer 21 is continuously formed so as to straddle between the adjacent second wirings 20, it is desirable to use an insulating material for the magnetic shield layer 21.
[0054]
11 (a), 11 (b) to 15 (a), 15 (b) are cross-sectional views showing the manufacturing process of the magnetic memory device according to the second embodiment of the present invention. The method for manufacturing the magnetic memory device according to the second embodiment will be described below. In addition, the process similar to 1st Embodiment is demonstrated easily.
[0055]
First, as shown in FIGS. 11A and 11B, the first interlayer insulating film 12 and the first wiring 13 are formed on the semiconductor substrate 11.
[0056]
Next, as shown in FIGS. 12A and 12B, a diode material layer 31 is formed on the first interlayer insulating film 12 and the first wiring 13. Next, the TMR material layer 17 including the magnetization pinned layer 14, the tunnel junction layer 15, and the magnetic recording layer 16 is formed on the diode material layer 31.
[0057]
Next, as shown in FIGS. 13A and 13B, using a mask material (not shown), the TMR material layer 17 and the diode material layer 31 are selectively etched and separated for each cell. The island-shaped MTJ element 18 and the diode 32 are formed. Next, a second interlayer insulating film 19 is formed on the MTJ element 18 and the first wiring 13, and the CMP or etch-back method is used until the second interlayer insulating film 19 exposes the surface of the MTJ element 18. And flattened.
[0058]
Next, as shown in FIGS. 14A and 14B, the second wiring is formed on the MTJ element 18 and the second interlayer insulating film 19 so as to be orthogonal to the extending direction of the first wiring 13. A wiring 20 is formed.
[0059]
Next, as shown in FIGS. 15A and 15B, the second interlayer insulating film 19 exposed between the second wirings 20 is formed using the second wirings 20 as a mask. The first interlayer insulating film 12 and the first wiring 13 are removed until exposure. Next, the magnetic shield layer 21 is formed on the second wiring 20, the first interlayer insulating film 12, and the first wiring 13.
[0060]
Next, as shown in FIGS. 10A and 10B, a third interlayer insulating film 22 is deposited on the magnetic shield layer 21. Thereby, the memory cell array portion of the MRAM is completed.
[0061]
According to the second embodiment, not only the same effects as in the first embodiment can be obtained, but also the following effects can be obtained.
[0062]
In the first embodiment, since it has a matrix array structure, there is a possibility that current leaks in addition to the selected cell when reading data. This may cause a problem that the S / N ratio of the read signal deteriorates or the read speed becomes slow. On the other hand, in the second embodiment, by providing the diode 32 as a switching element, the read current can be supplied only to the selected cell using the rectification of the diode 32. For this reason, the S / N ratio of the read signal can be improved, and the read speed can be improved.
[0063]
In the second embodiment, the diode 32 may be disposed between the second wiring 20 and the MTJ element 18.
[0064]
[Third Embodiment]
The third embodiment has a structure in which the magnetic shield layer is formed so as to straddle the adjacent second wiring so as to cover the MTJ element and the second wiring, and a transistor is used as the switching element.
[0065]
FIGS. 16A and 16B are sectional views of a magnetic memory device according to the third embodiment of the present invention. Here, FIG. 16A shows a cross-sectional view of the magnetic memory device along the extending direction of the first wiring, and FIG. 16B shows the magnetic memory along the extending direction of the second wiring. A sectional view of the device is shown. The structure of the magnetic memory device according to the third embodiment will be described below. Only the structure different from the first embodiment will be described.
[0066]
As shown in FIGS. 16A and 16B, in the third embodiment, a MOSFET 44 is provided as a switching element for a read current. That is, a contact 45 connected to the source / drain diffusion layer 43 of the MOSFET 44 is formed, and a lower electrode 48 of the MTJ element 18 connected to the contact 45 is formed. The lower electrode 48 is formed apart from the first wiring 13 and is electrically connected to the MTJ element 18. The side surface of the lower electrode 48 in the extending direction of the second wiring 20, the side surface of the MTJ element 18 in the extending direction of the second wiring 20, and the side surface in the extending direction of the second wiring 20 are: The plane is almost flat. The magnetic shield layer 21 is continuously formed on this plane and the upper surface of the second wiring 20 across the adjacent second wiring 20.
[0067]
The magnetic shield layer 21 only needs to be formed on at least the side surfaces of the second wiring 20 and the MTJ element 18, and is not necessarily formed on the side surfaces of the lower electrode 48. Further, since the magnetic shield layer 21 is continuously formed so as to straddle between the adjacent second wirings 20, it is desirable to use an insulating material for the magnetic shield layer 21.
[0068]
FIGS. 17A, 17B to 21A, 21B are cross-sectional views showing the manufacturing process of the magnetic memory device according to the third embodiment of the present invention. The method for manufacturing the magnetic memory device according to the third embodiment will be described below. In addition, the process similar to 1st Embodiment is demonstrated easily.
[0069]
First, as shown in FIGS. 17A and 17B, the gate electrode 42 is selectively formed on the semiconductor substrate 11 via the gate insulating film 41. A source / drain diffusion layer 43 is formed in the semiconductor substrate 11 on both sides of the gate electrode 42. Thereby, MOSFET 44 as a switching element is formed. Next, the first interlayer insulating film 12 and the first wiring 13 are formed, and the fourth interlayer insulating film 46 is formed on the first interlayer insulating film 12 and the first wiring 13. Further, a contact 45 connected to the source / drain diffusion layer 43 is formed.
[0070]
Next, as shown in FIGS. 18A and 18B, a lower electrode material layer 47 is formed on the fourth interlayer insulating film 46 and the contact 45. Next, a TMR material layer 17 composed of the magnetization fixed layer 14, the tunnel junction layer 15, and the magnetic recording layer 16 is formed on the lower electrode material layer 47.
[0071]
Next, as shown in FIGS. 19A and 19B, using a mask material (not shown), the TMR material layer 17 is selectively etched, and island-like MTJs separated for each cell are separated. Element 18 is formed. Next, the lower electrode material layer 47 is selectively etched to form a lower electrode 48 having a desired shape. Next, a second interlayer insulating film 19 is formed on the MTJ element 18, the lower electrode 48, and the fourth interlayer insulating film 46, and the second interlayer insulating film 19 is subjected to CMP until the surface of the MTJ element 18 is exposed. Alternatively, planarization is performed using an etch back method.
[0072]
Next, as shown in FIGS. 20A and 20B, the second wiring is formed on the MTJ element 18 and the second interlayer insulating film 19 so as to be orthogonal to the extending direction of the first wiring 13. A wiring 20 is formed.
[0073]
Next, as shown in FIGS. 21A and 21B, the second interlayer insulating film 19 exposed between the second wirings 20 is formed by using the second wirings 20 as a mask. The fourth interlayer insulating film 46 is removed until exposure. Next, the magnetic shield layer 21 is formed on the second wiring 20 and the fourth interlayer insulating film 46.
[0074]
Next, as shown in FIGS. 16A and 16B, a third interlayer insulating film 22 is deposited on the magnetic shield layer 21. Thereby, the memory cell array portion of the MRAM is completed.
[0075]
According to the third embodiment, not only the same effects as in the first embodiment can be obtained, but also the following effects can be obtained.
[0076]
In the first embodiment, since it has a matrix array structure, there is a possibility that current leaks in addition to the selected cell when reading data. This may cause a problem that the S / N ratio of the read signal is deteriorated or the read speed is slow. On the other hand, in the third embodiment, by providing the MOSFET 44 as a switching element, a read current can be supplied only to the selected cell. For this reason, the S / N ratio of the read signal can be improved, and the read speed can be improved.
[0077]
Furthermore, since the read switch is the MOSFET 44, the compatibility with the normal CMOS process is good, and the application is easy when the memory cell as in the third embodiment is embedded in the logic circuit.
[0078]
[Fourth Embodiment]
The fourth embodiment is a modification of the first embodiment, in which the magnetic shield layer is divided for each second wiring.
[0079]
FIG. 22A is a perspective view of a magnetic memory device according to the fourth embodiment of the present invention. FIG. 22B shows a cross-sectional view of the magnetic memory device taken along line XXIIB-XXIIB shown in FIG. FIG. 22C is a sectional view of the magnetic memory device taken along line XXIIC-XXIIC shown in FIG. The structure of the magnetic memory device according to the fourth embodiment will be described below. Only the structure different from the first embodiment will be described.
[0080]
As shown in FIGS. 22A, 22B, and 22C, in the fourth embodiment, the magnetic shield layer 21a is formed only on the side surfaces of the second wiring 20 and the MTJ element 19. The second wiring 20 is not formed on the second wiring 20 or between the adjacent second wirings 20. That is, the magnetic shield layer 21 a is divided for each second wiring 20. Here, it is desirable to use an insulating material for the magnetic shield layer 21a in order to prevent the upper and lower magnetic layers 14 and 16 of the MTJ element 19 from being short-circuited.
[0081]
23 (a), 23 (b), and 23 (c) are cross-sectional views showing the manufacturing process of the magnetic memory device according to the fourth embodiment of the present invention. The method for manufacturing the magnetic memory device according to the fourth embodiment will be described below. Note that description of steps similar to those of the first embodiment is omitted.
[0082]
First, as shown in FIGS. 2A, 2B, 2C to 9A, 9B, and 9C, the second wiring 20 and the MTJ element 18 are covered. Then, the magnetic shield layer 21 is formed.
[0083]
Next, as shown in FIGS. 23A, 23B and 23C, the magnetic shield formed on the upper surface of the second wiring 20 by vertical anisotropic etching such as RIE, for example. The layer 21 and the magnetic shielding layer 21 formed on the first interlayer insulating film 12 and the first wiring 13 between the second wirings 20 are removed. As a result, the magnetic shield layer 21 a remains only on the side surface of the MTJ element 18, the side surface of the second interlayer insulating film 19, and the side surface of the second wiring 20.
[0084]
Next, as shown in FIGS. 22A, 22B, and 22C, on the magnetic shield layer 21a, the second wiring 20, the first wiring 13, and the first interlayer insulating film 12, A third interlayer insulating film 22 is deposited. Thereby, the memory cell array portion of the MRAM is completed.
[0085]
According to the fourth embodiment, the same effect as in the first embodiment can be obtained.
[0086]
[Fifth Embodiment]
The fifth embodiment is a modification of the second embodiment, in which the magnetic shield layer is divided for each second wiring.
[0087]
24A and 24B are cross-sectional views of a magnetic memory device according to the fifth embodiment of the present invention. Here, FIG. 24A shows a cross-sectional view of the magnetic memory device along the extending direction of the first wiring, and FIG. 24B shows the magnetic memory along the extending direction of the second wiring. A sectional view of the device is shown. The structure of the magnetic memory device according to the fifth embodiment will be described below. Only the structure different from the second embodiment will be described.
[0088]
As shown in FIGS. 24A and 24B, in the fifth embodiment, the magnetic shield layer 21a is formed only on the side surfaces of the diode 32, the second wiring 20, and the MTJ element 19, It is not formed on the second wiring 20 or between the adjacent second wirings 20. That is, the magnetic shield layer 21 a is divided for each second wiring 20. Here, it is desirable to use an insulating material for the magnetic shield layer 21a in order to prevent the upper and lower magnetic layers 14 and 16 of the MTJ element 19 from being short-circuited.
[0089]
The magnetic shield layer 21a may be formed at least on the side surfaces of the second wiring 20 and the MTJ element 18, and is not necessarily formed on the side surfaces of the diode 32.
[0090]
25 (a) and 25 (b) are cross-sectional views showing the manufacturing process of the magnetic memory device according to the fifth embodiment of the present invention. The method for manufacturing the magnetic memory device according to the fifth embodiment will be described below. Note that description of steps similar to those of the second embodiment is omitted.
[0091]
First, as shown in FIGS. 11A, 11B to 15A, 15B, the magnetic shield layer 21 is formed so as to cover the diode 32, the second wiring 20, and the MTJ element 18. It is formed.
[0092]
Next, as shown in FIGS. 25A and 25B, the magnetic shield layer 21 formed on the upper surface of the second wiring 20 by vertical anisotropic etching such as RIE, for example, The first interlayer insulating film 12 between the two wirings 20 and the magnetic shield layer 21 formed on the first wiring 13 are removed. As a result, the magnetic shield layer 21 a remains only on the side surface of the diode 32, the side surface of the MTJ element 18, the side surface of the second interlayer insulating film 19, and the side surface of the second wiring 20.
[0093]
Next, as shown in FIGS. 24A and 24B, a third interlayer insulation is formed on the magnetic shield layer 21a, the second wiring 20, the first wiring 13, and the first interlayer insulating film 12. A film 22 is deposited. Thereby, the memory cell array portion of the MRAM is completed.
[0094]
According to the fifth embodiment, the same effect as in the second embodiment can be obtained.
[0095]
[Sixth Embodiment]
The sixth embodiment is a modification of the third embodiment, in which the magnetic shield layer is divided for each second wiring.
[0096]
FIGS. 26A and 26B are cross-sectional views of a magnetic memory device according to the sixth embodiment of the present invention. Here, FIG. 26A shows a cross-sectional view of the magnetic memory device along the extending direction of the first wiring, and FIG. 26B shows the magnetic memory along the extending direction of the second wiring. A sectional view of the device is shown. The structure of the magnetic memory device according to the sixth embodiment will be described below. Only the structure different from that of the third embodiment will be described.
[0097]
As shown in FIGS. 26A and 26B, in the sixth embodiment, the magnetic shield layer 21a is formed only on the side surfaces of the lower electrode 48, the second wiring 20 and the MTJ element 19, It is not formed on the second wiring 20 or between the adjacent second wirings 20. That is, the magnetic shield layer 21 a is divided for each second wiring 20. Here, it is desirable to use an insulating material for the magnetic shield layer 21a in order to prevent the upper and lower magnetic layers 14 and 16 of the MTJ element 19 from being short-circuited.
[0098]
The magnetic shield layer 21 a is only required to be formed on at least the side surfaces of the second wiring 20 and the MTJ element 18, and is not necessarily formed on the side surfaces of the lower electrode 48.
[0099]
27A and 27B are cross-sectional views showing the manufacturing process of the magnetic memory device according to the sixth embodiment of the present invention. The method for manufacturing the magnetic memory device according to the sixth embodiment will be described below. Note that description of steps similar to those of the third embodiment is omitted.
[0100]
First, as shown in FIGS. 17A, 17B to 21A, 21B, the magnetic shield layer 21 is formed so as to cover the lower electrode 48, the second wiring 20, and the MTJ element 18. Is formed.
[0101]
Next, as shown in FIGS. 27A and 27B, the magnetic shield layer 21 formed on the upper surface of the second wiring 20 by vertical anisotropic etching such as RIE, for example, The first interlayer insulating film 12 between the two wirings 20 and the magnetic shield layer 21 formed on the first wiring 13 are removed. As a result, the magnetic shield layer 21 a remains only on the side surface of the lower electrode 48, the side surface of the MTJ element 18, the side surface of the second interlayer insulating film 19, and the side surface of the second wiring 20.
[0102]
Next, as shown in FIGS. 26A and 26B, a third interlayer insulation is formed on the magnetic shield layer 21a, the second wiring 20, the first wiring 13, and the first interlayer insulating film 12. A film 22 is deposited. Thereby, the memory cell array portion of the MRAM is completed.
[0103]
According to the sixth embodiment, the same effect as in the third embodiment can be obtained.
[0104]
[Seventh Embodiment]
The seventh embodiment is a modification of the first embodiment. Like the fourth embodiment, the magnetic shield layer is divided into second wires, and the magnetic shield layer is also formed on the second wires. Is an example.
[0105]
FIG. 28 is a sectional view of a magnetic memory device according to the seventh embodiment of the present invention. The structure of the magnetic memory device according to the seventh embodiment will be described below. Only the structure different from the first embodiment will be described.
[0106]
As shown in FIG. 28, the magnetic memory device according to the seventh embodiment includes the first magnetic shield layer 21 a formed on the side surfaces of the second wiring 20 and the MTJ element 19, and the second wiring 20. The formed second magnetic shield layer 51 is provided. That is, since it is not formed between the adjacent second wirings 20, the magnetic shield layer 21 a is divided for each second wiring 20 as in the fourth embodiment. Here, the first magnetic shield layer 21a is preferably made of an insulating material in order to prevent the upper and lower magnetic layers 14 and 16 of the MTJ element 19 from being short-circuited. Further, the second magnetic shield layer 51 is not limited to an insulating material, and a conductive material can also be used.
[0107]
That is, when a conductive magnetic layer is used for the second magnetic shield layer 51, examples of the material of the conductive magnetic layer include a Ni—Fe alloy, a Co—Fe alloy, a Co—Fe—Ni alloy, Examples include Co- (Zr, Hf, Nb, Ta, Ti) -based amorphous materials and (Co, Fe, Ni)-(Si, B)-(P, Al, Mo, Nb, Mn) -based amorphous materials. .
[0108]
FIG. 29 is a cross-sectional view showing the manufacturing process of the magnetic memory device according to the seventh embodiment of the present invention. The method for manufacturing the magnetic memory device according to the seventh embodiment will be described below. Note that description of steps similar to those of the first embodiment is omitted.
[0109]
First, as shown in FIGS. 2 (a), 2 (b), 2 (c) to 8 (a), 8 (b), and 8 (c), the second wiring 20 is used as a mask. The second interlayer insulating film 19 exposed between the two wirings 20 is removed until the first interlayer insulating film 12 and the first wiring 13 are exposed.
[0110]
Next, as shown in FIG. 29, a magnetic shield layer 51 is formed on the second wiring 20. Next, the magnetic shield layer 21 is formed so as to cover the magnetic shield layer 51, the second wiring 20, and the MTJ element 18.
[0111]
Next, as shown in FIG. 28, the first between the magnetic shield layer 21 formed on the upper surface of the second wiring 20 and the second wiring 20 by vertical anisotropic etching such as RIE, for example. The interlayer insulating film 12 and the magnetic shield layer 21 formed on the first wiring 13 are removed. As a result, the magnetic shield layer 21 a remains on the side surface of the MTJ element 18, the side surface of the second interlayer insulating film 19, and the side surface of the second wiring 20, and the magnetic shield layer 51 remains on the second wiring 20. Is done. Next, a third interlayer insulating film 22 is deposited on the magnetic shield layer 51, the first wiring 13, and the first interlayer insulating film 12. Thereby, the memory cell array portion of the MRAM is completed.
[0112]
According to the seventh embodiment, the same effect as in the first embodiment can be obtained.
[0113]
Furthermore, since the magnetic shield layers 21a and 51 are separated for each adjacent second wiring 20 as in the fourth embodiment, the material of the magnetic shield layer 51 is not limited to an insulating material, A conductive material can also be used. For this reason, the selectivity of the material of the magnetic shield layer 51 can be improved.
[0114]
Further, in the seventh embodiment, since the magnetic shield layer 51 is also formed on the second wiring 20, the effects of suppressing erroneous writing and concentrating the magnetic field on the selected cell are improved as compared with the fourth embodiment. Can be increased.
[0115]
In addition, although 7th Embodiment was applied to the structure of 1st Embodiment, it is not limited to this. For example, as shown in FIGS. 30A and 30B, the present invention can be applied to a magnetic memory device including a diode 32 as a switching element as in the second embodiment. As shown in 31 (a) and 31 (b), the present invention can be applied to a magnetic memory device including a MOSFET 44 as a switching element as in the third embodiment.
[0116]
[Eighth Embodiment]
The eighth embodiment is a modification of the first embodiment, in which the side surfaces of the second wiring and the MTJ element are covered with an insulating layer, and the magnetic shield layer is formed across the adjacent second wiring. is there.
[0117]
FIG. 32 is a sectional view of a magnetic memory device according to the eighth embodiment of the present invention. The structure of the magnetic memory device according to the eighth embodiment will be described below. Only the structure different from the first embodiment will be described.
[0118]
As shown in FIG. 32, in the magnetic memory device according to the eighth embodiment, side wall insulating layers 61 are formed on the side surfaces of the second wiring 20 and the MTJ element 19, and the magnetic shield is formed on the second wiring 20. A layer 51 is formed, and the magnetic shield layer 21 is formed so as to cover the sidewall insulating layer 61 and the magnetic shield layer 51. In other words, in the eighth embodiment, by providing the sidewall insulating layer 61, the adjacent second wiring 20 and the MTJ element 18 can be electrically separated, and therefore the second wiring 20 adjacent to the magnetic shield layer 21 is provided. It is formed continuously across the bridge.
[0119]
Here, when, for example, an insulating material is used for the magnetic shield layer 51, the magnetic shield layer 21 is not limited to the insulating material, and a conductive material can also be used. On the other hand, when, for example, a conductive material is used for the magnetic shield layer 51, it is desirable to use an insulating material for the magnetic shield layer 21 in order to prevent the adjacent second wiring 20 from being short-circuited. .
[0120]
The magnetic shield layer 51 on the second wiring 20 is not necessarily formed, and the magnetic shield layer 21 may be directly formed on the second wiring 20.
[0121]
FIG. 33 is a cross-sectional view of the magnetic memory device manufacturing process according to the eighth embodiment of the present invention. The method for manufacturing the magnetic memory device according to the eighth embodiment will be described below. Note that description of steps similar to those of the first embodiment is omitted.
[0122]
First, as shown in FIGS. 2 (a), 2 (b), 2 (c) to 8 (a), 8 (b), and 8 (c), the second wiring 20 is used as a mask. The second interlayer insulating film 19 exposed between the two wirings 20 is removed until the first interlayer insulating film 12 and the first wiring 13 are exposed.
[0123]
Next, as shown in FIG. 33, the magnetic shield layer 51 is formed on the second wiring 20. Next, a sidewall insulating film 61 is formed on the side surfaces of the second interlayer insulating film 19 (not shown), the second wiring 20 and the MTJ element 18.
[0124]
Next, as shown in FIG. 32, the magnetic shield layer 21 is formed so as to cover the magnetic shield layer 51 and the sidewall insulating film 61. Next, a third interlayer insulating film 22 is deposited on the magnetic shield layer 21. Thereby, the memory cell array portion of the MRAM is completed.
[0125]
According to the eighth embodiment, the same effect as that of the first embodiment can be obtained.
[0126]
Further, in the eighth embodiment, the side surfaces of the second wiring 20 and the MTJ element 18 are covered with the sidewall insulating layer 61. Therefore, even when the magnetic shield layer 21 is continuously formed across the adjacent second wirings 20, the material of the magnetic shield layer 21 is not limited to an insulating material, These materials can also be used. For this reason, the selectivity of the material of the magnetic shield layer 21 can be improved.
[0127]
The eighth embodiment is applied to the structure of the first embodiment, but is not limited to this. For example, as shown in FIGS. 34A and 34B, the present invention can be applied to a magnetic memory device including a diode 32 as a switching element as in the second embodiment. As shown in 35 (a) and 35 (b), the present invention can be applied to a magnetic memory device including a MOSFET 44 as a switching element as in the third embodiment.
[0128]
Further, in FIGS. 30, 34 (a), 34 (b), 35 (a), and 35 (b), the magnetic shield layer 21 is continuously formed across the adjacent second wiring 20. However, it is not limited to this. For example, as shown in FIGS. 36, 37 (a), 37 (b), 38 (a), and 38 (b), the magnetic shield layer 21 between the adjacent second wirings 20 and on the magnetic shield layer 51. And the magnetic shield layer 21 may be divided for each second wiring 20. In this case, the magnetic shield layers 21 and 51 can be made of either an insulating material or a conductive material.
[0129]
[Ninth Embodiment]
The ninth embodiment is a modification of the first embodiment, in which the side surface of the MTJ element is covered with an insulating layer, and the magnetic shield layer is formed across the adjacent second wiring.
[0130]
FIG. 39 is a sectional view of a magnetic memory device according to the ninth embodiment of the present invention. The structure of the magnetic memory device according to the ninth embodiment will be described below. Only the structure different from the first embodiment will be described.
[0131]
As shown in FIG. 39, in the magnetic memory device according to the ninth embodiment, the width of the second wiring 20 is larger than the width of the MTJ element 18 and is recessed from the side surface of the second wiring 20. A sidewall insulating layer 19 a is formed on the side surface of the MTJ element 19. A magnetic shield layer 21 is formed so as to cover the side wall insulating layer 19a and the second wiring 20, and the magnetic shield layer 21 is continuously formed across the adjacent second wirings 20.
[0132]
In the ninth embodiment, when the magnetic shield layer 21 made of a conductive material is formed across the adjacent second wiring 20, the MTJ element 18 adjacent in the extending direction of the first wiring 13 is Although electrically isolated by the sidewall insulating film 19a, the adjacent second wiring 20 is not electrically isolated. For this reason, in the ninth embodiment, it is desirable to use an insulating material for the magnetic shield layer 21.
[0133]
FIG. 40 is a cross-sectional view showing the manufacturing process of the magnetic memory device according to the ninth embodiment of the present invention. The method for manufacturing the magnetic memory device according to the ninth embodiment will be described below. Note that description of steps similar to those of the first embodiment is omitted.
[0134]
First, as shown in FIGS. 2 (a), 2 (b), 2 (c) to 6 (a), 6 (b), 6 (c), island-shaped MTJ elements 18 separated for each cell. Is formed. Next, a second interlayer insulating film 19 is formed on the MTJ element 18 and the first wiring 13, and the CMP or etch-back method is used until the second interlayer insulating film 19 exposes the surface of the MTJ element 18. And flattened.
[0135]
Next, as shown in FIG. 40, the second wiring 20 is formed on the MTJ element 18 and the second interlayer insulating film 19 so as to be orthogonal to the extending direction of the first wiring 13. Here, the second wiring 20 is formed such that the width of the second wiring 20 is larger than the width of the MTJ element 18.
[0136]
Next, as shown in FIG. 39, using the second wiring 20 as a mask, the second interlayer insulating film 19 exposed between the second wirings 20 is replaced with the first interlayer insulating film 12 and the second interlayer insulating film 12. One wiring 13 is removed until exposure. As a result, a sidewall insulating layer 19 a made of the second interlayer insulating film 19 is formed on the side surface of the MTJ element 18. Next, the magnetic shield layer 21 is formed on the second wiring 20, the first interlayer insulating film 12, and the first wiring 13. Next, a third interlayer insulating film 22 is deposited on the magnetic shield layer 21. Thereby, the memory cell array portion of the MRAM is completed.
[0137]
According to the ninth embodiment, the same effect as that of the first embodiment can be obtained.
[0138]
In addition, although 9th Embodiment was applied to the structure of 1st Embodiment, it is not limited to this. For example, as shown in FIGS. 41 (a) and 41 (b), the present invention can be applied to a magnetic memory device including a diode 32 as a switching element as in the second embodiment. As shown in 42 (a) and 42 (b), the present invention can also be applied to a magnetic memory device including a MOSFET 44 as a switching element as in the third embodiment.
[0139]
In FIGS. 39, 41 (a), 41 (b), 42 (a), and 42 (b), the magnetic shield layer 21 is continuously formed across the adjacent second wiring 20. However, it is not limited to this. For example, as shown in FIGS. 43, 44 (a), 44 (b), 45 (a), and 45 (b), the magnetic shield layer 21 between the adjacent second wirings 20 and on the magnetic shield layer 51. And the magnetic shield layer 21 may be divided for each second wiring 20. In this case, the magnetic shield layer 21 can be made of either an insulating material or a conductive material.
[0140]
43, 44 (a), 44 (b), 45 (a), and 45 (b), the magnetic shield layer 21 is not left on the second wiring 20, but the present invention is not limited to this. For example, the magnetic shield layer 51 may be formed on the second wiring 20 as shown in FIGS. 46, 47 (a), 47 (b), 48 (a), and 48 (b). In this case, the magnetic shield layers 21 and 51 can be made of either an insulating material or a conductive material. According to these structures, it is possible to further enhance the effect of suppressing erroneous writing and concentrating the magnetic field on the selected cell.
[0141]
[Tenth embodiment]
The tenth embodiment has the same structure as the first embodiment, but the MTJ element patterning method is different.
[0142]
49 to 52 are perspective views showing the manufacturing process of the magnetic memory device according to the tenth embodiment of the present invention. The method for manufacturing the magnetic memory device according to the tenth embodiment will be described below. In addition, the process similar to 1st Embodiment is demonstrated easily.
[0143]
First, as shown in FIG. 49, the first interlayer insulating film 12 and the first wiring 13 are formed on the semiconductor substrate 11 as in the first embodiment. Next, a TMR material layer 17 including a magnetization fixed layer 14, a tunnel junction layer 15, and a magnetic recording layer 16 is formed on the first interlayer insulating film 12 and the first wiring 13. Next, the TMR material layer 17 is selectively etched using a mask material (not shown) to form a linear TMR material layer 17 extending in the extending direction of the first wiring 13. Next, a second interlayer insulating film 19 is formed on the TMR material layer 17 and the first interlayer insulating film 12, and the second interlayer insulating film 19 is subjected to CMP or etching until the surface of the TMR material layer 17 is exposed. It is planarized using the back method.
[0144]
Next, as shown in FIG. 50, the second wiring 20 is formed on the TMR material layer 17 and the second interlayer insulating film 19 so as to be orthogonal to the extending direction of the first wiring 13.
[0145]
Next, as shown in FIG. 51, the second interlayer insulating film 19 and the TMR material layer 17 exposed between the second wirings 20 are formed using the second wiring 20 as a mask. The insulating film 12 and the first wiring 13 are removed until exposure. As a result, island-shaped MTJ elements 18 separated for each cell are formed.
[0146]
Next, as shown in FIG. 52, the magnetic shield layer 21 is formed on the second wiring 20, the first interlayer insulating film 12, and the first wiring 13.
[0147]
Thereafter, as in the first embodiment, a third interlayer insulating film 22 is deposited on the magnetic shield layer 21 as shown in FIGS. 1 (a), 1 (b), and 1 (c). Thereby, the memory cell array portion of the MRAM is completed.
[0148]
According to the tenth embodiment, the same effect as that of the first embodiment can be obtained.
[0149]
Furthermore, in the tenth embodiment, the patterning of the MTJ element 18 is performed by first processing in a straight line and then processing in a self-aligning manner with the second wiring 20. For this reason, it is possible to form, for example, a rectangular MTJ element 18 that cannot be realized by only lithography technology. Therefore, for example, by reducing the magnetization reversal threshold, the amount of current required for writing can be reduced. Furthermore, since the variation in the shape of each MTJ element 18 can be suppressed, the variation in the threshold value of the write current for each MTJ element 18 can be suppressed. As a result, it is possible to reduce the power consumption of the entire memory cell and form a memory that is unlikely to cause a write error.
[0150]
The manufacturing method according to the tenth embodiment has been described as applied to the first embodiment. However, if the second wiring and the MTJ element have the same width, the second to eighth described above can be used. It is also possible to apply to this embodiment.
[0151]
[Eleventh embodiment]
The eleventh embodiment is a modification of the first to third embodiments, and is an example in which not only the second wiring but also the first wiring is covered with a magnetic shield layer.
[0152]
53 (a), 53 (b), 54 (a), 54 (b), 55 (a), and 55 (b) are sectional views of the magnetic memory device according to the eleventh embodiment of the present invention. . Here, FIGS. 53 (a) and 53 (b) show a modification of the first embodiment in which no switching element is provided, and FIGS. 54 (a) and 54 (b) show a diode 32 as a switching element. 55 (a) and 55 (b) show a modification of the third embodiment in which the transistor 44 is provided as a switching element. The structure of the magnetic memory device according to the eleventh embodiment will be described below. Only the structure different from the first embodiment will be described.
[0153]
As shown in FIGS. 53 (a), 53 (b), 54 (a), 54 (b), 55 (a), and 55 (b), the magnetic storage device according to the eleventh embodiment is the first Magnetic shield layers 62 are also formed on the bottom and side surfaces of the wiring 13. Since the magnetic shield layer 62 is divided for each cell, the magnetic shield layer 62 may be formed of an insulating material or a conductive material.
[0154]
When the first wiring 13 has a damascene structure, the magnetic shield layer 62 is formed by the following method, for example. First, a first wiring trench is formed in the insulating film 12. A magnetic shield layer 62 is formed in the groove, and a first wiring material layer is formed on the magnetic shield layer 62. Thereafter, the magnetic shield layer 62 and the material layer are planarized by CMP or etch back until the surface of the insulating film 12 is exposed. As a result, a structure in which the magnetic shield layer 62 is formed on the bottom and side surfaces of the first wiring 13 can be formed.
[0155]
According to the eleventh embodiment, the same effect as in the first embodiment can be obtained.
[0156]
Furthermore, in the eleventh embodiment, the bottom surface and the side surface of the first wiring 13 are covered with the magnetic shield layer 62. For this reason, the magnetic shield layer 62 sufficiently exhibits the effect as a yoke, and the current magnetic field produced by the first wiring 13 can be efficiently applied to the selected cell. Therefore, since the write current flowing through the first wiring 13 can be reduced, the power consumption can be further reduced.
[0157]
Further, by covering the first wiring 13 with the magnetic shield layer 62, the leakage magnetic field to the adjacent MTJ element 18 arranged in the extending direction of the second wiring 20 can be more efficiently blocked. Accordingly, erroneous writing can be suppressed.
[0158]
Further, the magnetic shield layer 62 is separated for each adjacent first wiring 13. Therefore, the material of the magnetic shield layer 62 is not limited to an insulating material, and a conductive material can also be used, so that the selectivity of the material of the magnetic shield layer 62 can be improved.
[0159]
[Twelfth embodiment]
The twelfth embodiment is a modification of the eleventh embodiment and has a structure in which a magnetic shield layer is sandwiched between barrier metals.
[0160]
56 (a), 56 (b), 57 (a), 57 (b), 58 (a), and 58 (b) are sectional views of the magnetic memory device according to the twelfth embodiment of the present invention. . 56 (a) and 56 (b) show a modification of the first embodiment in which no switching element is provided, and FIGS. 57 (a) and 57 (b) show a diode 32 as a switching element. 58 (a) and 58 (b) show a modification of the third embodiment in which a transistor 44 is provided as a switching element. The structure of the magnetic memory device according to the twelfth embodiment will be described below. Only the structure different from the eleventh embodiment will be described.
[0161]
As shown in FIGS. 56 (a), 56 (b), 57 (a), 57 (b), 58 (a), 58 (b), the magnetic storage device according to the twelfth embodiment The magnetic shield layer 21 formed on the top and side surfaces of the wiring 20 is sandwiched between barrier metal layers 63 and 64, and the magnetic shield layer 62 formed on the bottom and side surfaces of the first wiring 13 is sandwiched between barrier metal layers 65 and 66. It is out.
[0162]
For the barrier metal layers 63 and 65 formed inside the magnetic shield layers 21 and 62, for example, a material such as Co or CoFe is used. On the other hand, the barrier metal layers 64 and 66 formed outside the magnetic shield layers 21 and 62 are made of materials such as Ta, TaN, and TaSiN, for example.
[0163]
When the first wiring 13 has a damascene structure, the magnetic shield layer 62 and the barrier metal layers 65 and 66 are formed by the following method, for example. First, a first wiring trench is formed in the insulating film 12. A barrier metal layer 66, a magnetic shield layer 62, and a barrier metal layer 65 are formed in this groove in this order, and a first wiring material layer is formed on the magnetic shield layer 62. Thereafter, the barrier metal layers 65 and 66, the magnetic shield layer 62, and the material layer are planarized by CMP or etch back until the surface of the insulating film 12 is exposed. As a result, the magnetic shield layer 62 sandwiched between the barrier metal layers 65 and 66 is formed on the bottom and side surfaces of the first wiring 13.
[0164]
According to the twelfth embodiment, the same effect as in the eleventh embodiment can be obtained.
[0165]
Furthermore, in the twelfth embodiment, by providing the barrier metal layers 63, 64, 65, 66 on the inner side and the outer side of the magnetic shield layers 21, 62, the following effects can be obtained, respectively.
[0166]
By providing the barrier metal layer 63 between the second wiring 20 and the magnetic shield layer 21, it is possible to suppress the reaction between the magnetic shield layer 21 and the second wiring 20, and the performance of the magnetic shield (yoke performance). In addition, an increase in wiring resistance in the second wiring 20 can be suppressed.
[0167]
By providing the barrier metal layer 64 between the magnetic shield layer 21 and the interlayer insulating film 22, it is possible to improve the adhesion between the magnetic shield layer 21 and the interlayer insulating film 22 which is the upper layer film. It is possible to prevent the shield material 21 from diffusing into the interlayer insulating film 22.
[0168]
By providing the barrier metal layer 65 between the first wiring 13 and the magnetic shield layer 62, the reaction between the magnetic shield layer 62 and the first wiring 13 can be suppressed, and the yoke performance can be improved. In addition, an increase in wiring resistance in the first wiring 13 can also be suppressed.
[0169]
By providing the barrier metal layer 66 between the magnetic shield layer 62 and the interlayer insulating film 12, the adhesion between the magnetic shield layer 62 and the underlying interlayer insulating film 12 can be improved, and the magnetic shield layer 62 is further improved. Can be prevented from diffusing into the interlayer insulating film 12.
[0170]
[Thirteenth embodiment]
The thirteenth embodiment is a modification of the magnetic memory device that does not use a switching element.
[0171]
59 and 60 are perspective views of a magnetic memory device according to the thirteenth embodiment of the present invention. The structure of the magnetic memory device according to the thirteenth embodiment will be described below. The description will focus on the parts different from the structure of FIGS. 53 (a) and 53 (b).
[0172]
In the structure shown in FIG. 59, the first wiring 13 is divided into a write word line 13a and a read word line 13b. The write word line 13a extends, for example, so as to be orthogonal to the second wiring (bit line) 20, and is disposed apart from the MTJ element 18. On the other hand, the read word line 13 b extends in parallel on the same plane as the write word line 13 a and is connected to the MTJ element 18 through the lower metal layer 67 and the contact 68. Magnetic shield layers 62a and 62b are formed on the side and bottom surfaces of the write and read word lines 13a and 13b, respectively.
[0173]
In the structure shown in FIG. 60, the first wiring 13 is divided into a write word line 13a and a read word line 13b. The write word line 13a extends, for example, so as to be orthogonal to the second wiring (bit line) 20, and is disposed apart from the MTJ element 18. Magnetic shield layers 62a are formed on the side and bottom surfaces of the write word line 13a. On the other hand, the read word line 13b extends in parallel with the write word line 13a, is disposed between the MTJ element 18 and the write word line 13a, and is in contact with the MTJ element 18.
[0174]
According to the thirteenth embodiment, the same effect as in the eleventh embodiment can be obtained.
[0175]
Furthermore, in the thirteenth embodiment, the first wiring 13 is divided into a write word line 13a and a read word line 13b. For this reason, compared with the simple cross-point structure as shown in FIGS. 53A and 53B, a larger readout signal can be obtained and the readout speed can be improved.
[0176]
Further, by partially separating the write line and the read line, voltage bias applied to the tunnel junction layer 15 at the time of writing can be eliminated, and reliability can be improved.
[0177]
In the thirteenth embodiment, since there is no switch element, the cell size can be reduced, and the development for multilayering is facilitated.
[0178]
In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention when it is practiced. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.
[0179]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a magnetic storage device capable of suppressing erroneous writing and concentrating a magnetic field on a selected cell, and a manufacturing method thereof.
[Brief description of the drawings]
FIG. 1A is a perspective view showing a semiconductor memory device according to a first embodiment of the present invention, and FIG. 1B is a semiconductor memory device taken along line IB-IB in FIG. FIG. 1C is a cross-sectional view of the semiconductor memory device taken along line IC-IC in FIG.
2A and 2B are cross-sectional views showing a TMR element having a single tunnel junction structure according to each embodiment of the present invention.
FIGS. 3A and 3B are sectional views showing a TMR element having a double tunnel junction structure according to each embodiment of the present invention.
4A is a perspective view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, and FIG. 4B is along the line IVB-IVB in FIG. 4A; 4 is a cross-sectional view of the semiconductor memory device, and FIG. 4C is a cross-sectional view of the semiconductor memory device taken along line IVC-IVC in FIG.
5A is a perspective view showing a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 4A, and FIG. 5B is a perspective view of FIG. 5C is a cross-sectional view of the semiconductor memory device taken along line VB-VB, and FIG. 5C is a cross-sectional view of the semiconductor memory device taken along line VC-VC in FIG.
6 (a) is a perspective view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 5 (a), and FIG. 6 (b) is FIG. 6 (a). 6A is a cross-sectional view of the semiconductor memory device taken along line VIB-VIB, and FIG. 6C is a cross-sectional view of the semiconductor memory device taken along line VIC-VIC of FIG.
FIG. 7A is a perspective view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention following FIG. 6A, and FIG. 7B is FIG. 7C is a cross-sectional view of the semiconductor memory device taken along line VIIB-VIIB, and FIG. 7C is a cross-sectional view of the semiconductor memory device taken along line VIIC-VIIC in FIG.
FIG. 8A is a perspective view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention following FIG. 7A, and FIG. 8B is FIG. FIG. 8C is a cross-sectional view of the semiconductor memory device taken along line VIIIC-VIIIC of FIG. 8A.
FIG. 9A is a perspective view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention following FIG. 8A, and FIG. 9B is FIG. 9C is a cross-sectional view of the semiconductor memory device taken along line IXB-IXB, and FIG. 9C is a cross-sectional view of the semiconductor memory device taken along line IXC-IXC of FIG.
FIG. 10A is a cross-sectional view in the extending direction of the first wiring showing the semiconductor memory device according to the second embodiment of the present invention, and FIG. 10B is the second embodiment of the present invention. Sectional drawing in the extension direction of the 2nd wiring which shows the semiconductor memory device concerning a form.
FIG. 11A is a cross-sectional view in the extending direction of the first wiring showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, and FIG. Sectional drawing in the extension direction of the 2nd wiring which shows the manufacturing process of the semiconductor memory device concerning 2 embodiment.
12A is a cross-sectional view in the extending direction of the first wiring, showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 12B is a cross-sectional view in the extending direction of the second wiring showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG.
13A is a cross-sectional view in the extending direction of the first wiring showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 12A; FIG. FIG. 13B is a cross-sectional view in the extending direction of the second wiring showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG.
14A is a cross-sectional view in the extending direction of the first wiring, showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 13A; FIG. 14B is a cross-sectional view in the extending direction of the second wiring showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG.
15A is a cross-sectional view in the extending direction of the first wiring, showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 14A; FIG. 15B is a cross-sectional view in the extending direction of the second wiring showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention, following FIG.
FIG. 16A is a cross-sectional view in the extending direction of the first wiring showing the semiconductor memory device according to the third embodiment of the present invention, and FIG. 16B is the third embodiment of the present invention. Sectional drawing in the extension direction of the 2nd wiring which shows the semiconductor memory device concerning a form.
FIG. 17A is a cross-sectional view in the extending direction of the first wiring showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, and FIG. Sectional drawing in the extending direction of the 2nd wiring which shows the manufacturing process of the semiconductor memory device concerning 3 embodiment.
18A is a cross-sectional view in the extending direction of the first wiring, showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 17A; FIG. FIG. 18B is a cross-sectional view in the extending direction of the second wiring showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG.
FIG. 19A is a cross-sectional view in the extending direction of the first wiring showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 18A; FIG. 19B is a cross-sectional view in the extending direction of the second wiring showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG.
20A is a cross-sectional view in the extending direction of the first wiring, showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 19A; FIG. FIG. 20B is a cross-sectional view in the extending direction of the second wiring, showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG.
FIG. 21A is a cross-sectional view in the extending direction of the first wiring, showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG. FIG. 21B is a cross-sectional view in the extending direction of the second wiring showing the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention, following FIG.
FIG. 22A is a perspective view showing a semiconductor memory device according to the fourth embodiment of the present invention, and FIG. 22B is a semiconductor memory device taken along line XXIIB-XXIIB in FIG. FIG. 22C is a cross-sectional view of the semiconductor memory device taken along line XXIIC-XXIIC in FIG.
FIG. 23A is a perspective view showing the manufacturing process of the semiconductor memory device according to the fourth embodiment of the present invention, and FIG. 23B is along the line XXIIIB-XXIIIB of FIG. FIG. 23C is a cross-sectional view of the semiconductor memory device, and FIG. 23C is a cross-sectional view of the semiconductor memory device taken along line XXIIIC-XXIIIC in FIG.
24A is a cross-sectional view in the extending direction of the first wiring showing the semiconductor memory device according to the fifth embodiment of the present invention, and FIG. 24B is the fifth embodiment of the present invention. Sectional drawing in the extension direction of the 2nd wiring which shows the semiconductor memory device concerning a form.
FIG. 25A is a cross-sectional view in the extending direction of the first wiring showing the manufacturing process of the semiconductor memory device according to the fifth embodiment of the present invention, and FIG. Sectional drawing in the extension direction of the 2nd wiring which shows the manufacturing process of the semiconductor memory device concerning 5 embodiment.
FIG. 26A is a cross-sectional view in the extending direction of the first wiring showing the semiconductor memory device according to the sixth embodiment of the present invention, and FIG. 26B is the sixth embodiment of the present invention. Sectional drawing in the extension direction of the 2nd wiring which shows the semiconductor memory device concerning a form.
FIG. 27A is a cross-sectional view in the extending direction of the first wiring showing the manufacturing process of the semiconductor memory device according to the sixth embodiment of the present invention, and FIG. Sectional drawing in the extending direction of the 2nd wiring which shows the manufacturing process of the semiconductor memory device concerning 6th Embodiment.
FIG. 28 is a sectional view showing a semiconductor memory device according to a seventh embodiment of the present invention.
FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the seventh embodiment of the present invention.
FIGS. 30A and 30B are cross-sectional views showing a semiconductor memory device having a diode as a switching element according to a seventh embodiment of the present invention, and FIG. 30A shows a second wiring; FIG. 30B is a cross-sectional view perpendicular to the extending direction, and FIG. 30B is a cross-sectional view perpendicular to the extending direction of the first wiring.
FIGS. 31A and 31B are cross-sectional views showing a semiconductor memory device having a MOSFET as a switching element according to a seventh embodiment of the present invention, and FIG. 31A shows the second wiring; FIG. 31B is a cross-sectional view perpendicular to the extending direction, and FIG. 31B is a cross-sectional view perpendicular to the extending direction of the first wiring.
FIG. 32 is a sectional view showing a semiconductor memory device according to an eighth embodiment of the present invention.
FIG. 33 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the eighth embodiment of the present invention.
34A and 34B are cross-sectional views showing a semiconductor memory device having a diode as a switching element according to an eighth embodiment of the present invention, and FIG. 34A shows the second wiring. 34 is a cross-sectional view perpendicular to the extending direction, and FIG. 34B is a cross-sectional view perpendicular to the extending direction of the first wiring.
35 (a) and 35 (b) are cross-sectional views showing a semiconductor memory device having a MOSFET as a switching element according to an eighth embodiment of the present invention, and FIG. 35 (a) shows the second wiring. FIG. 35B is a cross-sectional view perpendicular to the extending direction, and FIG. 35B is a cross-sectional view perpendicular to the extending direction of the first wiring.
FIG. 36 is a sectional view showing another semiconductor memory device according to the eighth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring;
FIGS. 37A and 37B show another semiconductor memory device having a diode as a switching element according to the eighth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring; 37A is a sectional view perpendicular to the extending direction of the second wiring, and FIG. 37B is a sectional view perpendicular to the extending direction of the first wiring. .
FIGS. 38A and 38B show another semiconductor memory device having a MOSFET as a switching element according to an eighth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring. 38A is a sectional view perpendicular to the extending direction of the second wiring, and FIG. 38B is a sectional view perpendicular to the extending direction of the first wiring. .
FIG. 39 is a cross-sectional view showing a semiconductor memory device according to a ninth embodiment of the present invention.
FIG. 40 is a cross-sectional view showing a manufacturing process of a semiconductor memory device according to the ninth embodiment of the invention.
41 (a) and 41 (b) are cross-sectional views showing a semiconductor memory device having a diode as a switching element according to a ninth embodiment of the present invention, and FIG. 41 (a) shows the second wiring. FIG. 41B is a cross-sectional view perpendicular to the extending direction, and FIG. 41B is a cross-sectional view perpendicular to the extending direction of the first wiring.
42A and 42B are cross-sectional views showing a semiconductor memory device having a MOSFET as a switching element according to a ninth embodiment of the present invention, and FIG. FIG. 42B is a cross-sectional view perpendicular to the extending direction, and FIG. 42B is a cross-sectional view perpendicular to the extending direction of the first wiring.
FIG. 43 is a sectional view showing another semiconductor memory device according to the ninth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring;
44 (a) and 44 (b) show another semiconductor memory device having a diode as a switching element according to the ninth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring; 44A is a sectional view perpendicular to the extending direction of the second wiring, and FIG. 44B is a sectional view perpendicular to the extending direction of the first wiring. .
45A and 45B show another semiconductor memory device having a MOSFET as a switching element according to the ninth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring. 45A is a sectional view perpendicular to the extending direction of the second wiring, and FIG. 45B is a sectional view perpendicular to the extending direction of the first wiring. .
FIG. 46 is a sectional view showing another semiconductor memory device according to the ninth embodiment of the present invention, in which a magnetic shield layer is divided for each second wiring and formed on the second wiring;
47 (a) and 47 (b) show another semiconductor memory device having a diode as a switching element according to the ninth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring; FIG. 47A is a sectional view perpendicular to the extending direction of the second wiring, and FIG. 47B is a sectional view of the first wiring formed on the second wiring. Sectional drawing perpendicular | vertical with respect to the extending direction.
48A and 48B show another semiconductor memory device having a MOSFET as a switching element according to the ninth embodiment of the present invention, in which the magnetic shield layer is divided for each second wiring; FIG. 48A is a cross-sectional view perpendicular to the extending direction of the second wiring, and FIG. 48B is a cross-sectional view formed on the second wiring. Sectional drawing perpendicular | vertical with respect to the extension direction.
FIG. 49 is a perspective view showing the manufacturing process of the semiconductor memory device according to the tenth embodiment of the present invention.
FIG. 50 is a perspective view illustrating the manufacturing process of the semiconductor memory device according to the tenth embodiment of the present invention, following FIG. 49;
FIG. 51 is a perspective view illustrating the manufacturing process of the semiconductor memory device according to the tenth embodiment of the present invention, following FIG. 50;
FIG. 52 is a perspective view illustrating the manufacturing process of the semiconductor memory device according to the tenth embodiment of the present invention, following FIG. 51;
53A and 53B are cross-sectional views showing a magnetic memory device not provided with a switching element according to an eleventh embodiment of the present invention.
54A and 54B are cross-sectional views showing a magnetic memory device having a diode as a switching element according to an eleventh embodiment of the present invention.
FIGS. 55A and 55B are cross-sectional views showing a magnetic memory device having a MOSFET as a switching element according to an eleventh embodiment of the present invention.
56 (a) and 56 (b) are cross-sectional views showing a magnetic memory device without a switching element according to the twelfth embodiment of the present invention.
FIGS. 57A and 57B are cross-sectional views showing a magnetic memory device having a diode as a switching element according to a twelfth embodiment of the present invention.
FIGS. 58A and 58B are cross-sectional views showing a magnetic memory device having a MOSFET as a switching element according to a twelfth embodiment of the present invention.
FIG. 59 is a perspective view showing a magnetic memory device according to the thirteenth embodiment of the present invention.
FIG. 60 is a perspective view showing another magnetic memory device according to the thirteenth embodiment of the present invention.
FIG. 61 is a cross-sectional view showing a conventional semiconductor memory device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 12 ... 1st interlayer insulation film, 13 ... 1st wiring, 13a ... Write word line, 13b ... Read word line, 14, 14a, 14b ... Magnetization fixed layer, 15, 15a, 15b ... Tunnel Junction layer, 16 ... magnetic recording layer, 17 ... TMR material layer, 18 ... TMR element, 19 ... second interlayer insulating film, 19a, 61 ... side wall insulating layer, 20 ... second wiring, 21, 21a, 51, 62, 62a, 62b ... magnetic shield layer, 22 ... third interlayer insulating film, 31 ... diode material layer, 32 ... diode, 41 ... gate insulating film, 42 ... gate electrode, 43 ... source / drain diffusion layer, 44 ... MOSFET, 45, 68 ... contact, 46 ... fourth interlayer insulating film, 47 ... lower electrode material layer, 48 ... lower electrode, 63, 64, 65, 66 ... barrier metal layer, 67 ... lower metal layer, 1 DESCRIPTION OF SYMBOLS 1 ... Template layer, 102 ... Initial ferromagnetic layer, 103 ... Antiferromagnetic layer, 104, 104 ', 104 "... Reference ferromagnetic layer, 105, 105', 105" ... Free recording layer, 106 ... Contact layer, 107 ... nonmagnetic layer.

Claims (9)

A first wiring extending in a first direction;
A storage element disposed above the first wiring;
A second wiring disposed on the memory element and extending in a second direction different from the first direction;
A first magnetic shield layer formed on a side surface of the second wiring and a side surface of the memory element ;
A third wiring disposed on the same plane as the first wiring, extending in parallel with the first wiring, connected to the memory element, and used as a read wiring; Magnetic storage device. Forming a first wiring extending in a first direction;
  Selectively forming a memory element above the first wiring;
  Forming a first insulating layer around the memory element;
  Forming a second wiring extending in a second direction different from the first direction on the first insulating layer and the memory element;
  Removing the first insulating layer not covered with the second wiring by using the second wiring as a mask;
  Forming a first magnetic shield layer across the second wiring so as to cover the first and second wirings and the memory element;
  A method of manufacturing a magnetic storage device, comprising: After forming the first magnetic shield layer,
  The first magnetic shield layer between the upper surface of the second wiring and the second wiring is removed, and the first magnetic shield layer is used as the side surface of the second wiring and the side surface of the storage element. The method of manufacturing a magnetic memory device according to claim 2, further comprising: 4. The method of manufacturing a magnetic memory device according to claim 3, wherein the first magnetic shield layer is removed by anisotropic etching. Before forming the first magnetic shield layer, forming a second magnetic shield layer on the upper surface of the second wiring;
  After forming the first magnetic shield layer, the selected portion of the first magnetic shield layer is removed, and the first magnetic shield layer is placed on the side surface of the second wiring and the side surface of the storage element. With the process to leave
  The method of manufacturing a magnetic memory device according to claim 2, further comprising: Before forming the first magnetic shield layer,
  Forming a second magnetic shield layer on the upper surface of the second wiring;
  Forming a second insulating layer on the side surface of the second wiring and the side surface of the memory element;
  The method of manufacturing a magnetic memory device according to claim 2, further comprising: After forming the first magnetic shield layer,
  Removing the first magnetic shield layer between the upper surface of the second magnetic shield layer and the second wiring and leaving the first magnetic shield layer on the side surface of the second insulating layer;
  The method of manufacturing a magnetic memory device according to claim 6, further comprising: Forming the second wiring by making the width of the second wiring larger than the width of the memory element in the first direction;
  The side surface of the memory element that is recessed from the side surface of the second wiring by removing the first insulating layer that is not covered with the second wiring by using the second wiring as a mask. Leaving the first insulating layer,
  The first magnetic shield layer is formed on the side surface and the top surface of the second wiring and the side surface of the first insulating layer.
  The method of manufacturing a magnetic memory device according to claim 2. Forming a first wiring extending in a first direction;
  Forming a linear memory element extending in the first direction above the first wiring; and ,
  Forming a first insulating layer around the memory element;
  Forming a second wiring extending in a second direction different from the first direction on the first insulating layer and the memory element;
  Removing the first insulating layer and the memory element that are not covered with the second wiring using the second wiring as a mask, and making the memory element into an island shape;
  Forming a first magnetic shield layer across the second wiring;
  A method of manufacturing a magnetic storage device, comprising:

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