US7912884B2 - Method and apparatus for implementing finite impulse response filters without the use of multipliers - Google Patents

Method and apparatus for implementing finite impulse response filters without the use of multipliers Download PDF

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US7912884B2
US7912884B2 US11/633,875 US63387506A US7912884B2 US 7912884 B2 US7912884 B2 US 7912884B2 US 63387506 A US63387506 A US 63387506A US 7912884 B2 US7912884 B2 US 7912884B2
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response
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filter
impulse
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US20080133625A1 (en
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Radu Alexandru
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Fujifilm Healthcare Corp
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Aloka Co Ltd
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Priority to US11/633,875 priority Critical patent/US7912884B2/en
Priority to CN200780044500.3A priority patent/CN101617235B/zh
Priority to EP07865153A priority patent/EP2097759A4/en
Priority to PCT/US2007/086346 priority patent/WO2008070644A2/en
Priority to JP2009540417A priority patent/JP5108022B2/ja
Publication of US20080133625A1 publication Critical patent/US20080133625A1/en
Priority to US13/032,924 priority patent/US8452828B1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0248—Filters characterised by a particular frequency response or filtering method
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0227—Measures concerning the coefficients
    • H03H17/023—Measures concerning the coefficients reducing the wordlength, the possible values of coefficients
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters

Definitions

  • the invention relates generally to the field of digital signal processing. More specifically, embodiments of the invention relate to methods and systems for implementing finite impulse response filters without using multipliers.
  • Filtering is one of the most often used operations in digital signal processing.
  • One method of filtering is by means of a finite impulse response (FIR) filter.
  • FIR finite impulse response
  • an input signal is convolved with an impulse response of finite duration that determines the frequency response output characteristics. Since an FIR is typically used in a sampled data system, the signal and the impulse response are quantized in time and amplitude yielding discrete samples. The discrete samples comprising the desired impulse response are the FIR filter coefficients.
  • the FIR filter calculation for each output sample is a two step process. A number of input signal samples are multiplied by a corresponding number of coefficient values (the values for each pair are multiplied together). Afterwards, all of the products are added together. The number and values of coefficients correspond with a desired frequency response. The longer the impulse response, the more filter coefficients and therefore the more multiplications are needed.
  • FIR filters One disadvantage of FIR filters is the computational complexity required for each output sample. For example, for each output sample, N multiply-accumulate (MAC) operations need be performed. A 100 coefficient filter requires 100 multiplications and 100 additions for each output sample.
  • MAC multiply-accumulate
  • DSP Digital signal processing
  • multiplier remains relatively expensive when compared to other arithmetic operations such as adders.
  • the expense is directly related to logic gate count.
  • Binary adders are less costly than binary multipliers, however their use should be minimized as well. If the goal of a filter designer is to minimize cost and to conserve IC resources when implementing multichannel designs, it is desirable to find filtering architectures and methods which minimize, or obviate multipliers.
  • a desired impulse response is decomposed into a sum of rectangular impulse responses of equal height, each of which implemented as a running sum requiring a subtraction and an addition.
  • multiple running sums may be implemented on the same hardware.
  • a whole filter of arbitrary impulse response shapes and lengths may be implemented using memory and two arithmetic units. Two or more such filters may be cascaded to obtain a better approximation of the desired frequency characteristic.
  • One aspect of the invention provides methods for filtering a signal using a desired impulse response.
  • Methods according to this aspect of the invention preferably start with decomposing the desired impulse response into a plurality of individual rectangular component impulse responses, inputting the signal to each one of the plurality of rectangular component impulse responses, convolving each one of the plurality of rectangular component impulse responses with the input signal, and summing the plurality of convolutions, wherein the sum is the response of the desired impulse response to the input signal.
  • convolving includes using a running sum.
  • decomposing includes calculating a frequency response for the desired impulse response, specifying a quantity of component rectangular impulse responses, decomposing the desired impulse response into a candidate response, the candidate response comprises the quantity of component rectangular impulse responses such that each component rectangular impulse response has either a positive or negative amplitude and when summed together approximate the desired impulse response, refining the candidate impulse response iteratively comprising a) calculating a frequency response for the candidate response, and b) comparing the candidate frequency response with the desired frequency response, wherein if the candidate frequency response is within the predefined range, use the candidate response, and if the candidate frequency response is not within a predefined range, adjust one or more of the candidate response component rectangular impulse response lengths, repeating steps a) and b).
  • Digital filters comprise a filter input for inputting signal samples, a filter output for outputting a filtered sampled signal, a first delay coupled to the filter input for delaying a number of samples corresponding to a number of samples preceding a rectangular impulse response, a second delay coupled to an output of the first delay for delaying a number of samples corresponding to a number of samples representing the rectangular impulse response, a subtractor coupled to the output of the first delay and an output of the second delay for obtaining the difference between incoming signal samples and signal samples time-shifted by the amount corresponding to the rectangular impulse response, and an accumulator input coupled to an output of the subtractor for keeping a running sum of the difference samples as the filter output.
  • Yet another aspect of the invention is a digital filter that comprises a filter input for inputting signal samples, a filter output for outputting a filtered sampled signal, a buffer coupled to the filter input, the buffer acting as a queue, a register having an input coupled to a first data output of the buffer, a subtractor having a minus input coupled to an output of the register and a plus input coupled to a second data output of the buffer for obtaining differences between a plurality of time-shifted signal samples and a second plurality of time-shifted signal samples output from the buffer, wherein each pair of samples of the first and second plurality of time-shifted samples output from the buffer represents a rectangular impulse response such that the incoming data sample is convolved with each of the plurality of rectangular impulse responses in time, an accumulator input coupled to an output of the subtractor for keeping a running sum of the plurality of differences, and an output coupled to the filter output, and a controller coupled to the buffer and accumulator, the controller configured to rotate through the buffer for addresses where a next incoming signal
  • FIG. 1 shows an exemplary plot of a filter impulse response.
  • FIGS. 2A , 2 B and 2 C show an exemplary decomposition of the filter impulse response shown in FIG. 1 into component impulse responses h 1 , h 2 , h 3 , and h 4 .
  • FIG. 3 is a block diagram of an exemplary impulse response decomposition method.
  • FIG. 4 is an exemplary system block diagram of a filter implemented as a sum of component rectangular filters.
  • FIG. 6 is an exemplary system block diagram of a FIR filter using time-multiplexed multiple rectangular impulse response filters.
  • FIG. 7 is an exemplary alternative embodiment of the filter shown in FIG. 6 including a scaling multiplier.
  • FIG. 8 is an exemplary alternative embodiment of the filter shown in FIG. 6 including a scaling multiplexer.
  • Embodiments of the invention provide methods and systems for implementing a FIR filter structure that does not require multipliers.
  • FIG. 1 shows an exemplary desired filter impulse response, or filter kernel, symmetrical with respect to its center and comprising a positive center lobe and side-lobes of smaller amplitude. Only one pair of negative side-lobes is shown.
  • the impulse response may be approximated by a sum of positive and negative rectangular components, as shown in FIG. 2A given by,
  • Each rectangular component kernel h 1 , h 2 , h 3 , and h 4 is defined by a discrete number of ⁇ non-zero coefficients (or samples). Zero values are added to either side of a rectangular response to equal the duration of the component kernel having the greater number of non-zero coefficients for proper time-alignment.
  • the rectangular filter component h 1 shown in FIG. 2B , comprises 22 non-zero negative ( ⁇ 1) coefficients.
  • the rectangular filter component h 3 shown in FIG. 2A , comprises eight positive coefficients and must have seven zero coefficients placed before its non-zero amplitudes.
  • the rectangular filter component h 4 comprises six positive coefficients and has eight zero coefficients placed before its non-zero amplitudes.
  • the decomposition of a desired filter impulse response or kernel into component rectangular filters is an optimization between implementation expense, operational efficiency, and desired filter frequency response accuracy.
  • the invention performs an impulse decomposition method beginning with a desired filter frequency response as shown in FIG. 3 .
  • the filter frequency response is determined by an impulse response where the quantized impulse response and the filter coefficients are identical.
  • the design consists of determining the impulse response from the desired frequency response and then quantizing the impulse response to generate the filter coefficients.
  • a user specifies stop, passband, and stopband attenuation (dB) (step 305 ), and hardware constraints such as the maximum number of impulse responses (step 310 ) and the maximum kernel length (number of coefficients) of the desired filter (step 315 ).
  • a prototype impulse response may be designed using software specifically designed to calculate a filter impulse response (step 320 ).
  • the impulse response is derived using software to perform a complex optimization process.
  • One widely used program, MATLAB, from The MathWorks may be used.
  • the impulse response may be graphically decomposed into component rectangular impulse responses as in FIG. 2 (step 325 ) resulting in a first candidate decomposition.
  • a decomposition is not unique and the first candidate (step 325 ) may not produce satisfactory results.
  • an iterative process may be used where the frequency response corresponding to the candidate impulse response decomposition is calculated (step 330 ) and compared with the initial frequency response specification (step 335 ).
  • step 340 If the frequency comparison result is not satisfactory (step 340 ), an iteration on the component structure may be performed.
  • the decomposition is modified (step 350 ) by changing the widths of the rectangular component impulse responses by small amounts to produce a new candidate whose frequency response is calculated (step 330 ) and compared with the initial frequency response specification (step 335 ). If the comparison is acceptable (step 340 ), that candidate response is used (step 355 ).
  • Each of the cascaded filters may be designed as described above and may be further tuned by a similar iterative process with the difference that the frequency response of the cascaded FIR filters is now computed (step 330 ) after each iteration and compared to the initial specification.
  • the optimization method usually results in two cascaded filters, each with different positions of the minima and maxima in the stopband of their frequency characteristics such that the stopband minima of one filter compensate the stopband maxima of the other.
  • the compensation aspect allows the cascaded filter to exhibit uniformly good stopband attenuation.
  • the rectangular components may be considered to represent the impulse responses of individual component filters.
  • the component filters and their rectangular impulse responses will be referred to by the symbols h 1 , h 2 , etc.
  • the filter's response to the signal is equal to the sum of the responses of the component filters to the same signal
  • An input signal s[n] input 405 to the system 401 would be processed by each component filter h 1 , h 2 , h 3 , and h 4 , and then summed 403 together.
  • the component filter responses h i may be implemented as the signed sums of signal samples over the non-zero portion of the impulse response thereby obviating multipliers.
  • FIG. 5 Shown in FIG. 5 is an exemplary architecture of a recursive running sum filter configured for one predefined rectangular component response.
  • the filter 501 includes a signal sample s[n] input 503 , a first delay line such as a FIFO (first in, first out) 505 , a second delay line 507 , a first subtractor 509 , an accumulator 511 comprising a second adder/subtractor 513 and a storage register 515 , and a filter sample o[n] output 517 .
  • the filter 501 is a synchronous, pipelined architecture. The same clock (not shown) is used for both reading and writing data samples. To implement FIG. 4 would require four filters as shown in FIG. 5 , each preconfigured with a rectangular component response h 1 , h 2 , h 3 , and h 4 .
  • a rectangular response is defined using the first 505 and second 507 delay lines.
  • the first delay line 505 is preconfigured for the number of leading zero coefficients d i in a response.
  • the second delay line 507 is preconfigured for the number of non-zero coefficients D i in a response.
  • the first delay line 505 provide the delay d i from the start of the impulse response to the first non-zero coefficient. For example, if the architecture shown in FIG. 5 was used to implement FIG. 4 , each delay 505 would account for the leading number of zero coefficients for h 1 , h 2 , h 3 , and h 4 .
  • d 1 0 (D 1 equals 22).
  • d 2 6 (D 2 equals 10).
  • D 3 d 3 equals 7 (D 3 equals 8).
  • d 4 equals 8 (D 4 equals 6).
  • the recursive operation begins when a d delay 505 is over and the first input sample s[ 0 ] enters the second delay line 507 and subtractor 509 .
  • the subtractor 509 subtracts the output of the second delay line 507 (which at this point in time is 0) from the input sample.
  • the first value s[ 0 ] is summed with 0 in adder/subtractor 513 and stored in register 515 .
  • the next series of samples, s[1 to D ⁇ 1] are added together and stored 513 .
  • the input signal sampling frequency f s is typically lower than clock frequencies used within a filter.
  • a typical input signal sampling frequency f s may be 40 MHz, with each sample quantized to 12 bits.
  • the filter itself may operate at multiples of the sampling frequency f s , for example, at 160 MHz (4f s ).
  • the higher clock rate allows the filter circuits to perform multiple operations between input signal samples, allowing multiple component rectangular filters to be calculated and summed by the same circuit. Multiple component filters may be implemented in a time-multiplexed fashion on the same circuit thus reducing the total size and cost of the filter.
  • the filter 601 comprises a signal sample s[n] input 603 , a multiple port memory 605 , a first storage register 607 , a first subtractor 609 , an accumulator 611 comprising a second adder/subtractor 613 and a second storage register 615 , and a filter sample output o[n] 617 .
  • a controller 619 controls the filter operation.
  • the circuit operates synchronously timed by a clock (not shown) f f which is phase-aligned with the input sample clock f s .
  • the clock has a frequency which is an integer multiple of the sampling frequency If s depending on the number I of component impulse responses employed.
  • the preferred type of multiple port memory 605 employed by the invention is available in FPGA (Field Programmable Gate Array) integrated circuits. Other memory configurations may be used.
  • an input sample s[n] may be written to any of the addresses c, where 0 ⁇ c ⁇ M ⁇ 1.
  • the controller 619 is coupled to the multiple port memory 605 and second adder/subtractor 613 of the accumulator 611 .
  • the filter controller 619 provides first A 1 and second A 2 data access addresses, the write enable signal WE, a sign control for the accumulator 611 , and gating signals (not shown) used for initialization.
  • the controller 619 is implemented by means of a look-up table (LUT) 621 in which the sequence of values for the first A 1 and second A 2 addresses, the write enable WE and accumulator 613 sign control are predefined before operation.
  • the LUT 621 may be self-addressed, that is the sequence of LUT addresses is also programmed in the same LUT 621 .
  • the LUT address register is cleared, after which subsequent addresses are read from the LUT 621 itself. This operation simplifies the controller logic.
  • the LUT may be a read-only memory (ROM) or a random access memory (RAM).
  • the output of the LUT may be registered to increase circuit speed, and in this case the circuit timing and sequence of data in the LUT must be appropriately adjusted.
  • a pipeline register (not shown) may be inserted between the output of the first adder 609 and the input to the accumulator 611 .
  • the pipeline register adds an extra clock delay between the first adder 609 and the accumulator 611 , which requires the control signals' timing to be appropriately adjusted.
  • the filter 601 performs the function of a plurality of component filters as shown in FIG. 5 and employed in FIG. 4 .
  • Two filter clock cycles, subcycle 0 and subcycle 1 are defined within each sample clock cycle.
  • each component filter has M coefficients, the total impulse response of the filter 601 has M coefficients.
  • One of the component filters, h 1 or h 2 has M non-zero coefficients defining its kernel length.
  • the other component filter kernel may have the same number, or less than M non-zero coefficients, D.
  • the component filter having D non-zero coefficients may have d zeros added before the non-zero portion defining the rectangular response and may have trailing zeros such that the total length of the component impulse response is M.
  • the delay d before the non-zero coefficients may be greater than or equal to zero.
  • the accumulator 611 register 615 and memory 605 are initialized to 0.
  • the controller 619 is also initialized such that it generates address 0 on the first address output A 1 .
  • Operation begins with input sampling clock cycle 0 , with the arrival of sample s[ 0 ] at the filter input 603 .
  • subcycle 0 of sampling cycle 0 the old sample of component filter h 1 is read from address 0 of memory 505 via data bus D 1 (in the first M period cycles, the old value is 0 due to initialization).
  • Controller 619 asserts a memory write enable signal WE.
  • the clock leading edge of subcycle 1 stores the value from data bus D 1 into register 607 and writes sample s[ 0 ] into address 0 of memory 605 .
  • controller 619 de-asserts the memory write enable WE and causes address A 2 to take the value 0 causing sample s[ 0 ] to be read from address 0 of memory 605 to data bus D 2 , and to be forwarded to the input of accumulator register 615 via subtractor 609 and adder/subtractor 613 .
  • the total operation requires multiple subcycles, but since the operation is pipelined, a new operation is performed for each clock cycle.
  • the controller 619 asserts the sign control signal causing adder/subtractor 613 to perform addition or subtraction according to the sign of the non-zero coefficients of the first component filter h 1 .
  • controller 619 asserts an address A 1 which precedes address 0 by d+D, which according to the circular buffer addressing described above, results in the first address A 1 equaling M ⁇ d ⁇ D and represents the address of the old sample of the second component filter h 2 .
  • the contents of address A 1 is read via data bus D 1 .
  • the controller 619 generates addresses A 1 and A 2 , larger by 1 than the corresponding addresses generated in the previous sampling cycle, except that the addresses have a limited range of values according to the rules of circular buffer addressing. Namely, if during a sampling cycle an address reaches the value M ⁇ 1 then in the following sampling cycle the corresponding address does not take value M but wraps around to value 0.
  • the embodiment shown in FIG. 8 adds a scaling multiplexer 803 between the subtractor 609 and accumulator 611 .
  • the 2 n powers for each component filter h i are predefined scaling values assigned to a respective component filter (h 1 and h 2 ).
  • the multiplexer 803 shifts the binary value output by the subtractor 609 the predefined number of places towards the most significant bit (MSB) or the least significant bit (LSB), adding zeros if necessary. Moving a binary number one place (power) towards the MSB effectively multiplies the value by 2, the converse effectively divides the value by 2.
  • the use of the multiplexer 803 may improve the impulse response approximation, but not to the resolution afforded by using a multiplier 703 .
  • the invention may also be applied to 2-dimensional or higher-dimensional filters using the filter response decomposition method and implementation for the recursive calculation of multi-dimensional sums.
  • 2-dimensional or multi-dimensional filtering is often used during image processing and is similar to 1-dimensional filtering.
  • Filter response decompositions for multi-dimensional filters are not rectangular, but are parallelepiped or parallelepipedic components.
  • the teachings of the invention may be extended to include multi-dimensional filter responses.

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US11/633,875 US7912884B2 (en) 2006-12-04 2006-12-04 Method and apparatus for implementing finite impulse response filters without the use of multipliers
CN200780044500.3A CN101617235B (zh) 2006-12-04 2007-12-04 实现不使用乘法器的有限脉冲响应滤波器的方法和设备
EP07865153A EP2097759A4 (en) 2006-12-04 2007-12-04 METHOD AND DEVICE FOR IMPLEMENTING FILES WITH FINITER IMPULSE RESPONSE WITHOUT USING MULTIPLICATORS
PCT/US2007/086346 WO2008070644A2 (en) 2006-12-04 2007-12-04 Method and apparatus for implementing finite impulse response filters without the use of multipliers
JP2009540417A JP5108022B2 (ja) 2006-12-04 2007-12-04 乗算器を利用しない有限インパルス応答フィルタを実装する方法および装置
US13/032,924 US8452828B1 (en) 2006-12-04 2011-02-23 Method and apparatus for implementing finite impulse response filters without the use of multipliers

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EP2097759A4 (en) 2013-04-03
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US8452828B1 (en) 2013-05-28

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