US7829474B2 - Method for arraying nano material and method for fabricating liquid crystal display device using the same - Google Patents
Method for arraying nano material and method for fabricating liquid crystal display device using the same Download PDFInfo
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- US7829474B2 US7829474B2 US11/418,314 US41831406A US7829474B2 US 7829474 B2 US7829474 B2 US 7829474B2 US 41831406 A US41831406 A US 41831406A US 7829474 B2 US7829474 B2 US 7829474B2
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Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- the present invention relates to a method for arraying nano material, and more particularly, to a method for arraying nano material in a uniform direction, and to a method for fabricating a liquid crystal display device using the same.
- TFTs thin film transistors
- the TFTs can reduce power consumption of the display devices and are also advantageous to fabricate large-sized display devices.
- FIGS. 1A and 1B are schematic views of a related art TFT. Specifically, FIG. 1A is a plan view of the related art TFT and FIG. 1B is a sectional view taken along line I-I′ of FIG. 1A .
- a substrate 10 is prepared.
- a conductive material is deposited on the substrate 10 and is then patterned to form a gate electrode 20 .
- a gate insulating layer 30 is formed on an entire surface of the substrate 10 where the gate electrode 20 is formed.
- a semiconductor layer 40 is formed on the gate insulating layer 30 corresponding to the gate electrode 20 .
- a metal layer is deposited on the semiconductor layer 40 and is then patterned to form source/drain electrodes 50 a and 50 b . Consequently, the TFT is formed through these procedures.
- the semiconductor layer 40 may be an inorganic semiconductor layer or an organic semiconductor layer.
- the inorganic semiconductor layer may be formed of amorphous silicon (a-Si) or polysilicon (p-Si).
- a-Si amorphous silicon
- p-Si polysilicon
- the inorganic semiconductor layer may include an active layer 40 a and an ohmic contact layer 40 b formed by sequentially depositing and patterning amorphous silicon and P-type or N-type doped amorphous silicon.
- the organic semiconductor layer may be formed of polysilicon that is made by crystallizing amorphous silicon.
- the inorganic semiconductor layer In forming the inorganic semiconductor layer, it is necessary to form a thin film using an expensive deposition apparatus and perform an etching process, resulting in the increase of the manufacturing cost. Specifically, if the inorganic semiconductor layer is formed of the polysilicon having higher carrier mobility than that of the amorphous silicon, device characteristics can be improved. In this case, however, since the crystallization process is performed at a high temperature, a lot of problems may be caused. In addition, high technology is required to form a uniform polysilicon layer. Therefore, there is a great difficulty in forming the inorganic semiconductor layer 40 .
- the organic semiconductor layer can be easily formed and also used in flexible display devices.
- the organic semiconductor layer has lower carrier mobility than that of the inorganic semiconductor layer. Therefore, if an on-current level is increased, the size of the TFT is also increased. If the size of the TFT in the display device is increased, a region occupied by the pixel electrode in the unit pixel is reduced. Consequently, an aperture ratio is reduced and a cost is increased.
- the nano transistor includes an active layer and source/drain electrodes.
- the active layer is formed of nano material such as nanowire and nanotube, and the source/drain electrodes are arranged spaced apart from each other on the active layer.
- the active layer can be easily formed using a wet etching process, instead of a deposition process. Also, device characteristics are excellent because of the use of nano material.
- the nano material should be arranged in a uniform direction.
- the carrier mobility of the active layer formed of the nano material can be increased.
- the respective nano transistors may be formed to have the same characteristics. Also, in the display devices using the nano transistors, it is possible to secure uniform electrical characteristics of the nano transistors, thereby obtaining uniform image quality of the display devices.
- One of methods for arraying the nano material in a uniform direction is a Langmuir-Blodgett method.
- a substrate where a self assembly monolayer is formed is soaked in a solution where nano material is dispersed, and the nano material is adsorbed on the substrate.
- the Langmuir-Blodgett method is not suitable for mass production and its stabilization is degraded.
- trenches having a uniform direction are formed on a substrate, where nano material will be formed, and nano material is then inserted into the trenches.
- this method is difficult to form nano-sized trenches. Also, it is difficult to insert nano material into the nano-sized trenches, causing device failure.
- the present invention is directed to a method for arraying nano material, and to a method for fabricating a liquid crystal display device using the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.
- a method for arraying nano materials that includes coating a substrate with a dispersion solution in which nano materials are dispersed and arraying the nano materials in a uniform direction using a charged conductive body.
- a method for fabricating a liquid crystal display device that includes preparing a substrate having a gate line formed thereon.
- a gate insulating layer is formed on the gate line and a surface treatment is performed to divide the gate insulating layer into a hydrophilic region and a hydrophobic region.
- a dispersion solution, in which nano materials are dispersed, is applied onto the hydrophilic region.
- the nano materials are arrayed in a uniform direction using a charged body.
- the substrate is thermally treated to fix the nano materials to the gate insulating layer, and thereby forming a semiconductor layer.
- Source and drain electrodes which are spaced apart from each other, are formed on the semiconductor layer and a passivation layer is formed on an entire surface of the substrate including the source and drain electrodes.
- the passivation layer has a contact hole exposing a portion of the drain electrode.
- a pixel electrode is formed that electrically connects to the drain electrode through the contact hole.
- a method for fabricating a conductive layer of an liquid crystal display device includes providing a substrate and performing a surface treatment to form a hydrophilic region. A dispersion solution is applied in which nano materials are dispersed and the nano materials are arrayed in a uniform direction using a charged body. The substrate is thermally treated to fix the nano materials to the substrate to form the conductive layer.
- FIGS. 1A and 1B are schematic views of a related art TFT
- FIGS. 2A to 2C are views for explaining an apparatus and method for arraying nano material according to a first embodiment of the present invention
- FIGS. 3A and 3B are views for explaining a method for fabricating an LCD according to another embodiment of the present invention.
- FIGS. 4A to 4C are plan views for explaining the method for fabricating the LCD in detail according to yet another embodiment of the present invention.
- FIGS. 5A to 5C are views illustrating a method for arraying nano material according to a still further embodiment of the present invention.
- FIGS. 2A and 2B are views for explaining an apparatus and method for arraying nano material according to a first embodiment of the present invention. Specifically, FIG. 2A is a plan view illustrating a process of arraying nano material and FIGS. 2B and 2C are sectional views taken along line II-II′ of FIG. 2A .
- a dispersion solution 120 where nano materials 100 are dispersed is coated on a substrate 100 by a typical method.
- the typical method include an inkjet printing, a spin coating, a deep coating, and a doctor blade.
- the present invention is not limited to these methods.
- the nano materials 110 dispersed in the dispersion solution 120 are arrayed in a random direction.
- the nano materials 110 may be nanowires or nanotubes.
- the nano materials 110 can be a dielectric material and, more particularly, may be at least one material selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, P, GaN, ZnO, SiO 2 , and Al 2 O 3 .
- the dispersion solution 120 may include a hydrophilic solvent and further include polymer and dispersant.
- the hydrophilic solvent 120 disperses the nano materials 110 such that the substrate 110 is uniformly coated with it.
- the polymer makes the nano materials 110 attached to the substrate 100 or prevents the nano materials 110 from moving along a charged body within the dispersion solution during an align process.
- the dispersant stably disperses the nano materials 110 , thereby preventing the nano materials 110 from being agglomerated.
- a surface treatment may be further performed on the substrate 100 .
- the surface treatment is a process of dividing the substrate 100 into a hydrophilic region and a hydrophobic region.
- the nano materials 110 dispersed in the hydrophilic solvent may be formed in the hydrophilic region.
- the apparatus 200 for arraying the nano material is moved while contacting the surface of the dispersion solution 120 or being spaced apart therefrom by a predetermined distance. At this point, it is preferable that the apparatus 200 should be charged.
- the apparatus 200 of the present invention includes a circular support 210 , a conductive substrate 220 arranged on the support 210 , a power supply 230 electrically connected to the conductive substrate 220 , and insulators 240 arranged at the inner and outer sides of the conductive substrate 220 .
- the apparatus 200 may have a roller shape as shown in FIG. 2B , the present invention is not limited to this shape. That is, the apparatus 200 may have a flat panel shape or other shapes.
- the support 210 supports and fixes the conductive substrate 220 and the insulators 240 .
- the support 210 may further include a moving element (not shown) to freely move the apparatus 200 .
- the conductive substrate 220 may be a metal substrate. As shown in FIG. 2 , the conductive substrate 220 may surround the support 210 and may be disposed on at least the support 210 .
- the insulators 240 may be formed of hydrophobic material, such as polydimethylsiloxane (PDMS).
- PDMS polydimethylsiloxane
- the power supply 230 supplies power to the conductive substrate 220 , so that the apparatus 200 is charged. Therefore, due to an electric field generated by the supplied power, the nano materials 110 can be arrayed on the substrate 100 in a uniform direction.
- the apparatus can be charged using an electrostatic induction method generally used or an electrostatic induction method using friction. At this point, the ground with the power supply 230 may be used.
- the charged apparatus 200 moves along an upper portion of the substrate 100 in a predetermined direction.
- nano materials 110 dispersed within the dispersion solution 120 rotates in a direction of the charged apparatus 200 . That is, the nano materials 110 are erected in a region where the apparatus 200 is placed. On the contrary, in a region where the apparatus 200 is not placed, the nano materials 110 are inclined in a direction of the apparatus 200 .
- the nano materials 110 are horizontally inclined in a direction in which the apparatus 200 moves.
- the nano materials 110 rotate in a direction, in which an electric field is formed, without adjusting viscosity or moving in the dispersion solution 120 according to characteristics of the polymer.
- the nano materials 110 have dipole characteristics in which both sides are charged with positive charge and negative charge, respectively.
- the nano materials 110 can be fixed to the substrate 100 , while removing the hydrophilic solvent, the polymer, and the dispersant, except the nano materials 100 .
- the nano materials 110 can be arrayed on the substrate 100 in a constant direction.
- the present invention since the nano materials 110 can be arrayed in a constant direction, the present invention can be applied to various fields, such as lines, transistors, diodes, nano sensors, and semiconductor devices, which have excellent electrical conductivity and uniform characteristic.
- FIGS. 3A and 3B are views for explaining a method for fabricating an LCD according to a second embodiment of the present invention. Specifically, FIG. 3A is a plan view of a bottom substrate in the LCD and FIG. 3B is a sectional view taken along line III-III′ of FIG. 3A .
- a gate line 310 through which a gate signal is supplied is formed on a substrate 300 .
- a gate insulating layer 320 is formed on an entire surface of the substrate 300 where the gate line 310 is formed.
- a data line 340 intersecting with the gate line 310 is formed on the gate insulating layer 320 .
- a nano transistor is formed in an intersection region of the gate line 310 and the data line 340 .
- the nano transistor is smaller than an amorphous TFT or polysilicon TFT, it prevents a transmitted light or reflected light from being shielded, thereby improving the aperture ratio of the LCD. Also, even if the LCD includes complicated circuits, the pixel region is not reduced.
- the nano transistor includes a semiconductor layer 330 formed of nano materials 335 at the gate insulating layer 320 corresponding to the gate line 310 , which intersects with the data line 340 , and a source electrode 345 a and a drain electrode 345 b spaced apart from each other on the semiconductor layer 330 .
- the source electrode 345 a is connected to the data line 340 and the drain electrode 345 b is connected to the pixel electrode 360 . It is preferable that the nano materials 335 of the semiconductor layer 330 should be arrayed in a uniform direction. By doing so, the control of the respective unit pixels is easy and the uniform electrical characteristic can be obtained.
- the nano materials 335 may be nanotubes or nanowires.
- the nano materials 335 may also be selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, P, GaN, ZnO, SiO 2 , and Al 2 O 3 .
- a passivation layer 350 is formed on an entire surface of the substrate 300 where the nano transistor is formed.
- the passivation layer 350 may be formed of silicon oxide, silicon nitride, or a stacked layer thereof.
- a portion of the passivation layer 350 is etched to form a contact hole P exposing a portion of the drain electrode 345 b .
- a transparent conductive layer is deposited and patterned to form a pixel electrode 360 .
- the pixel electrode 360 is electrically connected to the drain electrode 345 b through the contact hole P.
- a top substrate including a color filter and a common electrode fabricated using a typical method is provided. Then, the top substrate is attached to the substrate where the nano transistors are formed, and liquid crystal is injected between the two substrates. The LCD is fabricated through these procedures.
- FIGS. 4A to 4C are plan views for explaining the method for fabricating the LCD according to the second embodiment of the present invention.
- a substrate 300 is prepared.
- a conductive layer is deposited on the substrate 300 and patterned to form a gate line 310 .
- a gate insulating layer 320 is formed on an entire surface of the substrate 300 where the gate line 310 is formed.
- the gate insulating layer 320 may be formed of silicon oxide, silicon nitride, or a stacked layer thereof.
- the gate insulating layer 320 is divided into a hydrophilic region 315 a and a hydrophobic region 315 b.
- a solution containing hydrophilic organic molecules is coated on the gate insulating layer 320 by a typical coating method and is then patterned to form the hydrophilic region 315 a .
- a solution containing hydrophobic organic molecules is coated on the gate insulating layer 320 and is then patterned to form the hydrophobic region 315 b . That is, by coating the solution containing the hydrophilic or hydrophobic organic molecules on the gate insulating layer 320 and patterning the coated solution, the gate insulating layer 320 can be divided into the hydrophilic region 315 a and the hydrophobic region 315 b.
- the hydrophilic region 315 a is a region corresponding to a predetermined portion of the gate line 310 and the predetermined portion may be an intersection region of the gate line 310 and the data line that will be formed later.
- a dispersion solution 337 where the nano materials 335 are dispersed is coated on the gate insulating layer 320 by a typical method.
- the typical method include an inkjet printing, a spin coating, a deep coating, and a doctor blade. More preferably, the dispersion solution 337 is locally dropped in the hydrophilic region ( 315 a in FIG. 4A ) using the inkjet printing.
- the nano materials 335 may be nanowires or nanotubes. Also, the nano materials 335 may be at least one material selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, P, GaN, ZnO, SiO 2 , and Al 2 O 3 . Also, the dispersion solution 337 may include a hydrophilic solvent, polymer and dispersant, in addition to the nano materials 335 .
- the apparatus 200 moves on the substrate 300 . At this point, it is preferable that the apparatus 200 should be charged.
- the apparatus 200 is moved on or above the surface of the dispersion solution 337 .
- the nano materials 335 can be arrayed in a uniform direction.
- the nano materials 335 can be fixed to the substrate 300 , while removing the hydrophilic solvent, the polymer, and the dispersant, except the nano materials 335 . Accordingly, it is possible to form the semiconductor layer 330 formed of the nano materials 335 arrayed in a uniform direction.
- the nano transistor having excellent carrier mobility can be fabricated. Also, by forming a plurality of nano transistors on the substrate, the respective nano transistors can have uniform characteristics.
- a passivation layer 350 is formed on an entire surface of the substrate where the nano transistor is formed.
- the passivation layer 350 may be formed of silicon oxide, silicon nitride, or a stacked layer thereof.
- a portion of the passivation layer 350 is etched to form a contact hole P exposing a portion of the drain electrode 345 b .
- a transparent conductive layer is deposited and patterned to form a pixel electrode 360 .
- the pixel electrode 360 is electrically connected to the drain electrode 345 b through the contact hole P.
- each nano transistor includes the semiconductor layer formed of the nano materials arrayed in a uniform direction, the control of each unit pixel becomes easy and the LCD can have uniform image picture.
- FIGS. 5A to 5C are views illustrating a method of arraying nano material according to a fourth embodiment of the present invention.
- the nano materials should have dipole characteristics divided into positive polarity and negative polarity.
- the basic principle is identical to that in FIGS. 2A to 2C , which will be referred herein.
- the charged body 400 is moved left or right by a predetermined distance along a direction parallel to a gate line.
- the nano materials 110 are rotated without moving along an electric field of the charged body.
- the nano materials 110 erected within the dispersion solution 120 are rotated to have a predetermined slope.
- a thermal treatment is performed to remove the dispersion solution 120 .
- the nano materials 110 tilted at a predetermined slope fall down on the substrate 100 and then are aligned.
- the nano materials are arrayed in a uniform direction, it is possible to form a plurality of transistors having uniform characteristics.
- the present invention is advantageous to mass production and the semiconductor layer can be formed using the wet etching process, which does not require an expensive deposition apparatus. Consequently, the productivity can be improved, while reducing the manufacturing cost.
- the semiconductor layer can be formed of nano materials arrayed in a uniform direction, the LCD can be easily controlled and provide uniform image quality.
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US20070026646A1 (en) | 2007-02-01 |
JP2007038393A (en) | 2007-02-15 |
KR20070014955A (en) | 2007-02-01 |
KR101252850B1 (en) | 2013-04-09 |
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