US7683485B2 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US7683485B2 US7683485B2 US12/071,123 US7112308A US7683485B2 US 7683485 B2 US7683485 B2 US 7683485B2 US 7112308 A US7112308 A US 7112308A US 7683485 B2 US7683485 B2 US 7683485B2
- Authority
- US
- United States
- Prior art keywords
- semiconductor chip
- chip
- substrate
- center
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a semiconductor device and, more particularly, to a semiconductor device with a ball grilled array (BGA) substrate in which a semiconductor chip is packaged.
- BGA ball grilled array
- This publication discloses a semiconductor device and its bonding structure which prolong the bonding lifetime by giving metal balls that are on the perimeter a higher tensile strength than that of other metal balls.
- a device assembled without giving consideration to the positional relation in the perpendicular direction between semiconductor chip edges and balls on a BGA substrate as described above has a problem in that, when mounted to another substrate (this is called secondary packaging) and then tested for packaging strength, the solder balls 8 frequently come detached in places where the edges of the semiconductor chip 1 align with the centers of the solder balls 8 on the BGA substrate 9 (the landing pads 7 where the BGA substrate 9 and the solder balls 8 come into contact, to be exact) in the perpendicular direction of the substrate.
- At least one of semiconductor chip edges does not align with the ball center position on an assembled substrate (preferably, landing pads where solder balls come into contact with the assembled substrate), stress concentrations on the landing pads are therefore avoided after assembly.
- the present invention makes it possible to reduce the defect of a ball and a BGA substrate falling apart from each other during or after assembly.
- a possible mechanism of this defect is as follows:
- An edge of a semiconductor chip is the interface between the semiconductor chip and packaging resin. Distortion from stress generated on the interface, especially stress due to heat, concentrates on the interface. Furthermore, the concentrated stress increases the stress difference among a BGA substrate, a solder ball, and a secondary packaging substrate which are under the interface, until the concentrated stress ultimately separates the solder ball from a landing pad. Placing the interface off an imaginary line extended from the landing pad therefore reduces the above defect exponentially.
- the above placement also mitigates limitation on chip size for semiconductor devices. Specifically, although the solder ball position in the semiconductor device to be mounted to the secondary packaging substrate is fixed with respect to the wiring pattern on the secondary packaging substrate, and this may put an edge of the semiconductor chip at the above-described solder ball position, no problems arise if the semiconductor chip is mounted to the packaging substrate such that the semiconductor chip center is offset from the center of the packaging substrate (will be called eccentric mounting).
- Eccentric mounting which provides an increased degree of freedom in chip size, also makes it easy to deal with simple chip shrinking or minor changes to the chip while maintaining the fixed solder ball position.
- eccentric mounting is effective in dealing with the proximity between a chip edge and the center of a solder ball (landing pad) which accompanies an increase/decrease in degree of integration (such as a simple cutdown or double-up, and a chip size reduction through simple process shrinking).
- the packaging area can be reduced in the secondary packaging substrate.
- the secondary packaging area is reduced by putting all of solder balls which are arranged at the minimum pitch on the matrix into use. In other words, it eliminates the need for consideration and limitation in ball arrangement that ensures the reliability of solder balls, for example, omitting balls from an area directly below the semiconductor chip, especially areas immediately below chip edges and immediately below chip corners, or making solder balls in those areas as non-functional, dummy balls.
- FIG. 1 is a diagram showing a cross-sectional view of a semiconductor device according to a first embodiment of the present invention
- FIG. 2 is a diagram showing a plan view of the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a diagram in which the semiconductor device according to the first embodiment of the present invention is mounted
- FIG. 4 is a schematic diagram of common semiconductor device packaging
- FIG. 5 is a diagram showing a modification example of the semiconductor device according to the first embodiment of the present invention.
- FIG. 6 is a diagram showing a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
- FIG. 7 is a diagram showing a plan view of the semiconductor device according to the second embodiment of the present invention.
- FIG. 8 is a diagram showing a modification example of the semiconductor device according to the second embodiment of the present invention.
- FIG. 9 is a diagram showing a cross-sectional view of a conventional semiconductor device.
- FIG. 10 is a diagram showing a plan view of the conventional semiconductor device.
- FIGS. 1 through 3 are diagrams showing a semiconductor device according to a first embodiment of the present invention.
- FIG. 1 is a diagram showing a cross-sectional view of the semiconductor device according to the first embodiment of the present invention
- FIG. 2 is a planar perspective view of the semiconductor device viewed from the above.
- FIG. 3 is a cross-sectional view in which the semiconductor device is mounted to another substrate (this is called secondary packaging).
- wiring (circuit) patterns 4 and 6 are formed on the top and bottom faces of a BGA substrate 9 , and a semiconductor chip 1 is mounted to the top or bottom-face of the BGA substrate 9 with an adhesive 16 (this is called primary packaging). Bonding pads 2 on the semiconductor chip 1 are electrically coupled by bonding wires 3 to the wiring patterns 4 on the top face of the BGA substrate 9 .
- the wiring patterns 4 are coupled to wiring patterns 6 , which are on the bottom face of the circuit substrate 9 , through through holes 5 , and also coupled to solder balls 8 through landing pads 7 .
- a piece of insulating tape 15 covers an area between the landing pads 7 on the other face of the BGA substrate 9 to which the chip is not mounted.
- the semiconductor chip 1 on the BGA substrate 9 is covered with mold resin 10 .
- FIG. 2 looks up to the semiconductor chip from below.
- the position of the semiconductor chip 1 which otherwise cannot be seen from below is seen through in FIG. 2 .
- the semiconductor chip 1 is mounted to the circuit substrate 9 such that central coordinates C 1 of the semiconductor chip 1 do not coincide with central coordinates C 2 of the circuit substrate 9 . This prevents edges of the semiconductor chip 1 from aligning with the centers of the solder balls 8 (the landing pads 7 where the solder balls and the BGA substrate are bonded).
- FIG. 2 employs a solid line to indicate the solder ball diameter and a dotted line to indicate the landing pad diameter.
- the insulating tape 15 covers the bottom face of the BGA substrate except the landing pads.
- the substrate positioning of conventional art in which the edges of the semiconductor chip 1 align with the centers of the solder balls 8 on the BGA substrate 9 in a direction perpendicular to the substrate is avoided as shown in FIG. 3 .
- the stress concentration generated on contact areas between the balls and the BGA substrate is thus mitigated, and the defect of the solder balls 8 coming detached from the landing pads 7 during or after assembly is reduced drastically.
- FIG. 4 positioning of the semiconductor chip 1 and the BGA substrate 9 in relation to each other.
- the four sides of the semiconductor chip are positioned (angles ⁇ 1 and ⁇ 2 in FIG. 4 ) in relation to the four sides of the BGA substrate which has given numbers of rows and columns (three rows ⁇ five columns in the drawing).
- One chip taken out of the fifteen chips will be discussed in the following description for simplification.
- the semiconductor chip can be disposed in any place of the BGA substrate by simply setting corner coordinates of the semiconductor chip 1 (x 2 , y 2 ) with respect to corner coordinates of the BGA substrate (x 1 , y 1 ) in a mounting machine.
- the center of the semiconductor chip and the center of the BGA substrate are thus prevented from coinciding with each other.
- the solder ball interval (pitch A) shown in the drawing is normally 1.0 mm, and 0.5 mm in the case of fine pitch BGA (FPBGA), whereas the arrangement accuracy or error of the mounting machine (pitch B) is about ⁇ a few tens to a few hundreds ⁇ m.
- An edge of the semiconductor chip can therefore be placed in a gap between solder balls with ease.
- the above embodiment takes assembly by bonding as an example.
- a modification example of the first embodiment of the present invention is shown in FIG. 5 .
- the semiconductor chip 1 is a flip chip and pads 2 on the flip chip are press-fit to the BGA substrate 9 through metal bumps 12 .
- the semiconductor chip 1 in this case, too, is positioned such that semiconductor chip edges do not align with the solder ball centers as in the above embodiment.
- FIGS. 6 and 7 are diagrams showing a semiconductor device according to a second embodiment of the present invention.
- a semiconductor chip 13 is layered over the semiconductor chip 1 of the first embodiment of the present invention, thereby making a multi-chip package (MCP) structure.
- MCP multi-chip package
- the two layered semiconductor chips are arranged such that their respective edges do not align with the ball positions on the BGA substrate in the perpendicular direction as in the first embodiment of the present invention. This will be described below with reference to FIG. 7 , which is a diagram visualizing a planar perspective view of the chip from above the chip.
- the center of the lower semiconductor chip 1 and the center of the upper semiconductor chip 13 coincide with each other in this embodiment.
- the centers of the upper and lower semiconductor chips must not coincide with each other.
- FIG. 8 is a modification example of the second embodiment of the present invention. Shown in FIG. 8 is a case in which the upper chip size is larger than the lower chip size, or opposing two sides are longer in the upper chip than in the lower chip, in other words, the upper chip protrudes from the lower chip.
- the first semiconductor chip 1 is mounted to the BGA substrate, the spacer 14 is placed on the first semiconductor chip 1 , and then the second semiconductor chip 13 is mounted to the spacer 14 .
- first and second embodiments of the present invention may be employed in combination, so that the lower chip is flip chip-bonded and the second chip is mounted to the lower chip by bonding.
- the number of chip layers is not limited to two, and three or more semiconductor chips may be layered and, needless to say, the present invention is applicable not only to cases where multiple chips are stacked but also to cases where multiple chips are arranged side by side. And the present invention is applicable not only to case where BGA but also to cases where LGA etc. In other words, the ball can be changed to a terminal.
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57120/2007 | 2007-03-07 | ||
JP2007057120A JP2008218882A (en) | 2007-03-07 | 2007-03-07 | Semiconductor device |
JP2007-057120 | 2007-03-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080217774A1 US20080217774A1 (en) | 2008-09-11 |
US7683485B2 true US7683485B2 (en) | 2010-03-23 |
Family
ID=39740827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/071,123 Active 2028-09-05 US7683485B2 (en) | 2007-03-07 | 2008-02-15 | Semiconductor device |
Country Status (3)
Country | Link |
---|---|
US (1) | US7683485B2 (en) |
JP (1) | JP2008218882A (en) |
CN (1) | CN101261975A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090224403A1 (en) * | 2008-03-06 | 2009-09-10 | Elpida Memory, Inc | Semiconductor device and method of manufacturing the same |
US8610288B2 (en) | 2010-04-23 | 2013-12-17 | Elpida Memory, Inc. | Semiconductor device with stacked semiconductor chips |
US20150332986A1 (en) * | 2014-05-14 | 2015-11-19 | Micron Technology, Inc. | Semiconductor device including semiconductor chip covered with sealing resin |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6013748B2 (en) * | 2012-03-22 | 2016-10-25 | Hoya株式会社 | Semiconductor package |
US8766453B2 (en) * | 2012-10-25 | 2014-07-01 | Freescale Semiconductor, Inc. | Packaged integrated circuit having large solder pads and method for forming |
US10826194B2 (en) | 2018-02-21 | 2020-11-03 | International Business Machines Corporation | Scalable phased array package |
US10784563B2 (en) * | 2018-02-21 | 2020-09-22 | International Business Machines Corporation | Scalable phased array package |
CN112582333A (en) * | 2019-09-27 | 2021-03-30 | 中芯长电半导体(江阴)有限公司 | Rewiring layer and preparation method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001144214A (en) | 1999-11-17 | 2001-05-25 | Canon Inc | Semiconductor device and bonding structure thereof |
US6995469B2 (en) * | 2003-05-21 | 2006-02-07 | Olympus Corporation | Semiconductor apparatus and fabricating method for the same |
US20070004083A1 (en) * | 2004-08-07 | 2007-01-04 | Texas Instruments Incorporated | Arrangement in Semiconductor Packages for Inhibiting Adhesion of Lid to Substrate While Providing Compression Support |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5637920A (en) * | 1995-10-04 | 1997-06-10 | Lsi Logic Corporation | High contact density ball grid array package for flip-chips |
-
2007
- 2007-03-07 JP JP2007057120A patent/JP2008218882A/en active Pending
-
2008
- 2008-02-15 US US12/071,123 patent/US7683485B2/en active Active
- 2008-03-05 CN CNA2008100834296A patent/CN101261975A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001144214A (en) | 1999-11-17 | 2001-05-25 | Canon Inc | Semiconductor device and bonding structure thereof |
US6995469B2 (en) * | 2003-05-21 | 2006-02-07 | Olympus Corporation | Semiconductor apparatus and fabricating method for the same |
US20070004083A1 (en) * | 2004-08-07 | 2007-01-04 | Texas Instruments Incorporated | Arrangement in Semiconductor Packages for Inhibiting Adhesion of Lid to Substrate While Providing Compression Support |
Non-Patent Citations (1)
Title |
---|
R. Mathew, et al., "1 Gb/s Ethernet Physical Layer Device Package Development", 2006 Electronic Components and Technology Conference IEEE ECTC (p. 35-40) on May 31, 2006. |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090224403A1 (en) * | 2008-03-06 | 2009-09-10 | Elpida Memory, Inc | Semiconductor device and method of manufacturing the same |
US8178971B2 (en) * | 2008-03-06 | 2012-05-15 | Elpida Memory, Inc. | Semiconductor device and method of manufacturing the same |
USRE45932E1 (en) * | 2008-03-06 | 2016-03-15 | Ps4 Luxco S.A.R.L. | Semiconductor device and method of manufacturing the same |
US8610288B2 (en) | 2010-04-23 | 2013-12-17 | Elpida Memory, Inc. | Semiconductor device with stacked semiconductor chips |
US9177941B2 (en) | 2010-04-23 | 2015-11-03 | Ps4 Luxco S.A.R.L. | Semiconductor device with stacked semiconductor chips |
US20150332986A1 (en) * | 2014-05-14 | 2015-11-19 | Micron Technology, Inc. | Semiconductor device including semiconductor chip covered with sealing resin |
US9362194B2 (en) * | 2014-05-14 | 2016-06-07 | Micron Technology, Inc. | Semiconductor chip covered with sealing resin having a filler material |
Also Published As
Publication number | Publication date |
---|---|
CN101261975A (en) | 2008-09-10 |
US20080217774A1 (en) | 2008-09-11 |
JP2008218882A (en) | 2008-09-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9761563B2 (en) | Multi-chip package having a stacked plurality of different sized semiconductor chips, and method of manufacturing the same | |
US7683485B2 (en) | Semiconductor device | |
US10431556B2 (en) | Semiconductor device including semiconductor chips mounted over both surfaces of substrate | |
US7598617B2 (en) | Stack package utilizing through vias and re-distribution lines | |
US7402911B2 (en) | Multi-chip device and method for producing a multi-chip device | |
US6674175B2 (en) | Ball grid array chip packages having improved testing and stacking characteristics | |
KR100621991B1 (en) | Chip scale stack package | |
US9627366B2 (en) | Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another | |
US20120127674A1 (en) | Semiconductor device assemblies including elongated fasteners | |
US20070045803A1 (en) | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices | |
JP2006522478A (en) | Semiconductor multi-package module including processor and memory package assembly | |
JP3490314B2 (en) | Multi-chip type semiconductor device | |
KR20090034180A (en) | Semiconductor package having interposer and electronic apparatus and method for manufacturing semiconductor package | |
US7902664B2 (en) | Semiconductor package having passive component and semiconductor memory module including the same | |
US7868439B2 (en) | Chip package and substrate thereof | |
US20030015803A1 (en) | High-density multichip module and method for manufacturing the same | |
US20090065924A1 (en) | Semiconductor package with reduced volume and signal transfer path | |
KR100426608B1 (en) | Center pad type integrated circuit chip that means for jumpering is mounted on the active layer and manufacturing method thereof and multi chip package | |
US20050230829A1 (en) | Semiconductor device | |
TWI841208B (en) | Package structure and method of forming thereof | |
KR20080084075A (en) | Stacked semiconductor package | |
KR20070078953A (en) | Stack type package | |
KR20230143497A (en) | Semiconductor package and method for manufacturing the same | |
TW202433706A (en) | Package structure | |
KR20020042958A (en) | Stack chip package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NEC ELECTRONICS CORPORATION,JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NIKAIDO, HIROFUMI;REEL/FRAME:020567/0127 Effective date: 20080208 Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NIKAIDO, HIROFUMI;REEL/FRAME:020567/0127 Effective date: 20080208 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025235/0497 Effective date: 20100401 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF ADDRESS;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:044928/0001 Effective date: 20150806 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |