US7682904B2 - Method of fabricating flash memory device - Google Patents

Method of fabricating flash memory device Download PDF

Info

Publication number
US7682904B2
US7682904B2 US12/131,626 US13162608A US7682904B2 US 7682904 B2 US7682904 B2 US 7682904B2 US 13162608 A US13162608 A US 13162608A US 7682904 B2 US7682904 B2 US 7682904B2
Authority
US
United States
Prior art keywords
layer
forming
oxidization
conductive layer
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US12/131,626
Other versions
US20090023279A1 (en
Inventor
Eun Soo Kim
Jung Geun Kim
Suk Joong Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, EUN SOO, KIM, JUNG GEUN, KIM, SUK JOONG
Publication of US20090023279A1 publication Critical patent/US20090023279A1/en
Application granted granted Critical
Publication of US7682904B2 publication Critical patent/US7682904B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a method of fabricating a flash memory device and, more particularly, to a method of fabricating a flash memory device that can improve an interference phenomenon between neighboring word lines and prevent abnormal oxidization of a conductive layer for a control gate.
  • a flash memory device is a memory device that can retain its data when power is off.
  • This flash memory device is equipped with a charge trap layer in which charges are trapped in order to cause a threshold voltage (Vth) difference between the gate and the channel.
  • the threshold voltage (Vth) is varied depending on a state (a program state or an erase state in which electrons are discharged) in which charges are injected into the charge trap layer.
  • a gate voltage (Vg) for turning on the channel is varied.
  • the operation of the flash memory device is implemented based on the concept that the threshold voltage (Vth) is changed depending on charges trapped or stored in the charge trap layer.
  • a control gate is formed using a tungsten (W) layer with a low resistivity. Formation of the control gate using the tungsten layer causes abnormal oxidization of the tungsten layer during a subsequent annealing process. The abnormal oxidization is caused by a reaction between the tungsten (W) in the tungsten layer and the oxygen in an oxide layer of the spacer. Such abnormal oxidization of the tungsten layer becomes a significant problem in securing the reliability of a device after the process is finished.
  • the width of isolation layers is narrowed and a distance between neighboring word lines and between neighboring floating gates is reduced.
  • An interference capacitor in the word line direction, the bit line direction, and the like causes an interference that deepens the shift of the cell threshold voltage, making normal cell operation difficult.
  • An insulating layer between floating gates is generally formed of an oxide layer having a dielectric constant of 4.2. However, it is difficult to lower the capacitance value in order to form spacers. Using a material having a low dielectric constant instead of the oxide layer does not solve the fundamental problem and is difficult to implement.
  • the present invention is directed towards a method of fabricating a flash memory device, which can have one or more benefits, such as improving interference between neighboring word lines, preventing abnormal oxidization of a conductive layer for a control gate, and implementing a robust high-speed device.
  • a method of fabricating a flash memory device in accordance with an aspect of the present invention includes providing a semiconductor substrate in which a tunnel dielectric layer, a first conductive layer, a dielectric layer, and a second conductive layer are formed, patterning the second conductive layer and the dielectric layer, forming an anti-oxidization layer over the first conductive layer, including the patterned second conductive layer and the patterned dielectric layer, etching the anti-oxidization layer, while etching the first conductive layer, in such a manner that the anti-oxidization layer remains on sidewalls of the second conductive layer and the first conductive layer is patterned, forming a first insulating layer having an overhang shape on its top while surrounding each element of the remaining anti-oxidization layer, and forming a second insulating layer having an air-gap between the first insulating layers on the sidewalls of adjacent elements of the patterned first conductive layer.
  • the second conductive layer can be formed of a tungsten (W) layer.
  • the anti-oxidization layer can be formed of a tungsten nitride (WN) layer.
  • the anti-oxidization layer can be formed using a Chemical Vapor Deposition (CVD) or a Physical Vapor Deposition (PVD) method.
  • the anti-oxidization layer can be formed to a thickness in a range of 80 to 100 angstrom, for example by using the CVD method.
  • the anti-oxidization layer can be formed to a thickness in a range of 200 to 300 angstrom, for example by using the PVD method.
  • the anti-oxidization layer can remain at a thickness in a range of 20 to 50 angstrom on the sidewalls of the second conductive layer.
  • the first insulating layer can be formed of an insulating layer having a poor gap-filling characteristic.
  • the insulating layer having a poor gap-filling characteristic can include an Ozone-Tetra Ortho Silicate Glass (O 3 -TEOS) layer or an Undoped Silicate Glass (USG) layer.
  • the first insulating layer can be formed to a thickness in a range of 300 to 500 angstrom, for example by using the CVD method.
  • the second insulating layer can be formed of a High Density Plasma (HDP) oxide layer.
  • HDP High Density Plasma
  • an additional etch process can be further performed in order to partially remove the overhang shapes.
  • a barrier layer can be formed on the dielectric layer before the second conductive layer is formed.
  • the barrier layer can be formed of a tungsten nitride (WN) layer.
  • a hard mask can be formed on the second conductive layer before the second conductive layer is patterned. The hard mask can be formed of material that does not react with the second conductive layer at the time of annealing. When the first conductive layer is patterned, the hard mask can partially remain.
  • An annealing process can be further performed after the second insulating layer is formed.
  • the tungsten nitride (WN) layer of the anti-oxidization layer and the barrier layer that remain after the annealing process is completed can be changed into a tungsten layer to increase a cross section of the second conductive layer.
  • FIGS. 1A to 1G are sectional views showing a method of fabricating a flash memory device in accordance with an embodiment of the present invention.
  • FIGS. 1A to 1G are sectional views showing a method of fabricating a flash memory device in accordance with an embodiment of the present invention.
  • a tunnel dielectric layer 102 and a first conductive layer 104 are formed over a semiconductor substrate 100 .
  • the tunnel dielectric layer 102 can be formed, for example, of a silicon oxide (SiO 2 ) layer. In this embodiment, an oxidation process can be used to form the tunnel dielectric layer 102 .
  • the first conductive layer 104 can be used as a floating gate and can be formed, for example, of a polysilicon layer, a metal layer, or a stacked layer of them. Preferably, a polysilicon layer is used.
  • An etch process employing a mask is performed to pattern the first conductive layer 104 and the tunnel dielectric layer 102 in the isolation region in one direction (a bit line direction), exposing the semiconductor substrate 100 in the isolation region.
  • the semiconductor substrate 100 exposed in the isolation region is etched to a specific depth to form trenches (not shown).
  • An insulating layer is formed by depositing insulating material over the semiconductor substrate 100 including the trenches, such that the trenches are gap-filled. A polishing process is then performed to form isolation layers (not shown) in the trench regions. Thereafter, an additional etch process can be performed in order to control the Effective Field Oxide Height (EFH) of the isolation layers.
  • ESH Effective Field Oxide Height
  • a dielectric layer 106 , a barrier layer 108 , a second conductive layer 110 , and a hard mask 112 are sequentially formed over the semiconductor substrate 100 including the first conductive layer 104 and the isolation layers.
  • the dielectric layer 106 can have, for example, an Oxide-Nitride-Oxide (ONO) stacked layer structure formed of a first oxide layer 106 a , a nitride layer 106 b , and a second oxide layer 106 c .
  • the second conductive layer 110 can be used as a control gate and can be formed of a tungsten (W) layer, for example in order to implement a high-speed device and improve an interference phenomenon between neighboring cells.
  • W tungsten
  • the barrier layer 108 is to be used as a barrier for forming the second conductive layer 110 and can be formed, for example, of a tungsten nitride (WN) layer.
  • the barrier layer 108 and the second conductive layer 110 preferably are formed using a PVD method. After the barrier layer 108 is formed, the second conductive layer 110 can be formed in-situ.
  • the hard mask 112 can prevent etch damage to the second conductive layer 110 during a subsequent gate etch process.
  • the hard mask 112 can be formed of material that does not react with the second conductive layer 110 , e.g. a tungsten layer for a control gate, during annealing.
  • the hard mask 112 can be formed of silicon oxynitride (SiON).
  • the hard mask 112 , the second conductive layer 110 , and the barrier layer 108 are patterned in a direction crossing the isolation layers by performing an etch process employing a mask (not shown).
  • the patterning may expose the dielectric layer 106 .
  • a control gate 110 a comprised of the second conductive layer 110 is formed.
  • the control gates 110 a of cells formed in different strings are interconnected to form word lines.
  • the hard mask 112 can also be etched to a specific thickness.
  • the exposed dielectric layer 106 is patterned by an etch process to expose the first conductive layer 104 . Meanwhile, in the etch process, the first conductive layer 104 can also be partially etched.
  • An anti-oxidization layer 114 is formed on the first conductive layer 104 including the dielectric layer 106 , the barrier layer 108 , the control gate 110 a , and the hard mask 112 .
  • the anti-oxidization layer 114 can prevent abnormal oxidization of the control gate 110 a, which is caused by a reaction, during an annealing process, between the tungsten (W) of the control gate 110 a and the oxygen of a subsequently formed spacer having an oxide layer.
  • the anti-oxidization layer 114 can be formed, for example, of a tungsten nitride (WN) layer.
  • the tungsten nitride (WN) layer can be formed, for example, using a CVD or PVD method.
  • the anti-oxidization layer 114 e.g. a tungsten nitride layer can be formed to a thickness sufficient to remain on the sidewalls of the control gate 110 a to protect the control gates 110 a after a subsequent gate etch process is completed.
  • the anti-oxidization layer 114 can be deposited to a thickness in a range of 80 to 100 angstrom when the CVD method is used, and to a thickness in a range of 200 to 300 angstrom when the PVD method is used.
  • the first conductive layer 104 is patterned by performing an etch process using the anti-oxidization layer 114 as an etch mask to form a floating gate 104 a that includes the first conductive layer 104 .
  • the surface of the tunnel dielectric layer 102 can be exposed by the patterning.
  • a gate pattern 116 that includes the tunnel dielectric layer 102 , the floating gate 104 a , the dielectric layer 106 , the barrier layer 108 , the control gate 110 a , and the hard mask 112 is also formed.
  • the anti-oxidization layer 114 preferably remains, in spacer form, on the sidewalls of the control gates 110 a while patterning the first conductive layer 104 .
  • the anti-oxidization layer 114 that remains on the sidewalls of the control gate 110 a can have a thickness in a range of 20 to 50 angstrom.
  • the anti-oxidization layer 114 that remains on the sidewalls of the control gate 110 a can prevent abnormal oxidization of the control gate 110 a during a subsequent annealing process.
  • the hard mask 112 can also be etched.
  • the hard mask 112 partially remain in order to prohibit abnormal oxidization of the control gate 110 caused by a reaction, during an annealing process, between the tungsten (W) in the control gate 110 a and the oxygen of the subsequently formed spacer having an oxide layer.
  • a first insulating layer 118 for spacers is formed to have an overhang shape while surrounding a top surface of the gate pattern 116 .
  • the first insulating layer 118 can be formed to a thickness in a range of 300 to 500 angstrom.
  • An air-gap 122 within a subsequently formed insulating layer between neighboring word lines can be formed by using a first insulating layer 118 formed of an insulating layer material having a poor gap-filling characteristic.
  • the first insulating layer 118 can be formed, for example, of an O 3 -TEOS layer or a USG layer. In this embodiment, the first insulating layer 118 preferably is formed using a CVD method.
  • a deposition rate is faster at the top of the gate pattern 116 than at the semiconductor substrate 100 due to the material having a poor gap-filling characteristic.
  • an overhang shape can be formed at the top of the first insulating layer 118 while the first insulating layer 118 is deposited.
  • the overhang shape causes the first insulating layer 118 to have a negative slope, which can potentially degrade a subsequent gap-fill characteristic.
  • An insulating layer for spacers has to be additionally deposited subsequently.
  • the overhang shape of the first insulating layer 118 formed on an element of the gate pattern 116 does not come in contact with an overhang shape of the first insulating layer 118 formed on an adjacent element of the gate pattern 116 .
  • the first insulating layer 118 can be formed to a thickness of 300 to 500 angstrom.
  • the first insulating layer 118 can be partially etched by an additional etch process in order to partially remove the overhang shapes and open a deposition entry for deposition of a second insulating layer 120 .
  • a second insulating layer 120 for spacers is formed by depositing an insulating material over the semiconductor substrate 100 including the first insulating layer 118 having the overhang shape.
  • the second insulating layer 120 can be formed, for example, using an oxide layer, preferably, a HDP oxide layer employing a HDP method.
  • an air-gap 122 is formed within the second insulating layer 120 between elements of the gate pattern 116 .
  • the air-gap 122 is formed between the first insulating layers 118 on sidewalls of neighboring floating gates 104 a.
  • the dielectric constant of the oxide layer is approximately 4.2, whereas the dielectric constant of air is 1.0.
  • the air-gap 122 having a low dielectric constant of 1.0 is formed between the gate patterns 116 (for example, the floating gate 104 a and the word line), interference capacitance between neighboring word lines is reduced and, therefore, an interference effect between neighboring word lines can be improved.
  • a subsequent fabrication process of a flash memory device generally includes an annealing process performed at high temperature.
  • the annealing process is preferably performed after the second insulating layer 120 is formed or subsequent other processes are performed.
  • the flash memory device after the annealing process is completed is described below with reference to the accompanying drawings.
  • the flash memory device having the structure as shown in FIG. 1F can prevent abnormal oxidization of the control gate 110 a by preventing a reaction, during the annealing process, between the tungsten (W) in the control gate 110 a and the oxygen in the first insulating layer 118 .
  • Diffusion of nitrogen (N 2 ) within the anti-oxidization layer 114 to the outside during the annealing performed at a high temperature of 700 to 1000 degrees Celsius can prevent the abnormal oxidization of the control gate 110 a. Consequently, the reliability of the device can be improved and a robust device can be implemented.
  • a final control gate 110 b that is formed after the annealing process has an increased cross section occupied by the tungsten (W) layer, which can aid in implementing a high-speed device.
  • the air-gap having a low dielectric constant is formed within the oxide layer for spacers between the word lines and the floating gates, so interference between neighboring word lines can be improved. Accordingly, a high-speed device can be implemented.
  • the tungsten nitride (WN) layer is formed on the sidewalls of the tungsten (W) layer for the control gate.
  • the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. Accordingly, the reliability of a device can be improved and a robust high-speed device can be implemented.
  • the tungsten nitride (WN) layer is changed into the tungsten layer in a subsequent annealing process. Accordingly, the cross section of the control gate that is finally formed can be increased. Accordingly, a higher-speed device can be implemented.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.

Description

CROSS-REFERENCES TO RELATED APPLICATION
The priority of Korean Patent Application Number 10-2007-0071643, filed on Jul. 18, 2007, is hereby claimed and the disclosure thereof is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a flash memory device and, more particularly, to a method of fabricating a flash memory device that can improve an interference phenomenon between neighboring word lines and prevent abnormal oxidization of a conductive layer for a control gate.
A flash memory device is a memory device that can retain its data when power is off. This flash memory device is equipped with a charge trap layer in which charges are trapped in order to cause a threshold voltage (Vth) difference between the gate and the channel. The threshold voltage (Vth) is varied depending on a state (a program state or an erase state in which electrons are discharged) in which charges are injected into the charge trap layer. Thus, a gate voltage (Vg) for turning on the channel is varied. The operation of the flash memory device is implemented based on the concept that the threshold voltage (Vth) is changed depending on charges trapped or stored in the charge trap layer.
Recently, as a high speed of a device is required in line with higher integration of the device, a control gate is formed using a tungsten (W) layer with a low resistivity. Formation of the control gate using the tungsten layer causes abnormal oxidization of the tungsten layer during a subsequent annealing process. The abnormal oxidization is caused by a reaction between the tungsten (W) in the tungsten layer and the oxygen in an oxide layer of the spacer. Such abnormal oxidization of the tungsten layer becomes a significant problem in securing the reliability of a device after the process is finished.
Further, as devices are more highly integrated, the width of isolation layers is narrowed and a distance between neighboring word lines and between neighboring floating gates is reduced. An interference capacitor in the word line direction, the bit line direction, and the like causes an interference that deepens the shift of the cell threshold voltage, making normal cell operation difficult. An insulating layer between floating gates is generally formed of an oxide layer having a dielectric constant of 4.2. However, it is difficult to lower the capacitance value in order to form spacers. Using a material having a low dielectric constant instead of the oxide layer does not solve the fundamental problem and is difficult to implement.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed towards a method of fabricating a flash memory device, which can have one or more benefits, such as improving interference between neighboring word lines, preventing abnormal oxidization of a conductive layer for a control gate, and implementing a robust high-speed device.
A method of fabricating a flash memory device in accordance with an aspect of the present invention includes providing a semiconductor substrate in which a tunnel dielectric layer, a first conductive layer, a dielectric layer, and a second conductive layer are formed, patterning the second conductive layer and the dielectric layer, forming an anti-oxidization layer over the first conductive layer, including the patterned second conductive layer and the patterned dielectric layer, etching the anti-oxidization layer, while etching the first conductive layer, in such a manner that the anti-oxidization layer remains on sidewalls of the second conductive layer and the first conductive layer is patterned, forming a first insulating layer having an overhang shape on its top while surrounding each element of the remaining anti-oxidization layer, and forming a second insulating layer having an air-gap between the first insulating layers on the sidewalls of adjacent elements of the patterned first conductive layer.
The second conductive layer can be formed of a tungsten (W) layer. The anti-oxidization layer can be formed of a tungsten nitride (WN) layer. The anti-oxidization layer can be formed using a Chemical Vapor Deposition (CVD) or a Physical Vapor Deposition (PVD) method. The anti-oxidization layer can be formed to a thickness in a range of 80 to 100 angstrom, for example by using the CVD method. The anti-oxidization layer can be formed to a thickness in a range of 200 to 300 angstrom, for example by using the PVD method. The anti-oxidization layer can remain at a thickness in a range of 20 to 50 angstrom on the sidewalls of the second conductive layer. The first insulating layer can be formed of an insulating layer having a poor gap-filling characteristic.
The insulating layer having a poor gap-filling characteristic can include an Ozone-Tetra Ortho Silicate Glass (O3-TEOS) layer or an Undoped Silicate Glass (USG) layer. The first insulating layer can be formed to a thickness in a range of 300 to 500 angstrom, for example by using the CVD method. The second insulating layer can be formed of a High Density Plasma (HDP) oxide layer.
If the overhang shape come in contact with an overhang shape formed on an adjacent element of the remaining anti-oxidization layer when the first insulating layer is formed, an additional etch process can be further performed in order to partially remove the overhang shapes. A barrier layer can be formed on the dielectric layer before the second conductive layer is formed. The barrier layer can be formed of a tungsten nitride (WN) layer. A hard mask can be formed on the second conductive layer before the second conductive layer is patterned. The hard mask can be formed of material that does not react with the second conductive layer at the time of annealing. When the first conductive layer is patterned, the hard mask can partially remain.
An annealing process can be further performed after the second insulating layer is formed. The tungsten nitride (WN) layer of the anti-oxidization layer and the barrier layer that remain after the annealing process is completed can be changed into a tungsten layer to increase a cross section of the second conductive layer.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawings.
FIGS. 1A to 1G are sectional views showing a method of fabricating a flash memory device in accordance with an embodiment of the present invention.
 DESCRIPTION OF SPECIFIC EMBODIMENTS
Now, specific embodiments according to the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the disclosed embodiments, but can be implemented in various manners. The embodiments are provided to complete the disclosure of the present invention and to allow those having ordinary skill in the art to understand the present invention. The present invention is defined by the category of the claims.
FIGS. 1A to 1G are sectional views showing a method of fabricating a flash memory device in accordance with an embodiment of the present invention.
Referring to FIG. 1A, a tunnel dielectric layer 102 and a first conductive layer 104 are formed over a semiconductor substrate 100. The tunnel dielectric layer 102 can be formed, for example, of a silicon oxide (SiO2) layer. In this embodiment, an oxidation process can be used to form the tunnel dielectric layer 102. The first conductive layer 104 can be used as a floating gate and can be formed, for example, of a polysilicon layer, a metal layer, or a stacked layer of them. Preferably, a polysilicon layer is used.
An etch process employing a mask (not shown) is performed to pattern the first conductive layer 104 and the tunnel dielectric layer 102 in the isolation region in one direction (a bit line direction), exposing the semiconductor substrate 100 in the isolation region. The semiconductor substrate 100 exposed in the isolation region is etched to a specific depth to form trenches (not shown).
An insulating layer is formed by depositing insulating material over the semiconductor substrate 100 including the trenches, such that the trenches are gap-filled. A polishing process is then performed to form isolation layers (not shown) in the trench regions. Thereafter, an additional etch process can be performed in order to control the Effective Field Oxide Height (EFH) of the isolation layers.
A dielectric layer 106, a barrier layer 108, a second conductive layer 110, and a hard mask 112 are sequentially formed over the semiconductor substrate 100 including the first conductive layer 104 and the isolation layers. The dielectric layer 106 can have, for example, an Oxide-Nitride-Oxide (ONO) stacked layer structure formed of a first oxide layer 106 a, a nitride layer 106 b, and a second oxide layer 106 c. The second conductive layer 110 can be used as a control gate and can be formed of a tungsten (W) layer, for example in order to implement a high-speed device and improve an interference phenomenon between neighboring cells. The barrier layer 108 is to be used as a barrier for forming the second conductive layer 110 and can be formed, for example, of a tungsten nitride (WN) layer. In this embodiment, the barrier layer 108 and the second conductive layer 110 preferably are formed using a PVD method. After the barrier layer 108 is formed, the second conductive layer 110 can be formed in-situ.
The hard mask 112 can prevent etch damage to the second conductive layer 110 during a subsequent gate etch process. The hard mask 112 can be formed of material that does not react with the second conductive layer 110, e.g. a tungsten layer for a control gate, during annealing. For example, the hard mask 112 can be formed of silicon oxynitride (SiON).
Referring to FIG. 1B, the hard mask 112, the second conductive layer 110, and the barrier layer 108 are patterned in a direction crossing the isolation layers by performing an etch process employing a mask (not shown). The patterning may expose the dielectric layer 106. Thus, a control gate 110 a comprised of the second conductive layer 110 is formed. The control gates 110 a of cells formed in different strings are interconnected to form word lines. In the etch process, the hard mask 112 can also be etched to a specific thickness.
Referring to FIG. 1C, the exposed dielectric layer 106 is patterned by an etch process to expose the first conductive layer 104. Meanwhile, in the etch process, the first conductive layer 104 can also be partially etched.
An anti-oxidization layer 114 is formed on the first conductive layer 104 including the dielectric layer 106, the barrier layer 108, the control gate 110 a, and the hard mask 112. The anti-oxidization layer 114 can prevent abnormal oxidization of the control gate 110 a, which is caused by a reaction, during an annealing process, between the tungsten (W) of the control gate 110 a and the oxygen of a subsequently formed spacer having an oxide layer. The anti-oxidization layer 114 can be formed, for example, of a tungsten nitride (WN) layer.
The tungsten nitride (WN) layer can be formed, for example, using a CVD or PVD method. The anti-oxidization layer 114, e.g. a tungsten nitride layer can be formed to a thickness sufficient to remain on the sidewalls of the control gate 110 a to protect the control gates 110 a after a subsequent gate etch process is completed. For example, the anti-oxidization layer 114 can be deposited to a thickness in a range of 80 to 100 angstrom when the CVD method is used, and to a thickness in a range of 200 to 300 angstrom when the PVD method is used.
Referring to FIG. 1D, the first conductive layer 104 is patterned by performing an etch process using the anti-oxidization layer 114 as an etch mask to form a floating gate 104 a that includes the first conductive layer 104. The surface of the tunnel dielectric layer 102 can be exposed by the patterning. A gate pattern 116 that includes the tunnel dielectric layer 102, the floating gate 104 a, the dielectric layer 106, the barrier layer 108, the control gate 110 a, and the hard mask 112 is also formed.
In this embodiment, the anti-oxidization layer 114 preferably remains, in spacer form, on the sidewalls of the control gates 110 a while patterning the first conductive layer 104. The anti-oxidization layer 114 that remains on the sidewalls of the control gate 110 a can have a thickness in a range of 20 to 50 angstrom. The anti-oxidization layer 114 that remains on the sidewalls of the control gate 110 a can prevent abnormal oxidization of the control gate 110 a during a subsequent annealing process.
In the process of patterning the first conductive layer 104, the hard mask 112 can also be etched. The hard mask 112 partially remain in order to prohibit abnormal oxidization of the control gate 110 caused by a reaction, during an annealing process, between the tungsten (W) in the control gate 110 a and the oxygen of the subsequently formed spacer having an oxide layer.
Referring to FIG. 1E, a first insulating layer 118 for spacers is formed to have an overhang shape while surrounding a top surface of the gate pattern 116. The first insulating layer 118 can be formed to a thickness in a range of 300 to 500 angstrom. An air-gap 122 within a subsequently formed insulating layer between neighboring word lines can be formed by using a first insulating layer 118 formed of an insulating layer material having a poor gap-filling characteristic. The first insulating layer 118 can be formed, for example, of an O3-TEOS layer or a USG layer. In this embodiment, the first insulating layer 118 preferably is formed using a CVD method.
A deposition rate is faster at the top of the gate pattern 116 than at the semiconductor substrate 100 due to the material having a poor gap-filling characteristic. Hence, an overhang shape can be formed at the top of the first insulating layer 118 while the first insulating layer 118 is deposited. The overhang shape causes the first insulating layer 118 to have a negative slope, which can potentially degrade a subsequent gap-fill characteristic.
An insulating layer for spacers has to be additionally deposited subsequently. Thus, it is preferred that in order to secure a deposition entry, the overhang shape of the first insulating layer 118 formed on an element of the gate pattern 116 does not come in contact with an overhang shape of the first insulating layer 118 formed on an adjacent element of the gate pattern 116. The first insulating layer 118 can be formed to a thickness of 300 to 500 angstrom. However, when the overhang shapes come in contact with each other, the first insulating layer 118 can be partially etched by an additional etch process in order to partially remove the overhang shapes and open a deposition entry for deposition of a second insulating layer 120.
Referring to FIG. 1F, a second insulating layer 120 for spacers is formed by depositing an insulating material over the semiconductor substrate 100 including the first insulating layer 118 having the overhang shape. The second insulating layer 120 can be formed, for example, using an oxide layer, preferably, a HDP oxide layer employing a HDP method.
If the second insulating layer 120 is formed between the gate patterns 116 through the deposition entry narrowed by the overhang, an air-gap 122 is formed within the second insulating layer 120 between elements of the gate pattern 116. The air-gap 122 is formed between the first insulating layers 118 on sidewalls of neighboring floating gates 104 a.
In general, the dielectric constant of the oxide layer is approximately 4.2, whereas the dielectric constant of air is 1.0. Thus, if the air-gap 122 having a low dielectric constant of 1.0 is formed between the gate patterns 116 (for example, the floating gate 104 a and the word line), interference capacitance between neighboring word lines is reduced and, therefore, an interference effect between neighboring word lines can be improved.
A subsequent fabrication process of a flash memory device generally includes an annealing process performed at high temperature. In this embodiment, the annealing process is preferably performed after the second insulating layer 120 is formed or subsequent other processes are performed. The flash memory device after the annealing process is completed is described below with reference to the accompanying drawings.
Referring to FIG. 1G, the flash memory device having the structure as shown in FIG. 1F can prevent abnormal oxidization of the control gate 110 a by preventing a reaction, during the annealing process, between the tungsten (W) in the control gate 110 a and the oxygen in the first insulating layer 118. Diffusion of nitrogen (N2) within the anti-oxidization layer 114 to the outside during the annealing performed at a high temperature of 700 to 1000 degrees Celsius can prevent the abnormal oxidization of the control gate 110 a. Consequently, the reliability of the device can be improved and a robust device can be implemented.
Further, as nitrogen (N2) within the anti-oxidization layer 114 and the barrier layer 108 is diffused to the outside during the annealing process, the anti-oxidization layer 114 and the barrier layer 108 can be changed into a tungsten (W) layer. Accordingly, a final control gate 110 b that is formed after the annealing process has an increased cross section occupied by the tungsten (W) layer, which can aid in implementing a high-speed device.
As described above, in accordance with an embodiment of the present invention, the air-gap having a low dielectric constant is formed within the oxide layer for spacers between the word lines and the floating gates, so interference between neighboring word lines can be improved. Accordingly, a high-speed device can be implemented.
Further, the tungsten nitride (WN) layer is formed on the sidewalls of the tungsten (W) layer for the control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. Accordingly, the reliability of a device can be improved and a robust high-speed device can be implemented.
Further, when forming the barrier layer using the tungsten nitride (WN) layer below the tungsten (W) layer for the control gate, the tungsten nitride (WN) layer is changed into the tungsten layer in a subsequent annealing process. Accordingly, the cross section of the control gate that is finally formed can be increased. Accordingly, a higher-speed device can be implemented.
The embodiments disclosed herein have been proposed to allow a person skilled in the art to easily implement the present invention, and the person skilled in the part may implement the present invention by a combination of these embodiments. Therefore, the scope of the present invention is not limited by or to the disclosed embodiments, but can be implemented in various manners. The present invention is defined only by the appended claims and their equivalents.

Claims (20)

1. A method of fabricating a flash memory device, comprising:
providing a semiconductor substrate in which a tunnel dielectric layer, a first conductive layer, a dielectric layer, and a second conductive layer are formed;
patterning the second conductive layer and the dielectric layer;
forming an anti-oxidization layer over the first conductive layer, including the patterned second conductive layer and the patterned dielectric layer;
etching the anti-oxidization layer, while etching the first conductive layer, in such a manner that the anti-oxidization layer remains on sidewalls of the second conductive layer and the first conductive layer is patterned;
forming a first insulating layer surrounding each element of the remaining anti-oxidization layer and having a top with an overhang shape; and
forming a second insulating layer having an air-gap between the first insulating layer on sidewalls of adjacent elements of the patterned first conductive layer.
2. The method of claim 1, comprising forming the second conductive layer of a tungsten (W) layer.
3. The method of claim 1, comprising forming the anti-oxidization layer of a tungsten nitride (WN) layer.
4. The method of claim 3, comprising forming the anti-oxidization layer using a Chemical Vapor Deposition (CVD) or a Physical Vapor Deposition (PVD) method.
5. The method of claim 4, comprising forming the anti-oxidization layer to a thickness in a range of 80 to 100 angstrom using a CVD method.
6. The method of claim 4, comprising forming the anti-oxidization layer to a thickness in a range of 200 to 300 angstrom using a PVD method.
7. The method of claim 1, comprising etching the anti-oxidization layer in such a manner that it remains at a thickness in a range of 20 to 50 angstrom on the sidewalls of the second conductive layer.
8. The method of claim 1, comprising forming the first insulating layer of an insulating layer material having a poor gap-filling characteristic.
9. The method of claim 8, wherein the first insulating layer material having a poor gap-filling characteristic includes an O3-TEOS (Tetra Ortho Silicate Glass) layer or a USG (Undoped Silicate Glass) layer.
10. The method of claim 8, comprising forming the first insulating layer to a thickness in a range of 300 to 500 angstrom using a CVD method.
11. The method of claim 1, comprising forming the second insulating layer of a High Density Plasma (HDP) oxide layer.
12. The method of claim 1, wherein the overhang shape formed on an element of the remaining anti-oxidization layer comes in contact with an overhang shape formed on an adjacent element of the remaining anti-oxidization layer when the first insulating layer is formed, and further comprising performing an additional etch process in order to partially remove a portion of the overhang shapes.
13. The method of claim 1, further comprising forming a barrier layer on the dielectric layer before forming the second conductive layer.
14. The method of claim 13, comprising forming the barrier layer of a tungsten nitride (WN) layer.
15. The method of claim 1, further comprising forming a hard mask on the second conductive layer before patterning the second conductive layer.
16. The method of claim 15, comprising forming the hard mask of a material that does not react with the second conductive layer during annealing.
17. The method of claim 15, comprising patterning the first conductive layer in such a manner that the hard mask partially remains.
18. The method of claim 1, further comprising performing an annealing process after forming the second insulating layer.
19. The method of claim 18, further comprising forming a barrier layer on the dielectric layer before forming the second conductive layer, wherein the barrier layer is formed of a tungsten nitride (WN) layer; and
forming the anti-oxidization layer of a tungsten nitride (WN) layer.
20. The method of claim 19, further comprising changing the tungsten nitride (WN) layer of the anti-oxidization layer and the barrier layer that remain after the annealing process is completed into a tungsten layer, so a cross section of the second conductive layer is increased.
US12/131,626 2007-07-18 2008-06-02 Method of fabricating flash memory device Expired - Fee Related US7682904B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2007-0071643 2007-07-18
KR1020070071643A KR101010798B1 (en) 2007-07-18 2007-07-18 Manufacturing Method of Flash Memory Device

Publications (2)

Publication Number Publication Date
US20090023279A1 US20090023279A1 (en) 2009-01-22
US7682904B2 true US7682904B2 (en) 2010-03-23

Family

ID=40265176

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/131,626 Expired - Fee Related US7682904B2 (en) 2007-07-18 2008-06-02 Method of fabricating flash memory device

Country Status (3)

Country Link
US (1) US7682904B2 (en)
JP (1) JP2009027161A (en)
KR (1) KR101010798B1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090289296A1 (en) * 2008-05-26 2009-11-26 Hynix Semiconductor Inc. Semiconductor Device and Method of Fabricating the same
US8575680B2 (en) 2011-08-02 2013-11-05 Samsung Electronics Co., Ltd. Semiconductor device having air gap and method of fabricating the same
US8765572B2 (en) 2010-06-25 2014-07-01 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US20150021678A1 (en) * 2012-03-23 2015-01-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US8975684B2 (en) 2012-07-18 2015-03-10 Samsung Electronics Co., Ltd. Methods of forming non-volatile memory devices having air gaps
US9171781B2 (en) 2013-02-13 2015-10-27 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US9337208B2 (en) * 2014-09-24 2016-05-10 Macronix International Co., Ltd. Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same
US9391269B2 (en) 2014-01-29 2016-07-12 Samsung Electronics Co., Ltd. Variable resistance memory devices
US9450025B2 (en) 2014-08-14 2016-09-20 Samsung Electronics Co., Ltd. Resistive memory device and method of operating resistive memory device
US10381366B1 (en) 2018-02-17 2019-08-13 Sandisk Technologies Llc Air gap three-dimensional cross rail memory device and method of making thereof

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302116A (en) * 2008-06-10 2009-12-24 Toshiba Corp Semiconductor device and method of fabricating it
JP5377052B2 (en) * 2009-04-17 2013-12-25 株式会社東芝 Manufacturing method of semiconductor device
US8211762B1 (en) 2009-07-30 2012-07-03 Micron Technology, Inc. Non-volatile memory
KR20120027906A (en) * 2010-09-14 2012-03-22 삼성전자주식회사 Semiconductor devices and methods of manufacturing semiconductor devices
US8575000B2 (en) 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
JP2013197187A (en) * 2012-03-16 2013-09-30 Toshiba Corp Semiconductor device and method for manufacturing the same
KR102054264B1 (en) 2012-09-21 2019-12-10 삼성전자주식회사 Semiconductor device and method of fabricating the same
US9153455B2 (en) * 2013-06-19 2015-10-06 Micron Technology, Inc. Methods of forming semiconductor device structures, memory cells, and arrays
KR102039708B1 (en) * 2013-11-13 2019-11-01 삼성전자주식회사 Non-volatile memory device and manufacturing the same
US9362355B1 (en) * 2015-11-13 2016-06-07 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer
US9728447B2 (en) 2015-11-16 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-barrier deposition for air gap formation
CN109427798A (en) * 2017-08-28 2019-03-05 中芯国际集成电路制造(上海)有限公司 Flush memory device and its manufacturing method
CN110880475B (en) * 2018-09-06 2023-06-16 长鑫存储技术有限公司 Air gap forming method
US11011638B2 (en) * 2019-08-26 2021-05-18 International Business Machines Corporation Transistor having airgap spacer around gate structure
US11233136B2 (en) 2019-12-20 2022-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon carbide oxide hard mask for reducing dishing effects

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5880008A (en) * 1995-10-18 1999-03-09 Sharp Kabushiki Kaisha Method for forming field oxide film
US20040238847A1 (en) * 2001-12-25 2004-12-02 Kikuko Sugimae Semiconductor device and manufacturing method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04364723A (en) * 1991-06-12 1992-12-17 Kawasaki Steel Corp Semiconductor device and manufacture thereof
JP2000100976A (en) * 1998-09-21 2000-04-07 Matsushita Electronics Industry Corp Semiconductor memory device and manufacture thereof
JP2001326289A (en) * 2000-03-08 2001-11-22 Semiconductor Energy Lab Co Ltd Nonvolatile memory and semiconductor device
US7045849B2 (en) * 2003-05-21 2006-05-16 Sandisk Corporation Use of voids between elements in semiconductor structures for isolation
JP2005044844A (en) * 2003-07-23 2005-02-17 Toshiba Corp Nonvolatile semiconductor memory device and manufacturing method thereof
JP4322150B2 (en) * 2004-03-15 2009-08-26 富士通マイクロエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2006302950A (en) * 2005-04-15 2006-11-02 Renesas Technology Corp Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device
KR20060133166A (en) * 2005-06-20 2006-12-26 삼성전자주식회사 Gate forming method of nonvolatile memory device
JP4731262B2 (en) 2005-09-22 2011-07-20 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5880008A (en) * 1995-10-18 1999-03-09 Sharp Kabushiki Kaisha Method for forming field oxide film
US20040238847A1 (en) * 2001-12-25 2004-12-02 Kikuko Sugimae Semiconductor device and manufacturing method

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090289296A1 (en) * 2008-05-26 2009-11-26 Hynix Semiconductor Inc. Semiconductor Device and Method of Fabricating the same
US8097507B2 (en) * 2008-05-26 2012-01-17 Hynix Semiconductor Inc. Method of fabricating a semiconductor device
US8765572B2 (en) 2010-06-25 2014-07-01 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US8575680B2 (en) 2011-08-02 2013-11-05 Samsung Electronics Co., Ltd. Semiconductor device having air gap and method of fabricating the same
US20150021678A1 (en) * 2012-03-23 2015-01-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US9041088B2 (en) 2012-07-18 2015-05-26 Samsung Electronics Co., Ltd. Non-volatile memory devices having air gaps and methods of manufacturing the same
US8975684B2 (en) 2012-07-18 2015-03-10 Samsung Electronics Co., Ltd. Methods of forming non-volatile memory devices having air gaps
US9773795B2 (en) 2012-07-18 2017-09-26 Samsung Electronics Co., Ltd. Semiconductor devices having airgaps and methods of manufacturing the same
US9171781B2 (en) 2013-02-13 2015-10-27 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US9391269B2 (en) 2014-01-29 2016-07-12 Samsung Electronics Co., Ltd. Variable resistance memory devices
US9450025B2 (en) 2014-08-14 2016-09-20 Samsung Electronics Co., Ltd. Resistive memory device and method of operating resistive memory device
US9337208B2 (en) * 2014-09-24 2016-05-10 Macronix International Co., Ltd. Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same
US10381366B1 (en) 2018-02-17 2019-08-13 Sandisk Technologies Llc Air gap three-dimensional cross rail memory device and method of making thereof

Also Published As

Publication number Publication date
US20090023279A1 (en) 2009-01-22
KR20090008582A (en) 2009-01-22
KR101010798B1 (en) 2011-01-25
JP2009027161A (en) 2009-02-05

Similar Documents

Publication Publication Date Title
US7682904B2 (en) Method of fabricating flash memory device
US6548374B2 (en) Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device comprising the same
US7629213B2 (en) Method of manufacturing flash memory device with void between gate patterns
US8629035B2 (en) Method of manufacturing semiconductor device
US20110204430A1 (en) Nonvolatile memory device and method of fabricating the same
KR101060618B1 (en) Charge trap type nonvolatile memory device and manufacturing method thereof
US8952536B2 (en) Semiconductor device and method of fabrication
US7932159B2 (en) Flash memory device and method of fabricating the same
US7611964B2 (en) Method of forming isolation layer of semiconductor memory device
JP2008091614A (en) Semiconductor device and manufacturing method thereof
JP2008513991A (en) SONOS memory device with optimized shallow trench isolation
US20070102752A1 (en) Flash memory device and method of fabricating the same
JP3745297B2 (en) Method for manufacturing nonvolatile semiconductor memory device
US20090283818A1 (en) Flash Memory Device and Method of Fabricating the Same
US9337353B2 (en) Semiconductor device and method for fabricating the same
US20120126304A1 (en) Floating gate type semiconductor memory device and method of manufacturing the same
KR101034407B1 (en) Nonvolatile Memory Device and Manufacturing Method Thereof
KR100771553B1 (en) A buried nonvolatile memory device having a charge trap layer and a manufacturing method thereof
KR20090037165A (en) Manufacturing Method of Semiconductor Device
KR100622030B1 (en) Manufacturing method of nonvolatile memory device
KR100602938B1 (en) Manufacturing method of nonvolatile memory device
KR100996367B1 (en) Semiconductor device
KR20100013939A (en) Flash memory device and manufacturing method thereof
KR20070078274A (en) Nonvolatile Memory Device and Manufacturing Method Thereof
JP2007150068A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, EUN SOO;KIM, JUNG GEUN;KIM, SUK JOONG;REEL/FRAME:021034/0636

Effective date: 20080523

Owner name: HYNIX SEMICONDUCTOR INC.,KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, EUN SOO;KIM, JUNG GEUN;KIM, SUK JOONG;REEL/FRAME:021034/0636

Effective date: 20080523

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140323