US7545216B2 - Amplifier with current mirror bias adjust - Google Patents

Amplifier with current mirror bias adjust Download PDF

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US7545216B2
US7545216B2 US12/001,053 US105307A US7545216B2 US 7545216 B2 US7545216 B2 US 7545216B2 US 105307 A US105307 A US 105307A US 7545216 B2 US7545216 B2 US 7545216B2
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amplifier
current
bias
control
stage
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James Pearce Hamley
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45278—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using BiFET transistors as the active amplifying circuit
    • H03F3/45282—Long tailed pairs
    • H03F3/45286—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/4578—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with BiFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45244—Indexing scheme relating to differential amplifiers the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45304—Indexing scheme relating to differential amplifiers the common gate stage of a BIFET cascode dif amp being implemented fully by FETs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45476—Indexing scheme relating to differential amplifiers the CSC comprising a mirror circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45626—Indexing scheme relating to differential amplifiers the LC comprising biasing means controlled by the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45641—Indexing scheme relating to differential amplifiers the LC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45681—Indexing scheme relating to differential amplifiers the LC comprising offset compensating means

Definitions

  • FIG. 1 is a detailed schematic diagram of a power amplifier.
  • the amplifier is comprised of three stages:
  • the differential amplifier stage 10 receives an input signal to-be-amplified at input terminal 11 and, after a slight voltage divider comprised of R 0 and R 1 , passes the input signal to the gate, 12 , of Q 1 a , which is a matched FET dual to transistor Q 1 b .
  • Received at gate 14 of Q 1 b is the voltage divided signal, via resistors R 20 (with parallel compensation capacitor C 1 ), and R 22 at the amplifier output terminal 31 .
  • the sources of Q 1 a and Q 1 b are connected to source resistors R 7 and R 8 , respectively, which, in turn connect to a DC bias offset potentiometer POT 1 .
  • the wiper of POT 1 connects through a resistor R 23 to the collector of a matched transistor quad Q 3 a -Q 3 d .
  • transistors Q 3 a -Q 3 d are interconnected to form a current mirror, with the emitters of Q 3 c and Q 3 d connected to a source of negative bias voltage, B ⁇ .
  • the collector of Q 3 b connects through resistor R 9 to a source of positive bias voltage, B++.
  • the current through R 9 is determine by the difference between B++ and B ⁇ , minus the base to emitter drops of Q 3 b and Q 3 d (approximately 1.4 volts) divided by the value of R 9 . Since the current in Q 3 a , Q 3 c will mirror the current through Q 3 b , Q 3 d , the constant current provided through R 23 to the Q 1 a , Q 1 b differential pair is established.
  • the drains of the differential pair Q 1 a , Q 1 b are connected to the emitters of cascode transistors Q 2 a , Q 2 b , respectively.
  • the bases of cascade transistors Q 2 a , Q 2 b are fixed biased by a voltage divider comprised of series connected resistors R 4 , R 6 , which connect between B++ and ground.
  • the collector of Q 2 a designated as point A, is connected through a collector resistor R 2 to the positive bias supply B++.
  • the collector of Q 2 b designated as point B, connects through a collector resistor R 3 to the positive bias supply B++.
  • the differential amplifier stage 10 produces differential output signals at points A and B representing the difference between the signal at the amplifier input 11 and the signal at the amplifier output 31 .
  • the differential signals at points A and B are fed to the bases 21 , 22 of transistor matched pair Q 5 a , Q 5 b respectively, which form the inputs to the voltage amplification stage 20 .
  • the emitters of Q 5 a , Q 5 b connect through resistors R 10 , R 11 , respectively, to a common point 23 .
  • Also connected to common point 23 is the collector of transistor Q 5 b , which is a matched pair to transistor Q 5 a .
  • the bases of Q 5 a and Q 5 b , as well as the collector of Q 5 a are connected in common at point 24 .
  • the emitters of Q 5 a , Q 5 b are connected to the respective collectors of transistor matched pair Q 4 a , Q 4 a .
  • Q 4 a,b and Q 5 a,b are all matched transistors.
  • the bases of Q 4 a and Q 4 b are connected in common with the collector of Q 4 a .
  • the emitters of Q 4 a and Q 4 b connect to the source of positive bias voltage B++.
  • Point 24 connects through a resistor R 9 to the collector of a control transistor 25 .
  • the emitter of control transistor 25 connects through a resistor R 27 to the negative bias source B ⁇ .
  • the base of transistor 25 is a control point 26 .
  • control circuitry monitors one or more parameters of the amplifier and provides a control signal to control point 26 to control the bias to the power output stage 30 .
  • a current mirror is formed whereby the controlled current out of point 24 will be mirrored as current flow into point 23 .
  • the current into point 23 then splits as current into Q 6 a and Q 6 b.
  • transistors Q 6 a and Q 6 b are matched transistor pair Q 7 a and Q 7 b , respectively.
  • the bases of transistor matched pair Q 7 a and Q 7 b are connected in common and fixed biased by a voltage divider comprised of resistors R 12 and R 13 which connect between the positive bias source B++ and ground.
  • the collectors of Q 7 a and Q 7 b connect through resistors R 14 and RB 1 , respectively, to the collectors of a matched transistor pair Q 8 a and Q 8 b , respectively.
  • the collector of Q 8 a connects to the common connection of the bases of Q 8 a and Q 8 b .
  • the emitters of Q 8 a and Q 8 b connect to the collectors of transistor matched pair Q 8 c and Q 8 d , respectively.
  • the bases of Q 8 c and Q 8 d are connected in common and to the collector of Q 8 d .
  • transistors Q 8 a -Q 8 d are all matched.
  • Transistors Q 8 a -Q 8 d connected as shown, form a precision current mirror whereby the current through R 14 , which is related to the signal out of point A, is mirrored as a current through bias resistor RB 1 .
  • the current through bias resistor RB 1 is also related to the signal at point B. In this way, the differential output from points A and B is reflected as a differential current signal through RB 1 .
  • a compensation capacitor C 2 Shown connected from the base of Q 6 a to the collector of Q 7 a is a compensation capacitor C 2 .
  • a compensation capacitor C 3 connects from the base of Q 6 b to the collector of Q 7 b .
  • the capacitors C 1 -C 3 are adjusted in the normal manner to compensate the amplifier.
  • bias resistor RB 1 As shown, the current through bias resistor RB 1 is designated Iref C and it produces a bias voltage Vref C across points 27 , 28 , which are at opposite ends of bias resistor RB 1 .
  • Point 27 represents the output points of the voltage amplification stage 20.
  • Point 27 connects to the bases of emitter follower transistors Q 15 , Q 16 .
  • the collectors of transistors Q 15 and Q 16 connect to a positive bias source B+ and a negative bias source B ⁇ , respectively.
  • the emitters of Q 15 and Q 16 are connected through a second bias resistor RB 2 , at points 32 and 33 , respectively.
  • Point 32 connects to the bases of three parallel output transistors Q 9 -Q 11 .
  • the collectors of Q 9 -Q 11 all connect to the positive bias source B+.
  • the emitters of transistor Q 9 -Q 11 connect through respective emitter resistors R 16 through R 18 to the amplifier output point 31 .
  • point 33 connects to the bases of three parallel output transistors Q 12 -Q 14 .
  • the collectors of Q 12 -Q 14 all connect to the negative bias source B ⁇ .
  • the emitters of transistor Q 12 -Q 14 connect through respective emitter resistors R 19 through R 21 to the amplifier output point 31 .
  • the voltage applied to the control point 26 creates a reference current Iref A through control transistor 25 . Due to the current mirror connection of Q 4 a , Q 4 b , Q 5 a and Q 5 b , a current Iref B is created into point 23 .
  • the current Iref A equals the current Iref B, although Iref B could be deigned to be a fraction, or a multiple of Iref A.
  • each leg (leg 1 and leg 2 ) will carry a current equal to one-half of Iref A. Since the bias of the output transistors Q 9 -Q 14 is directly controlled by the voltage across resistor RB 2 which, in turn, is controlled by the voltage across RB 1 , it can be seen that applying appropriate signals at the control point 26 is a convenient and precise way to control bias current (IbiasQ 9 -IbiasQ 14 ) of the output transistors Q 9 -Q 14 .
  • a servo circuit 40 comprises an operational amplifier having a non-inverting input 42 , an inverting input 43 and an output 44 .
  • a resistor R 25 connects the inverting input 43 to the emitter of Q 11 .
  • the inverting input 43 monitors the voltage Vref which is equal to the bias current through Q 11 , IbiasQ 11 , times the value of emitter resistor R 18 .
  • the voltage Vref is representative of each of the output transistor Q 9 -Q 14 bias currents, IbiasQ 9 -IbiasQ 14 .
  • a capacitor, C 4 connects from the inverting input 43 to the output 44 of operational amplifier 41 .
  • the value of capacitor C 4 along with the value of resistor R 25 are selected to form a low pass filter, so that the voltage appearing at the inverting input 43 is, essentially, the DC voltage across emitter resistor R 18 .
  • the operational amplifier 41 has an adjustable DC voltage applied at its non-inverting input 42 which is achieved by connecting the non-inverting input 42 to the wiper of a potentiometer POT 2 .
  • POT 2 has one free end connected to ground and the other free end connected through a dropping resistor R 24 to the positive bias source B+.
  • the values for POT 2 and R 24 are selected based upon the desired operating range of the output transistor Q 9 -Q 14 bias current.
  • the output 44 of operational amplifier 41 connects through resistor R 26 to the control point 26 , which is the base of control transistor 25 .
  • the emitter of control transistor 25 connects to the negative bias source B—through resistor R 27 .
  • POT 2 is adjusted to apply a voltage Vref to the non-inverting input 42 which is the desired bias voltage and corresponds to the desired bias current through the output transistor Q 11 .
  • Vref voltage
  • operational amplifier 41 produces a positive voltage at its output 44 , which will increase the voltage at control point 26 and increase the current Iref A through control transistor 25 .
  • An increasing I ref A will, as described above, produce an increasing I ref B and Iref C, thereby increasing the bias current IbiasQ 11 in output transistor Q 11 .
  • bias current IbiasQ 11 will continue to increase until the voltage at the inverting input 43 equals the voltage at the non-inverting input 42 of operational amplifier 41 such that operational amplifier 41 will produce a signal at its output 44 which, when applied to control terminal 25 will maintain the bias current through Q 11 , and, thus, all of the other output transistors at the desired bias level as set by POT 2 .
  • FIG. 2 illustrates an alternative use of the novel output bias scheme, indicated generally at 50 , according to the present invention.
  • the basic amplifier construction of FIG. 1 is assumed, minus the servo circuit 40 .
  • the differential signals from points A and B of FIG. 1 are fed to a differential amplifier 51 , which in turn connects to a precision full wave rectifier circuit 52 .
  • the output from precision full wave rectifier circuit 52 is a DC voltage having an instantaneous peak level representative of the instantaneous input signal to the amplifier at input 11 of FIG. 1 .
  • This instantaneous peak level is then processed through a scalar circuit 53 and applied as the control voltage to control point 26 of FIG. 1 .
  • the bias of the output stage 30 in FIG. 1 can be set to be biased in a dynamic class A mode.
  • dynamic class A mode it is meant that the bias current level of the output stage 30 can be at low levels when no signal is applied to the amplifier at input 11 , to thereby maintain low power dissipation.
  • the control circuit 50 of FIG. 2 is designed to track the peak level of an input signal applied at amplifier input 11 such that the output transistors Q 9 -Q 14 never turn completely off, thereby avoiding undesired crossover distortion.
  • control circuits which apply a control signal to the control point to control the bias of the power output stage of an amplifier.
  • the embodiment in FIG. 1 just senses bias current through output transistor Q 11
  • the desired control circuit could combine both the DC bias servo 40 of FIG. 1 with the dynamic class A bias control circuit of FIG. 2 to control both DC and dynamic bias of the output stage 30 .
  • Numerous other approaches to control circuitry will be obvious to those of ordinary skill in the art in view of the teaching set forth herein.

Abstract

An amplifier includes a differential amplifier stage, a voltage amplification stage and a power output stage. The bias level of the output stage is proportional to current through the voltage amplification stage. The voltage amplification stage includes a current mirror whereby controlled current through a first leg of the current mirror controls current through the remaining, second leg, which, in turn, determines the bias level of the power output stage. Control circuitry senses a parameter of the amplifier, such as DC bias or input signal level to generate a control signal which is applied to the first leg of the current mirror to thereby control bias level of the power output stage.

Description

REFERENCE TO PRIOR APPLICATION
The present application claims the benefit of U.S. provisional application Ser. No. 60/874,200 filed Dec. 12, 2006.
DETAILED DESCRIPTION
FIG. 1 is a detailed schematic diagram of a power amplifier. The amplifier is comprised of three stages:
    • A differential amplifier stage, indicated generally at 10
    • A voltage amplification stage, indicated generally at 20, and
    • A power output stage, indicated generally at 30.
The differential amplifier stage 10 receives an input signal to-be-amplified at input terminal 11 and, after a slight voltage divider comprised of R0 and R1, passes the input signal to the gate, 12, of Q1 a, which is a matched FET dual to transistor Q1 b. Received at gate 14 of Q1 b is the voltage divided signal, via resistors R20 (with parallel compensation capacitor C1), and R22 at the amplifier output terminal 31. The sources of Q1 a and Q1 b are connected to source resistors R7 and R8, respectively, which, in turn connect to a DC bias offset potentiometer POT1. The wiper of POT1 connects through a resistor R23 to the collector of a matched transistor quad Q3 a-Q3 d. As shown, transistors Q3 a-Q3 d are interconnected to form a current mirror, with the emitters of Q3 c and Q3 d connected to a source of negative bias voltage, B−−. The collector of Q3 b connects through resistor R9 to a source of positive bias voltage, B++. The current through R9 is determine by the difference between B++ and B−−, minus the base to emitter drops of Q3 b and Q3 d (approximately 1.4 volts) divided by the value of R9. Since the current in Q3 a, Q3 c will mirror the current through Q3 b, Q3 d, the constant current provided through R23 to the Q1 a, Q1 b differential pair is established.
The drains of the differential pair Q1 a, Q1 b are connected to the emitters of cascode transistors Q2 a, Q2 b, respectively. The bases of cascade transistors Q2 a, Q2 b are fixed biased by a voltage divider comprised of series connected resistors R4, R6, which connect between B++ and ground. The collector of Q2 a, designated as point A, is connected through a collector resistor R2 to the positive bias supply B++. The collector of Q2 b, designated as point B, connects through a collector resistor R3 to the positive bias supply B++.
Thus, the differential amplifier stage 10 produces differential output signals at points A and B representing the difference between the signal at the amplifier input 11 and the signal at the amplifier output 31.
The differential signals at points A and B are fed to the bases 21, 22 of transistor matched pair Q5 a, Q5 b respectively, which form the inputs to the voltage amplification stage 20. The emitters of Q5 a, Q5 b connect through resistors R10, R11, respectively, to a common point 23. Also connected to common point 23 is the collector of transistor Q5 b, which is a matched pair to transistor Q5 a. The bases of Q5 a and Q5 b, as well as the collector of Q5 a are connected in common at point 24. The emitters of Q5 a, Q5 b are connected to the respective collectors of transistor matched pair Q4 a, Q4 a. Preferably, Q4 a,b and Q5 a,b are all matched transistors. The bases of Q4 a and Q4 b are connected in common with the collector of Q4 a. The emitters of Q4 a and Q4 b connect to the source of positive bias voltage B++.
Point 24 connects through a resistor R9 to the collector of a control transistor 25. The emitter of control transistor 25 connects through a resistor R27 to the negative bias source B−−. The base of transistor 25 is a control point 26. As will be discussed more thoroughly herein below, control circuitry monitors one or more parameters of the amplifier and provides a control signal to control point 26 to control the bias to the power output stage 30.
As can be seen from the connections of Q4 a,b and Q5 a,b, a current mirror is formed whereby the controlled current out of point 24 will be mirrored as current flow into point 23. The current into point 23 then splits as current into Q6 a and Q6 b.
In cascode with transistors Q6 a and Q6 b are matched transistor pair Q7 a and Q7 b, respectively. The bases of transistor matched pair Q7 a and Q7 b are connected in common and fixed biased by a voltage divider comprised of resistors R12 and R13 which connect between the positive bias source B++ and ground.
The collectors of Q7 a and Q7 b connect through resistors R14 and RB1, respectively, to the collectors of a matched transistor pair Q8 a and Q8 b, respectively. The collector of Q8 a connects to the common connection of the bases of Q8 a and Q8 b. The emitters of Q8 a and Q8 b connect to the collectors of transistor matched pair Q8 c and Q8 d, respectively. The bases of Q8 c and Q8 d are connected in common and to the collector of Q8 d. Preferably, transistors Q8 a-Q8 d are all matched. Transistors Q8 a-Q8 d, connected as shown, form a precision current mirror whereby the current through R14, which is related to the signal out of point A, is mirrored as a current through bias resistor RB1. The current through bias resistor RB1 is also related to the signal at point B. In this way, the differential output from points A and B is reflected as a differential current signal through RB1.
Shown connected from the base of Q6 a to the collector of Q7 a is a compensation capacitor C2. Similarly, a compensation capacitor C3 connects from the base of Q6 b to the collector of Q7 b. The capacitors C1-C3 are adjusted in the normal manner to compensate the amplifier.
As shown, the current through bias resistor RB1 is designated Iref C and it produces a bias voltage Vref C across points 27, 28, which are at opposite ends of bias resistor RB1.
The points 27, 28 represent the output points of the voltage amplification stage 20. Point 27 connects to the bases of emitter follower transistors Q15, Q16. The collectors of transistors Q15 and Q16 connect to a positive bias source B+ and a negative bias source B−, respectively. The emitters of Q15 and Q16 are connected through a second bias resistor RB2, at points 32 and 33, respectively.
Point 32 connects to the bases of three parallel output transistors Q9-Q11. The collectors of Q9-Q11 all connect to the positive bias source B+. The emitters of transistor Q9-Q11 connect through respective emitter resistors R16 through R18 to the amplifier output point 31.
Similarly, point 33 connects to the bases of three parallel output transistors Q12-Q14. The collectors of Q12-Q14 all connect to the negative bias source B−. The emitters of transistor Q12-Q14 connect through respective emitter resistors R19 through R21 to the amplifier output point 31.
In operation, the voltage applied to the control point 26 creates a reference current Iref A through control transistor 25. Due to the current mirror connection of Q4 a, Q4 b, Q5 a and Q5 b, a current Iref B is created into point 23. In this, the preferred embodiment of the invention, the current Iref A equals the current Iref B, although Iref B could be deigned to be a fraction, or a multiple of Iref A.
Now, the current Iref B splits between the first leg (leg 1) and the second leg (leg 2) of the voltage amplification stage 20. In general, each leg (leg 1 and leg 2) will carry a current equal to one-half of Iref A. Since the bias of the output transistors Q9-Q14 is directly controlled by the voltage across resistor RB2 which, in turn, is controlled by the voltage across RB1, it can be seen that applying appropriate signals at the control point 26 is a convenient and precise way to control bias current (IbiasQ9-IbiasQ14) of the output transistors Q9-Q14.
While many control circuits could be devised to control output transistor bias current in an advantageous manner, one specific example is illustrated in FIG. 1. Here, a servo circuit 40 comprises an operational amplifier having a non-inverting input 42, an inverting input 43 and an output 44. A resistor R25 connects the inverting input 43 to the emitter of Q11. In this way, the inverting input 43 monitors the voltage Vref which is equal to the bias current through Q11, IbiasQ11, times the value of emitter resistor R18. Assuming a reasonable match of the output transistors Q9-Q14, as further improved by the emitter resistors R16-R21, the voltage Vref is representative of each of the output transistor Q9-Q14 bias currents, IbiasQ9-IbiasQ14.
It is clearly advantageous to be able to control the DC bias levels in the power output stages of an amplifier to minimize distortion, prevent thermal runaway, manage heat dissipation, etc.
A capacitor, C4, connects from the inverting input 43 to the output 44 of operational amplifier 41. The value of capacitor C4 along with the value of resistor R25 are selected to form a low pass filter, so that the voltage appearing at the inverting input 43 is, essentially, the DC voltage across emitter resistor R18.
The operational amplifier 41 has an adjustable DC voltage applied at its non-inverting input 42 which is achieved by connecting the non-inverting input 42 to the wiper of a potentiometer POT2. POT2 has one free end connected to ground and the other free end connected through a dropping resistor R24 to the positive bias source B+. The values for POT2 and R24 are selected based upon the desired operating range of the output transistor Q9-Q14 bias current.
The output 44 of operational amplifier 41 connects through resistor R26 to the control point 26, which is the base of control transistor 25. The emitter of control transistor 25 connects to the negative bias source B—through resistor R27.
In operation, POT2 is adjusted to apply a voltage Vref to the non-inverting input 42 which is the desired bias voltage and corresponds to the desired bias current through the output transistor Q11. When the amplifier is first turned on, a positive voltage will appear at the non-inverting input 42 of operational amplifier 41. This will result in operational amplifier 41 producing a positive voltage at its output 44, which will increase the voltage at control point 26 and increase the current Iref A through control transistor 25. An increasing I ref A will, as described above, produce an increasing I ref B and Iref C, thereby increasing the bias current IbiasQ11 in output transistor Q11. The bias current IbiasQ11 will continue to increase until the voltage at the inverting input 43 equals the voltage at the non-inverting input 42 of operational amplifier 41 such that operational amplifier 41 will produce a signal at its output 44 which, when applied to control terminal 25 will maintain the bias current through Q11, and, thus, all of the other output transistors at the desired bias level as set by POT2.
FIG. 2 illustrates an alternative use of the novel output bias scheme, indicated generally at 50, according to the present invention. Here, the basic amplifier construction of FIG. 1 is assumed, minus the servo circuit 40. The differential signals from points A and B of FIG. 1 are fed to a differential amplifier 51, which in turn connects to a precision full wave rectifier circuit 52. Thus, the output from precision full wave rectifier circuit 52 is a DC voltage having an instantaneous peak level representative of the instantaneous input signal to the amplifier at input 11 of FIG. 1. This instantaneous peak level is then processed through a scalar circuit 53 and applied as the control voltage to control point 26 of FIG. 1.
By appropriate design of the differential amplifier 51, precision full wave rectifier 52 and scalar 53, the bias of the output stage 30 in FIG. 1 can be set to be biased in a dynamic class A mode. By “dynamic class A mode”, it is meant that the bias current level of the output stage 30 can be at low levels when no signal is applied to the amplifier at input 11, to thereby maintain low power dissipation. However, the control circuit 50 of FIG. 2 is designed to track the peak level of an input signal applied at amplifier input 11 such that the output transistors Q9-Q14 never turn completely off, thereby avoiding undesired crossover distortion.
There are numerous other ways to configure control circuits which apply a control signal to the control point to control the bias of the power output stage of an amplifier. For example, whereas the embodiment in FIG. 1 just senses bias current through output transistor Q11, it is well within the scope of this invention to use a conventional summing circuit, with inverters as appropriate, to monitor the bias current through all of the output transistors Q9-Q14 and thereby produce the control signal. In addition, the desired control circuit could combine both the DC bias servo 40 of FIG. 1 with the dynamic class A bias control circuit of FIG. 2 to control both DC and dynamic bias of the output stage 30. Numerous other approaches to control circuitry will be obvious to those of ordinary skill in the art in view of the teaching set forth herein.

Claims (3)

1. An amplifier including:
a differential amplifier stage,
a voltage amplification stage, and
a power output stage,
wherein:
a) the bias level of the output stage is proportional to current through the voltage amplification stage, and
b) the voltage amplification stage includes a current mirror whereby controlled current through a first leg of the current mirror controls current through the remaining, second leg, which, in turn, determines the bias level of the power output stage,
the amplifier further including control circuitry for sensing a parameter of the amplifier to generate a control signal which is applied to the first leg of the current mirror to thereby control bias level of the power output stage.
2. The amplifier of claim 1 wherein the control circuitry senses DC bias of the power output stage to generate a control signal which is applied to the first leg of the current mirror to thereby control bias level of the power output stage.
3. The amplifier of claim 1 wherein the control circuitry senses input signal level to generate a control signal which is applied to the first leg of the current mirror to thereby control bias level of the power output stage.
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* Cited by examiner, † Cited by third party
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US20110110137A1 (en) * 2009-06-03 2011-05-12 Jaroslaw Adamski Leakage Current Reduction in a Power Regulator
US20110181360A1 (en) * 2010-01-25 2011-07-28 Yang Edward Li Stacked linear power amplifier with capacitor feedback and resistor isolation
US20120049956A1 (en) * 2010-09-01 2012-03-01 Fleming Lam Amplifiers and related biasing methods and devices
RU2455757C1 (en) * 2011-03-11 2012-07-10 Государственное образовательное учреждение высшего профессионального образования "Южно-Российский государственный университет экономики и сервиса" (ГОУ ВПО "ЮРГУЭС") Precision operational amplifier
US8368462B2 (en) 2010-10-06 2013-02-05 Peregrine Semiconductor Corporation Method, system, and apparatus for RF switching amplifier
US8373490B2 (en) 2010-10-27 2013-02-12 Peregrine Semiconductor Corporation Method, system, and apparatus for RF and DC switching
US8559907B2 (en) 2004-06-23 2013-10-15 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US9264053B2 (en) 2011-01-18 2016-02-16 Peregrine Semiconductor Corporation Variable frequency charge pump
US9960737B1 (en) 2017-03-06 2018-05-01 Psemi Corporation Stacked PA power control

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114221628A (en) * 2021-12-13 2022-03-22 深圳飞骧科技股份有限公司 Power amplifier power regulating circuit and power amplifier

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642078A (en) * 1995-09-29 1997-06-24 Crystal Semiconductor Corporation Amplifier having frequency compensation by gain degeneration
US6215357B1 (en) * 1997-09-03 2001-04-10 Canon Kabushiki Kaisha Operational amplifier
US6377085B1 (en) * 2000-11-06 2002-04-23 Oki Semiconductor Precision bias for an transconductor
US7123095B2 (en) * 2004-02-12 2006-10-17 Renesas Technology Corp. High frequency power amplifier circuit and radio communication system
US7271662B2 (en) * 2004-09-24 2007-09-18 Renesas Technology Corporation High frequency power amplifier circuit and electric component for high frequency power amplifier
US7368992B2 (en) * 2004-02-18 2008-05-06 Peter Sandquist Load-invariant amplifier

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642078A (en) * 1995-09-29 1997-06-24 Crystal Semiconductor Corporation Amplifier having frequency compensation by gain degeneration
US6215357B1 (en) * 1997-09-03 2001-04-10 Canon Kabushiki Kaisha Operational amplifier
US6377085B1 (en) * 2000-11-06 2002-04-23 Oki Semiconductor Precision bias for an transconductor
US7123095B2 (en) * 2004-02-12 2006-10-17 Renesas Technology Corp. High frequency power amplifier circuit and radio communication system
US7368992B2 (en) * 2004-02-18 2008-05-06 Peter Sandquist Load-invariant amplifier
US7271662B2 (en) * 2004-09-24 2007-09-18 Renesas Technology Corporation High frequency power amplifier circuit and electric component for high frequency power amplifier

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9369087B2 (en) 2004-06-23 2016-06-14 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US11588513B2 (en) 2004-06-23 2023-02-21 Psemi Corporation Integrated RF front end with stacked transistor switch
US8649754B2 (en) 2004-06-23 2014-02-11 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US10715200B2 (en) 2004-06-23 2020-07-14 Psemi Corporation Integrated RF front end with stacked transistor switch
US9680416B2 (en) 2004-06-23 2017-06-13 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US11070244B2 (en) 2004-06-23 2021-07-20 Psemi Corporation Integrated RF front end with stacked transistor switch
US8559907B2 (en) 2004-06-23 2013-10-15 Peregrine Semiconductor Corporation Integrated RF front end with stacked transistor switch
US20110110137A1 (en) * 2009-06-03 2011-05-12 Jaroslaw Adamski Leakage Current Reduction in a Power Regulator
US8502607B2 (en) 2009-06-03 2013-08-06 Peregrine Semiconductor Corporation Leakage current reduction in a power regulator
US20110181360A1 (en) * 2010-01-25 2011-07-28 Yang Edward Li Stacked linear power amplifier with capacitor feedback and resistor isolation
US8487706B2 (en) 2010-01-25 2013-07-16 Peregrine Semiconductor Corporation Stacked linear power amplifier with capacitor feedback and resistor isolation
US8350624B2 (en) * 2010-09-01 2013-01-08 Peregrine Semiconductor Corporation Amplifiers and related biasing methods and devices
US20120049956A1 (en) * 2010-09-01 2012-03-01 Fleming Lam Amplifiers and related biasing methods and devices
US9509263B2 (en) 2010-09-01 2016-11-29 Peregrine Semiconductor Corporation Amplifiers and related biasing methods and devices
US8970303B2 (en) 2010-09-01 2015-03-03 Peregrine Semiconductor Corporation Amplifiers and related biasing methods and devices
US8368462B2 (en) 2010-10-06 2013-02-05 Peregrine Semiconductor Corporation Method, system, and apparatus for RF switching amplifier
US9331738B2 (en) 2010-10-06 2016-05-03 Peregrine Semiconductor Corporation Method, system, and apparatus for RF switching amplifier
US9000841B2 (en) 2010-10-06 2015-04-07 Peregrine Semiconductor Corporation Method, system, and apparatus for RF switching amplifier
US8373490B2 (en) 2010-10-27 2013-02-12 Peregrine Semiconductor Corporation Method, system, and apparatus for RF and DC switching
US9413362B2 (en) 2011-01-18 2016-08-09 Peregrine Semiconductor Corporation Differential charge pump
US9264053B2 (en) 2011-01-18 2016-02-16 Peregrine Semiconductor Corporation Variable frequency charge pump
RU2455757C1 (en) * 2011-03-11 2012-07-10 Государственное образовательное учреждение высшего профессионального образования "Южно-Российский государственный университет экономики и сервиса" (ГОУ ВПО "ЮРГУЭС") Precision operational amplifier
US9960737B1 (en) 2017-03-06 2018-05-01 Psemi Corporation Stacked PA power control

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