US7518909B2 - Non-volatile memory device adapted to reduce coupling effect between storage elements and related methods - Google Patents

Non-volatile memory device adapted to reduce coupling effect between storage elements and related methods Download PDF

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US7518909B2
US7518909B2 US11/606,908 US60690806A US7518909B2 US 7518909 B2 US7518909 B2 US 7518909B2 US 60690806 A US60690806 A US 60690806A US 7518909 B2 US7518909 B2 US 7518909B2
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memory array
bit lines
memory
data storage
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US20080084746A1 (en
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Ki-tae Park
Ki-nam Kim
Yeong-Taek Lee
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Definitions

  • Embodiments of the invention relate generally to non-volatile memory devices. More particularly, embodiments of the invention relate to technologies adapted to reduce a coupling effect between storage elements in the non-volatile memory devices.
  • FIG. 1 is a block diagram of a conventional memory array 10 including a plurality of sub-memory arrays.
  • memory array 10 includes a plurality of sub-memory arrays including a first sub-memory array 11 , a second sub-memory array 13 , and a plurality of strapping lines 12 formed in a bit line direction (or a column direction) between adjacent sub-memory arrays.
  • Each of sub-memory arrays 11 and 13 includes a plurality of even bit lines and a plurality of odd bit lines.
  • FIG. 2 is a block diagram of a non-volatile memory device 20 including memory array 10 illustrated in FIG. 1 .
  • non-volatile memory device 20 includes memory array 10 , a row decoder 12 , a control signal generation circuit 14 , a switching block 16 , and a page buffer 18 .
  • Sub-memory array 11 in memory array 10 includes even bit lines BLe 1 and BLe 2 and odd bit lines BLo 1 and BLo 2 .
  • sub-memory array 13 in memory array 10 includes even bit lines BLe 1 ′ and BLe 2 ′ and odd bit lines BLo 1 ′ and BLo 2 ′.
  • Cell strings 15 are respectively connected with even bit lines BLe 1 , BLe 2 , BLe 1 ′ and BLe 2 ′ and odd bit lines BLo 1 and BLo 2 , BLo 1 ′, and BLo 2 ′.
  • Each of cell strings 15 typically comprises a NAND string.
  • Each of cell strings 15 includes a first selection transistor, a second selection transistor, and a plurality of NAND flash electrically erasable and programmable read only memory (EEPROM) cells connected in series between the first and second selection transistors.
  • EEPROM electrically erasable and programmable read only memory
  • memory cells connected to even bit lines may be referred to throughout this written description as “even memory cells” and memory cells connected to odd bit lines may be referred to as “odd memory cells.”
  • Each NAND flash EEPROM cell included in each cell string 15 is formed in a P-type region or an N-type region.
  • the P-type region is typically formed within an N-type well formed in a P-type substrate and the N-type region is typically formed within a P-type well formed in an N-type substrate.
  • Strapping lines 12 include a strapping line for applying a voltage to the P-type region (or the N-type region), a strapping line for applying a voltage to a common source line, a bit line connected with dummy memory cells, and a strapping line for contacts.
  • Each of strapping lines 12 is typically formed with a structure similar to bit lines connected with respective cell strings 15 .
  • the memory cells illustrated in memory array 10 are multi-level cells.
  • the memory cells can be programmed to store more than one bit of data by adjusting the respective threshold voltages of the memory cells to different levels.
  • multi-level memory cells for storing 2-bit data will be described.
  • some multi-level cells can store more than 2 bits.
  • an upper bit will be referred to as 2 nd page data and a lower bit will be referred to as 1 st page data.
  • FIG. 3 is a block diagram illustrating one order in which memory cells in sub-memory array 11 or 13 illustrated in FIG. 2 can be programmed.
  • memory cells are programmed in units of odd and even pages. In other words, even memory cells connected to the same word line are programmed at the same time and odd memory cells connected to the same word line are programmed at the same time.
  • a method of programming memory cells in sub-memory array 11 or 13 is described below with reference to FIGS. 1 through 3 .
  • switching block 16 comprises switches 16 - 1 through 16 - 8 and page buffer 18 includes storage elements 18 - 1 through 18 - 4 .
  • Switches 16 - 1 , 16 - 3 , 16 - 5 , and 16 - 7 respectively connect even bit lines BLe 1 , BLe 2 , BLe 1 ′, and BLe 2 ′ in sub-memory array 11 and 13 with respective data storage elements 18 - 1 , 18 - 2 , 18 - 3 and 18 - 4 in response to a first control signal output from control signal generation circuit 14 .
  • switches 16 - 2 , 164 , 16 - 6 , and 16 - 8 in switching block 16 respectively connect odd bit lines BLo 1 , BLo 2 , BLo 1 ′, and BLo 2 ′ in sub-memory array 11 and 13 with respective data storage elements 18 - 1 , 18 - 2 , 18 - 3 , and 18 - 4 in response to a second control signal output from control signal generation circuit 14 .
  • a program operation or read operation can be performed on odd memory cells or even memory cells according to the first and second control signals.
  • the memory cells are programmed in an order indicated by the reference numerals 0 through 11 .
  • 1 st page data is programmed in memory cells connected to odd bit lines, as indicated by reference numerals “ 0 ”. Then 1 st page data is programmed in memory cells connected to even bit lines, as indicated by reference numerals “ 1 ”. Next, 2 nd page data is programmed in memory cells connected to odd bit lines as indicated by reference numeral “ 2 ”, and so on.
  • FIG. 4 is a conceptual diagram illustrating a coupling effect between conventional memory cells.
  • the coupling effect occurs where a threshold voltage change ⁇ Vx of one or more memory cells causes a threshold voltage change in other, e.g., adjacent memory cells.
  • a threshold voltage of an odd memory cell in FIG. 4 may change due to coupling capacitances Cx between the even memory cells and the odd memory cell.
  • the magnitude of the coupling effect can be roughly quantified in proportion to a combination of coupling capacitances Cx and the threshold voltage change ⁇ Vx of the even memory cells.
  • the magnitude of the coupling effect can be roughly quantified as 2Cx ⁇ Vx.
  • FIGS. 5A through 5D illustrate threshold voltage distributions for memory cells affected by coupling capacitance when programmed using a conventional programming method. Reference numerals shown in FIGS. 5A through 5D indicate the order in which memory cells are programmed.
  • a threshold voltage of a memory cell labeled “worst case cell” is affected by a threshold voltage change ⁇ Vx 1 of the selected even memory cells.
  • the labels Vo 10 , Vo 00 , and Vo 01 denote program verify voltage levels used to verify that memory cells are properly programmed.
  • the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ⁇ Vx 1 of horizontally adjacent memory cells, by a threshold voltage change ⁇ Vy 1 of a vertically adjacent memory cell and threshold voltage changes ⁇ VXy 1 of diagonally adjacent memory cells.
  • FIGS. 5C and 5D are programmed in a different order than the memory cells in FIGS. 5A and 5B .
  • FIG. 5C where selected even memory cells connected to word line WL 0 are programmed from threshold voltage state “11” to a threshold voltage state “10” in an operation indicated by reference numeral “ 5 ”, for example, the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ⁇ Vx 2 of the selected even memory cells.
  • the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ⁇ Vx 2 of horizontally adjacent even memory cells, by a threshold voltage change ⁇ Vy 2 of a vertically adjacent odd memory cell, and threshold voltage changes ⁇ Vxy 2 of diagonally adjacent memory cells.
  • the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ⁇ Vx 1 , ⁇ Vx 2 , and ⁇ Vxy 2 , even when the programming order is varied. As a result, the performance and reliability of the memory cells tends to deteriorate.
  • embodiments of the invention provide a non-volatile memory device and related methods adapted to reduce a coupling effect between horizontally adjacent storage elements.
  • a method of operating a non-volatile memory device comprises a memory array, and the memory array comprises a first sub-memory array including a plurality of cell strings and a plurality of even and odd bit lines respectively connected to the plurality of cell strings, a second sub-memory array including a plurality of cell strings and a plurality of even and odd bit lines respectively connected to the plurality of cell strings, and a strapping line extending in a column direction between the first sub-memory array and the second sub-memory array.
  • the method comprises receiving page data to be programmed, and simultaneously applying a bit line voltage corresponding to the page data to the plurality of even and odd bit lines in the first sub-memory array to program the page data in the plurality of cell strings in the first sub-memory array.
  • a method of programming a non-volatile memory device comprises a first sub-memory array, a second sub-memory array, a plurality of word lines connected to the first and second sub-memory arrays, and a strapping line extending in a column direction between the first sub-memory array and the second sub-memory array.
  • the method comprises applying a first operating voltage to a selected word line among the plurality of word lines and applying a second operating voltage to all non-selected word lines among the plurality of word lines, and performing a first program operation by simultaneously programming data to all memory cells included in the first sub-memory array and connected to the selected word line.
  • a non-volatile memory device comprises a first sub-memory array including a plurality of cell strings respectively connected with a plurality of first bit lines, a second sub-memory array including a plurality of cell strings respectively connected with a plurality of second bit lines, a strapping line formed between the first sub-memory array and the second sub-memory array, a page buffer including a plurality of data storage elements, and a switching block configured to perform a first switching operation for simultaneously connecting a first subset of the plurality of data storage elements with all of the respective first bit lines and a second switching operation for simultaneously connecting a second subset of the plurality of data storage elements with all of the respective second bit lines in response to at least one control signal.
  • a non-volatile memory device comprises a memory array comprising a first sub-memory array including a plurality of cell strings respectively connected with a plurality of first bit lines, a second sub-memory array including a plurality of cell strings respectively connected with a plurality of second bit lines, and at least one strapping line disposed between the first sub-memory array and the second sub-memory array.
  • the device further comprises a page buffer including a plurality of first data storage elements and a plurality of second data storage elements, and a switching block configured to perform a first switching operation to simultaneously connect the first data storage elements with the respective first bit lines in response to at least one first control signal, and further configured to perform a second switching operation to simultaneously connect the second data storage elements with the respective second bit lines in response to at least one second control signal.
  • a non-volatile memory device comprises a memory array including a first sub-memory array including a plurality of cell strings respectively connected with a plurality of first bit lines and a plurality of cell strings connected with a plurality of second bit lines, a second sub-memory array including a plurality of cell strings respectively connected with a plurality of third bit lines and a plurality of cell strings connected with a plurality of fourth bit lines, and a strapping line disposed between the first sub-memory array and the second sub-memory array.
  • the device further comprises a page buffer including a plurality of first data storage elements and a plurality of second data storage elements, a plurality of first switches respectively connected between the first bit lines and the first data storage elements, a plurality of second switches respectively connected between the second bit lines and the second data storage elements, a plurality of third switches respectively connected between the third bit lines and the first data storage elements, and a plurality of fourth switches respectively connected between the fourth bit lines and the second data storage elements.
  • a page buffer including a plurality of first data storage elements and a plurality of second data storage elements, a plurality of first switches respectively connected between the first bit lines and the first data storage elements, a plurality of second switches respectively connected between the second bit lines and the second data storage elements, a plurality of third switches respectively connected between the third bit lines and the first data storage elements, and a plurality of fourth switches respectively connected between the fourth bit lines and the second data storage elements.
  • a non-volatile memory device comprising a word line, a first sub-memory array including a plurality of memory cells connected to the word line and formed in a first conductivity type region, a second sub-memory array including a plurality of memory cells connected to the word line and formed in the first conductivity type region, a strapping line disposed between the first sub-memory array and the second sub-memory array and adapted to apply a voltage to the first conductivity type region, and a program control block configured to perform at least one operation among a first program operation for programming first page data to the plurality of memory cells included in the first sub-memory array and a second program operation for programming second page data to the plurality of memory cells included in the second sub-memory array in response to at least one control signal during a program operation.
  • FIG. 1 is a block diagram of a conventional memory array including a plurality of sub-memory arrays
  • FIG. 2 is a block diagram of a non-volatile memory device including the memory array illustrated in FIG. 1 ;
  • FIG. 3 is a block diagram illustrating an order in which memory cells in a sub-memory array illustrated in FIG. 2 are programmed;
  • FIG. 4 is a conceptual diagram for explaining a coupling effect between conventional memory cells
  • FIGS. 5A through 5D illustrate threshold voltage distributions of a memory cell affected by the coupling effect when memory cells in the memory array of FIG. 1 are programmed using a conventional method
  • FIG. 6A is a block diagram of a memory array including sub-memory arrays according to selected embodiments of the invention.
  • FIG. 6B is a block diagram illustrating an example of a strapping line according to selected embodiments of the invention.
  • FIG. 7 is a block diagram of a memory array including sub-memory arrays according to selected embodiments of the invention.
  • FIG. 8 illustrates an order for programming memory cells in the memory array illustrated in FIGS. 6A and 7 ;
  • FIG. 9 is a block diagram of a non-volatile memory device including a memory array according to selected embodiments of the invention.
  • FIG. 10 is a block diagram of a non-volatile memory device including a memory array according to selected embodiments of the invention.
  • FIG. 11 is a diagram for explaining a coupling disturbance occurring in a horizontal direction when memory cells are programmed according to selected embodiments of the invention.
  • FIGS. 12A through 12D illustrate threshold voltage distributions of a memory cell in worst cases due to a coupling disturbance when memory cells are programmed according to selected embodiments of the present invention
  • FIG. 13 is a flowchart illustrating a method of programming first page data according to selected embodiments of the invention.
  • FIG. 14 is a flowchart illustrating a method of programming second page data according to selected embodiments of the present invention.
  • FIG. 6A is a block diagram of a memory array 30 including sub-memory arrays according to selected embodiments of the invention.
  • FIG. 6B illustrates an example of a strapping line 31 according to selected embodiments of the invention.
  • memory array 30 includes a plurality of sub-memory blocks 30 - 1 through 30 - 6 .
  • a plurality of strapping lines 31 extending in a bit line or column direction are arranged between adjacent sub-memory blocks, e.g., between sub-memory blocks 30 - 1 and 30 - 2 , 30 - 2 and 30 - 3 , 30 - 3 and 30 - 4 , 30 - 4 and 30 - 5 , and 30 - 5 and 30 - 6 .
  • Each of strapping lines 31 includes a strapping line for supplying power to a common source line, a strapping line for applying a voltage to a memory sub-region (e.g., a P-type region or an N-type region) in which memory cells are formed, and a bit line connected with dummy memory cells.
  • Each of strapping lines 31 is typically formed with a structure similar to that of bit lines connected to cell strings in memory array 30 .
  • a single sub-memory block forms a single sub-memory array.
  • Each of sub-memory blocks 30 - 1 though 30 - 6 includes a plurality of even bit lines and a plurality of odd bit lines.
  • FIG. 7 is a block diagram of a memory array 32 including sub-memory arrays according to selected embodiments of the present invention.
  • memory array 32 included in a non-volatile memory device includes a plurality of sub-memory blocks 32 - 1 through 32 - 6 and strapping lines 31 .
  • At least one of strapping lines 31 extending in a bit line direction is arranged between adjacent sub-memory blocks, e.g., between sub-memory blocks 32 - 1 and 32 - 2 , 32 - 2 and 32 - 3 , 32 - 3 and 32 - 4 , 32 - 4 and 32 - 5 , and 32 - 5 and 32 - 6 .
  • a sub-memory array may include more than two sub-memory blocks.
  • FIG. 8 illustrates an order in which memory cells can be programmed in memory array 30 or 32 illustrated in FIG. 6A or FIG. 7 .
  • the memory cells are typically programmed by page unit, and therefore memory cells within the same page, i.e., having the same page address, are generally programmed at the same time.
  • all even and odd memory cells connected to the same word line in the same sub-memory array are programmed at the same time. For instance, during a first program operation, where a first page or a least significant bit (LSB) is programmed, a first word line WL 0 connected to a first sub-memory array 30 - 3 is selected. A program voltage is applied to first word line WL 0 connected to first sub-memory array 30 - 3 , and all memory cells in sub-memory array 30 - 3 connected with first word line WL 0 are programmed with first page data.
  • LSB least significant bit
  • first program operation completes, the programmed memory cells connected with even bit lines and memory cells connected with odd bit lines in sub-memory array 30 - 3 are alternately verified.
  • first word line WL 0 connected to a second sub-memory array 30 - 4 is selected.
  • the program voltage is applied to selected first word line WL 0 , and all memory cells connected with first word line WL 0 in second sub-memory array 304 are programmed with first page data.
  • the programmed memory cells connected with even bit lines and memory cells connected with odd bit lines in sub-memory array 30 - 4 are alternately verified.
  • second page data is programmed in the memory cells connected to word line WL 0 in first sub-memory array 30 - 3 , then second page data is programmed in the memory cells connected to word line WL 0 in second sub-memory array 30 - 4 , and so on.
  • the memory cells included in first and second sub-memory arrays 30 - 3 and 30 - 4 preferably comprise NAND flash electrically erasable and programmable read only memory (EEPROM) cells.
  • the memory cells may single level cells (SLCs) or multi-level cell (MLCs).
  • SLCs single level cells
  • MLCs multi-level cell
  • a storage element i.e., a floating gate of a NAND flash EEPROM cell may store one or more bits of data according to the amount of stored charges.
  • the reference numerals 0 through 11 in FIG. 8 indicate the order in which memory cells are programmed or written to. According to selected embodiments of the present invention, memory cells connected to the same word line in each of sub-memory cell arrays 30 - 3 and 30 - 4 can be programmed at one time using the same page address regardless of even and odd bit lines.
  • FIG. 9 is a block diagram of a non-volatile memory device 40 including a memory array 30 according to an embodiment of the invention.
  • non-volatile memory device 40 includes memory array 30 , a row decoder 12 , a control signal generation circuit 34 , a switching block 36 , and a page buffer 41 .
  • Switching block 36 includes switches 36 - 1 through 36 - 4 and 37 - 1 and 37 - 4 and page buffer 41 includes data storage elements 40 - 1 through 40 - 4 .
  • Memory array 30 includes a plurality of sub-memory arrays, including first sub-memory array 30 - 3 and second sub-memory array 30 - 4 .
  • First sub-memory array 30 - 3 includes a plurality of cell strings 15 which are respectively connected with first bit lines BLe 1 , BLo 1 , BLe 2 , and BLo 2 .
  • Second sub-memory array 30 - 4 includes a plurality of cell strings 15 which are respectively connected with second bit lines BLe 1 ′, BLo 1 ′, BLe 2 ′, and BLo 2 ′.
  • the label “BLe” denotes an even bit line
  • the label “BLo” denotes an odd bit line.
  • Each of cell strings 15 includes a fist selection transistor, a second selection transistor, and a plurality of NAND flash EEPROM cells connected in series between the first and second selection transistors. At least one strapping line extending in a bit line or column direction is disposed between first sub-memory array 30 - 3 and second sub-memory array 30 - 4 .
  • Row decoder 12 typically functions as a word line driving circuit. Row decoder 12 may select one of a plurality of word lines WL 1 through WLn in response to a row address and apply a first operating voltage to the selected word line and a second operating voltage to non-selected word lines. For instance, in a program mode, row decoder 12 typically applies the first operating voltage, e.g., a program voltage, to the selected word line and the second operating voltage, e.g., a pass voltage, to the non-selected word lines. As an example, the program voltage may be between 15 and 20 V and the pass voltage may be about 10 V.
  • row decoder 12 typically applies the first operating voltage, e.g., a ground voltage, to the selected word line and the second operating voltage, e.g., a read voltage, to the non-selected word lines.
  • the read voltage is typically around 4.5 V.
  • the program voltage is generally higher than the pass voltage, and the pass voltage is generally higher than the read voltage.
  • Control signal generation circuit 34 typically generates at least one of control signals CS 1 through CS 4 . Alternately, control signal generation circuit 34 may generate at least one of signals CS 1 and CS 2 and at least one of control signals CS 3 and CS 4 .
  • Control signal generation circuit 34 is generally implemented as a bit line driving circuit or a special circuit for accessing bit lines in memory array 30 . More specifically, control signal generation circuit 34 typically generates at least one among first control signal CS 1 for controlling switches 36 - 1 and 36 - 3 , second control signal CS 2 for controlling switches 36 - 2 and 36 - 4 , third control signal CS 3 for controlling switches 37 - 1 and 37 - 3 , and fourth control signal CS 4 for controlling switches 37 - 2 and 37 - 4 .
  • Each of switches 36 - 1 through 36 - 4 comprises a MOS transistor and referred to as a first transistor, and each of first transistors 36 - 1 through 36 - 4 is connected between a corresponding one among first bit lines BLe 1 , BLo 1 , BLe 2 , and BLo 2 and a corresponding one among data storage elements 40 - 1 through 40 - 4 .
  • transistor 36 - 1 is connected between first bit line BLe 1 and data storage element 40 - 1
  • transistor 36 - 2 is connected between first bit line BLo 1 and data storage element 40 - 3
  • transistor 36 - 3 is connected between first bit line BLe 2 and data storage element 40 - 2
  • transistor 36 - 4 is connected between first bit line BLo 2 and data storage element 40 - 4 .
  • Each of second switches 37 - 1 through 37 - 4 comprises a MOS transistor and referred to as a second transistor, and each of second transistors 37 - 1 through 37 - 4 is connected between a corresponding one among second bit lines BLe 1 ′, BLo 1 ′, BLe 2 ′, and BLo 2 ′ and a corresponding one among plurality of data storage elements 40 - 1 through 40 - 4 .
  • transistor 37 - 1 is connected between second bit line BLe 1 ′ and data storage element 40 - 1
  • transistor 37 - 2 is connected between second bit line BLo 1 ′ and data storage element 40 - 3
  • transistor 37 - 3 is connected between second bit line BLe 2 ′ and data storage element 40 - 2
  • transistor 374 is connected between second bit line BLo 2 ′ and data storage element 404 .
  • Page buffer 41 includes a plurality of data storage elements 40 - 1 through 40 - 4 .
  • Each of data storage elements 40 - 1 through 40 - 4 comprises a register including a plurality of latches.
  • Page buffer 41 stores data to be programmed into memory array 30 in a program operation and also stores data that has been read from memory array 30 in a read operation.
  • page buffer 41 may store data read from memory array 30 in a program verification operation.
  • data storage elements 40 - 1 through 40 - 4 detect data stored in NAND flash EEPROM cells connected with a selected word line and first bit lines BLe 1 , BLo 1 , BLe 2 , and BLo 2 or second bit lines BLe 1 ′, BLo 1 ′, BLe 2 ′, and BLo 2 ′.
  • control signal generation circuit 34 generates control signals CS 1 and CS 2 to turn on first switches 36 - 1 through 36 - 4 at the same time
  • data storage elements 40 - 1 through 40 - 4 may apply a program inhibition voltage, e.g., a power supply voltage, or a program voltage, e.g., a ground voltage, to first bit lines BLe 1 , BLo 1 , BLe 2 , and BLo 2 , respectively, at one time in the program mode according to data to be programmed. Accordingly, unlike non-volatile memory device 20 illustrated in FIG.
  • non-volatile memory device 40 can simultaneously program all flash EEPROM cells in first sub-memory array 30 - 3 and connected with a selected word line. As a result, a coupling disturbance or a coupling effect between horizontally adjacent memory cells is avoided, as illustrated in FIG. 11 .
  • control signal generation circuit 34 generates control signals CS 3 and CS 4 to turn on second switches 37 - 1 through 37 - 4 at the same time
  • data storage elements 40 - 1 through 40 - 4 may apply the program inhibition voltage or the program voltage to second bit lines BLe 1 ′, BLo 1 ′, BLe 2 ′, and BLo 2 ′, respectively, at the same time in the program mode according to data to be programmed.
  • non-volatile memory device 40 can simultaneously program all flash EEPROM cells included in second sub-memory array 30 - 4 and connected with the selected word line. As a result, a coupling disturbance or a coupling effect that may be caused by adjacent memory cells is avoided, as illustrated in FIG. 11 .
  • Each of control signals CS 1 through CS 4 may include one or more bits.
  • FIG. 10 is a block diagram of a non-volatile memory device 40 ′ including a memory array according to selected embodiments of the invention.
  • Non-volatile memory device 40 ′ illustrated in FIG. 10 is similar to non-volatile memory device 40 illustrated in FIG. 9 , except that a switching block 46 is substituted for switching block 36 and a page buffer 50 is substituted for page buffer 41 .
  • switching block 46 comprises first switches 46 - 1 through 46 - 4 and second switches 47 - 1 through 47 - 4 and page buffer 50 comprises first data storage elements 51 - 1 through 51 - 4 and second data storage elements 53 - 1 through 53 - 4 .
  • Each of data storage elements 51 - 1 through 51 - 4 and 53 - 1 through 53 - 4 typically comprises a register including at least one latch.
  • Each of first switches 46 - 1 through 46 - 4 comprises a MOS transistor and is referred to as a first transistor, and each of first transistors 46 - 1 through 46 - 4 is connected between a corresponding one among first bit lines BLe 1 , BLo 1 , BLe 2 , and BLo 2 and a corresponding one among first data storage elements 51 - 1 through 51 - 4 .
  • transistor 46 - 1 is connected between first bit line BLe 1 and first data storage element 51 - 1
  • transistor 46 - 2 is connected between first bit line BLo 1 and first data storage element 51 - 2
  • transistor 46 - 3 is connected between first bit line BLe 2 and first data storage element 51 - 3
  • transistor 46 - 4 is connected between first bit line BLo 2 and first data storage element 51 - 4 .
  • Each of second switches 47 - 1 through 47 - 4 comprises a MOS transistor and is referred to as a second transistor, and each of second transistors 47 - 1 through 47 - 4 is connected between a corresponding one among second bit lines BLe 1 ′, BLo 1 ′, BLe 2 ′, and BLo 2 ′ and a corresponding one among second data storage elements 53 - 1 through 53 - 4 .
  • transistor 47 - 1 is connected between second bit line BLe 1 ′ and second data storage element 53 - 1
  • transistor 47 - 2 is connected between second bit line BLo 1 ′ and second data storage element 53 - 2
  • transistor 47 - 3 is connected between second bit line BLe 2 ′ and second data storage element 53 - 3
  • transistor 47 - 4 is connected between second bit line BLo 2 ′ and second data storage element 53 - 4 .
  • control signal generation circuit 34 In a program mode, control signal generation circuit 34 generates control signals CS 1 and CS 2 to turn on first switches 46 - 1 through 46 - 4 at the same time, and first data storage elements 51 - 1 through 51 - 4 respectively apply the program inhibition voltage or the program voltage to bit lines BLe 1 , BLo 1 , BLe 2 , and BLo 2 in first sub-memory array 30 - 3 at the same time according to data to be programmed. Accordingly, all flash EEPROM cells included in first sub-memory array 30 - 3 and connected with a selected word line can be simultaneously programmed. As such, a coupling disturbance or a coupling effect between horizontally adjacent memory cells is avoided, as illustrated in FIG. 11 .
  • control signal generation circuit 34 may also generate control signals CS 3 and CS 4 at the same time to turn on second switches 47 - 1 through 47 - 4 .
  • second data storage elements 53 - 1 through 53 - 4 respectively apply the program inhibition voltage or the program voltage to second bit lines BLe 1 ′, BLo 1 ′, BLe 2 ′, and BLo 2 ′ included in second sub-memory array 30 - 4 at the same time in the program mode according to data to be programmed. Accordingly, all flash EEPROM cells included in second sub-memory array 30 - 4 and connected with the selected word line can be simultaneously programmed. As a result, a coupling disturbance or a coupling effect between horizontally adjacent memory cells is avoided, as illustrated in FIG. 11 .
  • control signal generation circuit 34 generates control signals CS 1 through CS 4 to simultaneously turn on first switches 46 - 1 through 46 - 4 and second switches 47 - 1 through 47 - 4 , all flash EEPROM cells that are included in first and second sub-memory arrays 30 - 3 and 30 - 4 and are connected with the selected word line can be simultaneously programmed.
  • a non-volatile memory device in the program mode or the read mode, can simultaneously program data into or read data from all memory cells that are included in first sub-memory array 30 - 3 and connected with a selected word line and can simultaneously program data into or read data from all memory cells that are included in second sub-memory array 30 - 4 and connected with the selected word line.
  • the non-volatile memory device in the program or read mode, can simultaneously program data into or read data from all memory cells that are included in first and second sub-memory arrays 30 - 3 and 30 - 4 and connected with the selected word line.
  • a program control block performs at least one operation among a first program operation, in which all memory cells included in first sub-memory array 30 - 3 are simultaneously programmed, and a second program operation, in which all memory cells included in second sub-memory array 30 - 4 are simultaneously programmed, in response to at least one of control signals CS 1 through CS 4 .
  • the program control block includes a word line driving circuit, i.e., row decoder 12 , page buffer 41 or 50 , and switching block 36 or 46 .
  • FIG. 11 is a diagram illustrating coupling disturbance between horizontally adjacent memory cells that are programmed according to selected embodiments of the present invention. Referring to FIGS. 4 and 11 , where all memory cells connected with word line WL 0 in a sub-memory block are simultaneously programmed according to selected embodiments of the present invention, a coupling effect or a coupling disturbance between horizontally adjacent memory cells is avoided.
  • FIGS. 12A through 12D illustrate threshold voltage distributions of a memory cell in worst cases where memory cells are programmed according to selected embodiments of the present invention.
  • threshold voltage changes ⁇ Vx 1 or ⁇ Vx 2 are completely removed from the memory cell labeled “worst case cell” in FIGS. 12A through 12D .
  • the non-volatile memory device according to selected embodiments of the present invention does not need to repeatedly perform the program operation in order to remove the effects of the coupling effect. As a result, the reliability of the non-volatile memory device is improved.
  • FIG. 13 is a flowchart illustrating a method of programming first page data according to selected embodiments of the invention.
  • the program operation includes a programming procedure for injecting electrons into floating gates of selected memory cells and a program verification procedure for verifying whether programmed memory cells have reached a predetermined threshold voltage.
  • first page data is loaded into page buffer 41 in an operation S 10 .
  • first page data is programmed into first sub-memory array 30 - 3 .
  • a programming operation for other arrays such as second sub-memory array 30 - 4 can be performed similar to programming operation used to program first sub-memory array 30 - 3 .
  • first page data loaded into page buffer 41 is simultaneously programmed to memory cells included in first sub-memory array 30 - 3 through switches 36 - 1 through 36 - 4 in an operation S 20 . Then, during a program verification procedure for verifying whether the first page data has been properly programmed, page buffer 41 reads data from memory cells connected with even bit lines BLe 1 and BLe 2 through switches 36 - 1 and 36 - 3 turned on in response to first control signal CS 1 and verifies the data in an operation S 30 . In addition, page buffer 41 also reads data from memory cells connected with odd bit lines BLo 1 and BLo 2 through switches 36 - 2 and 36 - 4 turned on in response to second control signal CS 2 and verifies the data in an operation S 40 .
  • the programming procedure may be performed with respect to each sub-memory array and the program verification procedure may be alternately performed with respect to a set of even bit lines and a set of odd bit lines.
  • the first page data program operation illustrated in FIG. 13 corresponds to an LSB program operation, in which a first bit line voltage, e.g., a voltage for programming data “1” or data “0”, is applied to all bit line included in the first sub-memory array 30 - 3 according to LSB data to be programmed so that the LSB data is programmed.
  • FIG. 14 is a flowchart illustrating a method of programming second page data according to selected embodiments of the present invention.
  • second page data is loaded to page buffer 41 in operation S 110 .
  • the second page data is programmed into first sub-memory array 30 - 3 .
  • a programming operation for other arrays such as second sub-memory array 30 - 4 can be performed similar to programming operation used to program first sub-memory array 30 - 3 .
  • page buffer 41 reads first page data from memory cells connected with even bit lines BLe 1 and BLe 2 included in first sub-memory array 30 - 3 in an operation S 120 and reads the first page data from memory cells connected with odd bit lines BLo 1 and BLo 2 included in first sub-memory array 30 - 3 in operation S 130 .
  • page buffer 41 programs the second page data based on data read in operations S 120 and 130 and the second page data to be loaded.
  • a second page data program operation corresponds to an MSB program operation in which LSB data that has been programmed to memory cells included in first sub-memory array 30 - 3 during the LSB program operation is sequentially read through even bit lines BLe 1 and BLe 2 and odd bit lines BLo 1 and BLo 2 and a second bit line voltage, e.g., a voltage for programming data “1” or “0”, is applied to all bit lines included in first sub-memory array 30 - 3 based on the LSB data and MSB data.
  • a second bit line voltage e.g., a voltage for programming data “1” or “0”
  • page buffer 40 reads data from memory cells connected with the even bit lines BLe 1 and BLe 2 through the switches 36 - 1 and 36 - 3 turned on in response to the first control signal CS 1 and verifies the data in operation S 150 .
  • Page buffer 40 also reads data from memory cells connected with the odd bit lines BLo 1 and BLo 2 through the switches 36 - 2 and 36 - 4 turned on in response to second control signal CS 2 and verifies the data in an operation S 160 .
  • the second page data programming procedure may be performed with respect to each sub-memory array and the second page data program verification procedure may be alternately performed with respect to a set of even bit lines and a set of odd bit lines.
  • threshold voltage changes due to coupling between horizontally adjacent memory cells are substantially eliminated. Accordingly, the need for re-programming to remove the effects of coupling disturbance is reduced or eliminated, thereby increasing the reliability of memory cells while allowing high-speed programming.

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