US7512190B2 - Data transmission apparatus using asynchronous dual-rail bus and method therefor - Google Patents

Data transmission apparatus using asynchronous dual-rail bus and method therefor Download PDF

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Publication number
US7512190B2
US7512190B2 US10/938,391 US93839104A US7512190B2 US 7512190 B2 US7512190 B2 US 7512190B2 US 93839104 A US93839104 A US 93839104A US 7512190 B2 US7512190 B2 US 7512190B2
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United States
Prior art keywords
data
index
control unit
signal
transmission
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Expired - Fee Related, expires
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US10/938,391
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English (en)
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US20050180514A1 (en
Inventor
Byung-Soo Choi
Dong-Soo Har
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Gwangju Institute of Science and Technology
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Gwangju Institute of Science and Technology
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Assigned to GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY, DEPARTMENT OF INFORMATION AND COMMUNICATIONS (GIST) reassignment GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY, DEPARTMENT OF INFORMATION AND COMMUNICATIONS (GIST) ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAR, DONG-SOO, CHOI, BYUNG-SOO
Publication of US20050180514A1 publication Critical patent/US20050180514A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
US10/938,391 2004-02-18 2004-09-09 Data transmission apparatus using asynchronous dual-rail bus and method therefor Expired - Fee Related US7512190B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040010699A KR100617387B1 (ko) 2004-02-18 2004-02-18 비동기식 이중선 버스를 이용한 데이터 전송 장치 및 그방법
KR10-2004-0010699 2004-02-18

Publications (2)

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US20050180514A1 US20050180514A1 (en) 2005-08-18
US7512190B2 true US7512190B2 (en) 2009-03-31

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US10/938,391 Expired - Fee Related US7512190B2 (en) 2004-02-18 2004-09-09 Data transmission apparatus using asynchronous dual-rail bus and method therefor

Country Status (2)

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US (1) US7512190B2 (ko)
KR (1) KR100617387B1 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9977852B2 (en) * 2015-11-04 2018-05-22 Chronos Tech Llc Application specific integrated circuit interconnect
US9977853B2 (en) 2015-11-04 2018-05-22 Chronos Tech Llc Application specific integrated circuit link
US10073939B2 (en) 2015-11-04 2018-09-11 Chronos Tech Llc System and method for application specific integrated circuit design
US11550982B2 (en) 2015-11-04 2023-01-10 Chronos Tech Llc Application specific integrated circuit interconnect
US10181939B2 (en) 2016-07-08 2019-01-15 Chronos Tech Llc Systems and methods for the design and implementation of an input and output ports for circuit design
US10331835B2 (en) 2016-07-08 2019-06-25 Chronos Tech Llc ASIC design methodology for converting RTL HDL to a light netlist
US10637592B2 (en) 2017-08-04 2020-04-28 Chronos Tech Llc System and methods for measuring performance of an application specific integrated circuit interconnect
US11087057B1 (en) 2019-03-22 2021-08-10 Chronos Tech Llc System and method for application specific integrated circuit design related application information including a double nature arc abstraction

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128678A (en) * 1998-08-28 2000-10-03 Theseus Logic, Inc. FIFO using asynchronous logic to interface between clocked logic circuits
US6152613A (en) * 1994-07-08 2000-11-28 California Institute Of Technology Circuit implementations for asynchronous processors
US20030163627A1 (en) * 2002-02-28 2003-08-28 Deng Brian Tse Enhanced universal serial bus (USB) bus monitor controller
US6625163B1 (en) * 1999-04-21 2003-09-23 Nortel Networks Ltd. Collision detection on a differential bus
US20030196030A1 (en) * 1990-10-18 2003-10-16 Elliott Duncan G. Method and apparatus for an energy efficient operation of multiple processors in a memory
US20030237056A1 (en) * 2002-06-21 2003-12-25 Aaron Schoenfeld Low power buffer implementation
US20040078608A1 (en) * 2001-04-02 2004-04-22 Ruban Kanapathippillai Method and apparatus for power reduction in a digital signal processor integrated circuit
US20040114698A1 (en) * 2001-02-24 2004-06-17 Barrett Wayne Melvin Data capture technique for high speed signaling
US6798744B1 (en) * 1999-05-14 2004-09-28 Pmc-Sierra, Inc. Method and apparatus for interconnection of flow-controlled communication
US7298762B2 (en) * 2002-11-15 2007-11-20 Terayon Communication Systems, Inc. Method for sharing an upstream among multiple downstreams

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030196030A1 (en) * 1990-10-18 2003-10-16 Elliott Duncan G. Method and apparatus for an energy efficient operation of multiple processors in a memory
US6152613A (en) * 1994-07-08 2000-11-28 California Institute Of Technology Circuit implementations for asynchronous processors
US6128678A (en) * 1998-08-28 2000-10-03 Theseus Logic, Inc. FIFO using asynchronous logic to interface between clocked logic circuits
US6625163B1 (en) * 1999-04-21 2003-09-23 Nortel Networks Ltd. Collision detection on a differential bus
US6798744B1 (en) * 1999-05-14 2004-09-28 Pmc-Sierra, Inc. Method and apparatus for interconnection of flow-controlled communication
US20040114698A1 (en) * 2001-02-24 2004-06-17 Barrett Wayne Melvin Data capture technique for high speed signaling
US20040078608A1 (en) * 2001-04-02 2004-04-22 Ruban Kanapathippillai Method and apparatus for power reduction in a digital signal processor integrated circuit
US20030163627A1 (en) * 2002-02-28 2003-08-28 Deng Brian Tse Enhanced universal serial bus (USB) bus monitor controller
US20030237056A1 (en) * 2002-06-21 2003-12-25 Aaron Schoenfeld Low power buffer implementation
US7298762B2 (en) * 2002-11-15 2007-11-20 Terayon Communication Systems, Inc. Method for sharing an upstream among multiple downstreams

Also Published As

Publication number Publication date
US20050180514A1 (en) 2005-08-18
KR20050082280A (ko) 2005-08-23
KR100617387B1 (ko) 2006-08-31

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