US7411523B2 - Hardware efficient implementation of finite impulse response filters with limited range input signals - Google Patents
Hardware efficient implementation of finite impulse response filters with limited range input signals Download PDFInfo
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- US7411523B2 US7411523B2 US11/748,923 US74892307A US7411523B2 US 7411523 B2 US7411523 B2 US 7411523B2 US 74892307 A US74892307 A US 74892307A US 7411523 B2 US7411523 B2 US 7411523B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
- H04L25/4919—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using balanced multilevel codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H2017/0692—Transposed
Definitions
- Information transmission at maximum transmission rates is the quest of the information transmission designer. Adapting existing data transmission infrastructure to accommodate faster transmission rates may also be desirable. As data transmission rates are increased, data corruption may result from effects such as attenuation, echo, return loss, and crosstalk in the existing transmission infrastructure.
- Attenuation may be defined as signal loss between a transceiver and a receiver. Attenuation may increase with increasing data transmission frequency. Echo may occur as a result of full duplex operation or parallel transmission, i.e., where both the transmit and receive signals are active on the same wire. Residual transmit signal and cabling return loss may combine to produce unwanted signals which may be referred to as echo. Echo may occur due to power reflections due to cable impedance mismatches.
- a method and apparatus for a hardware-efficient implementation of finite impulse response filters with limited range input signals substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
- FIG. 1 is a diagram illustrating a multiplier according to an embodiment of the present invention
- FIG. 2 illustrates a finite impulse response filter with a 10-level input signal according to an embodiment of the present invention
- FIG. 3 is a flow chart illustrating processing of signals using a finite impulse response filter with a 10-level input signal according to an embodiment of the present invention.
- Information bits may be serially transmitted using at least two level symbols, and there may be a one-to-one correspondence between the bits and the symbols.
- the one-to-one correspondence between the bits and symbols may result in a signal with significant frequency components at the bit rate frequency.
- Communication channels may experience significant integrity degradation at higher frequencies.
- communication channels may provide high quality up to a certain threshold frequency.
- the degradation may be very sharp, rendering communications beyond the threshold frequency impossible without providing error correction to the signals.
- Cat-5 cables are defined as comprising four unshielded twisted pairs of wires in a single jacket
- a Cat-5 cable may connect a transceiver and a receiver to provide 4 times parallel data transmission capabilities
- all four twisted pairs of wires in the Cat-5 cable may be employed simultaneously to provide four times the data transmission capability of a single cable having a pair of wires.
- Communication channels having a threshold frequency may limit the data transmission rate to the threshold frequency.
- PAM-5 Pulse Amplitude Modulation level 5
- the PAM-5 standard may be employed to encode 8-bit data words with four five-level symbols.
- a number of encoders may operate in unison to achieve a high data transmission throughput rate.
- the symbols generated by each of the encoders may be transmitted in parallel with respect to one another.
- Parallel transmission may be incompatible with some preexisting networks designed for serial transmissions.
- An embodiment according to the present invention may comprise a method of data coding to adapt a transmission infrastructure to higher speed data transmission.
- PAM-5 is adapted to provide greater bandwidth than binary signaling.
- binary signaling each transmitted symbol represents one bit, for example, 0 or 1.
- each symbol represents one of five different levels, for example, ( ⁇ 2, ⁇ 1, 0, 1, 2). Because each symbol can represent two bits of information, (four levels to represent two bits, plus an extra fifth level which may be used for error correction coding), the symbol rate, and therefore also the signal bandwidth, may be reduced by a factor of two.
- the fifth level of coding may provide error correction to recover transmitted symbols in the presence of signal interference such as, echo, crosstalk, etc.
- Linear digital equalization may be provided by a finite impulse response (FR) filter.
- FR finite impulse response
- PAM-5 a five level FIR filter may be employed.
- PAM-10 i.e., 10 level pulse amplitude modulation
- the rate of data transmission i.e., the bit rate
- PAM-10 is adapted to provide greater bandwidth than PAM-5 and binary signaling
- each transmitted symbol represents one of ten different levels, for example, ( ⁇ 9, ⁇ 7, ⁇ 5, ⁇ 3, ⁇ 1, 1, 3, 5, 7, 9).
- each symbol may represent four bits of information. Because each symbol can represent four bits of information, the symbol rate, and therefore also the signal bandwidth, maybe reduced.
- Signal equalization may also be used to compensate for signal distortion introduced by the communication channel.
- Linear digital equalization may be provided by a finite impulse response (FIR) filter.
- FIR filters provide echo cancellation by performing multiplications of the input signal by selected coefficients. These multiplications may produce a large number of products and additions, which may consume filter chip area and power, produce processing delays that limit symbol rate, and cause other data transmission delays
- Cables used for signal transmission have limited bandwidth capabilities. In order to move information at higher bit rates, more bits per symbol may be encoded. Building an echo cancellation device using a greater number of bits per symbol, ordinarily would increase the delay, chip real estate, power consumption, etc. for the echo cancellation device.
- Booth coding may be applied to multiply the input samples by interference cancellation coefficients.
- Booth coding may provide a reduction in the complexity of multiplication circuits by recoding the numbers being multiplied in a more compact form.
- One approach to perform multiplication is to shift and add, i.e., long multiplication. For each column in the multiplier, the multiplicand is shifted the appropriate number of columns, and multiplied by the value of the digit in that column of the multiplier to obtain a product.
- the number of products is exactly the number of columns in the multiplier. It may be possible to reduce the number of products by half using a technique of radix-4 Booth coding, or modified Booth coding Using radix-4 Booth coding, instead of shifting and adding for every column of the multiplier term and multiplying by 1 or 0, it is possible to take two columns at a time, and multiply by 2, 1, 0, ⁇ 1 or ⁇ 2, to obtain the same result Therefore, to multiply by 7, for example, we can multiply the product aligned against the least significant bit (LSB, first column) by ⁇ 1, and multiply the product aligned with the third column by 2, for example:
- LSB least significant bit
- An advantage of this method is the halving of the number of products, resulting in a decrease in propagation delay in data transmission, reduction in the complexity of the circuit, and reduction in the power consumption of the circuit, and the ability to more compactly code information.
- the method may comprise receiving a signal sample; encoding the signal sample using a coding process to produce symbolic values; modifying the symbolic values to reduce a number of digits used to represent the symbolic values and produce coded values; and processing the coded values in the signal processing device.
- the coding process may be a radix4 Booth coding process.
- modifying the symbolic values may comprise changing a value of a digit in the coding process based upon a value in a next higher order digit of the symbolic value to create the coded value.
- processing may comprise using the coded values input to the signal processing device.
- the signal processing device may comprise a digital filter.
- the digital filter may comprise a finite impulse response filter.
- processing the coded values in the signal processing device may further comprise inputting the coded values to the signal processing device; directing the coded values to a plurality of multipliers; multiplying the coded values by coefficients forming a plurality of products; directing the products to a plurality of adders; summing the products to produce a processed signal; delaying output of the processed signal by at least one unit delay; and outputting the processed signal.
- multiplying the coded values by coefficients forming a plurality of products may further comprise directing the coded values to a plurality of multipliers and a plurality of sign inverters; multiplying the coded values by first coefficients in the multipliers to form at least one first product; and multiplying the coded values by at least one second coefficient in the sign inverters to form at least one second product.
- the method may comprise receiving a signal sample; encoding the signal sample using a coding process to produce symbolic values having a particular number of bits; modifying the symbolic values to reduce a number of digits used to represent the symbolic values and produce coded values; and processing the coded values in the signal processing device.
- reducing the number of digits used to represent the symbolic values may further comprise eliminating at least one digit during the coding process without losing any digital information; and processing more digital information per unit time with fewer processing operations.
- the coding process may be a radix-4 Booth coding process.
- modifying the symbolic values may comprise changing a value of a digit in the coding process based upon a value in a next higher order digit of the symbolic values to create the coded values.
- processing may comprise using the coded values input to the signal processing device.
- the signal processing device may comprise a digital filter.
- the digital filter may comprise a finite impulse response filter.
- processing the coded values in the signal processing device may further comprise inputting the coded values to the signal processing device; directing the coded values to a plurality of multipliers; multiplying the coded values by coefficients forming a plurality of products; directing the products to a plurality of adders; summing the products to produce a processed signal; delaying output of the processed signal by a at least one unit delay; and outputting the processed signal.
- multiplying the coded values by coefficients forming a plurality of products may further comprise directing the coded values to a plurality of multipliers and a plurality of sign inverters; multiplying the coded values by first coefficients in the multipliers to form at least one first product; and multiplying the coded values by at least one second coefficient in the sign inverters to form at least one second product.
- a signal processing device comprising an input adapted to receiving a signal sample; an encoder adapted to encoding the signal sample using a coding process to produce symbolic values; and a processor adapted to modify the symbolic values to reduce a number of digits used to represent the symbolic values, produce coded values, and process the coded values in the signal processing device.
- the device may further comprise a plurality of multipliers; and a plurality of adders, wherein coded values may be input to the signal processing device, multiplied by a plurality of coefficient bits in the plurality of multipliers to create a plurality products, wherein the products may be summed together, and the processed signal may undergo a unit delay before being output from the signal processing device.
- one coding process that the encoder may be adapted to perform is a radix-4 Booth coding process.
- the processor in modifying the symbolic values, may be adapted to change a value of a digit in the coding process based upon a value in a next higher order digit of the symbolic values to create the coded value.
- the signal processing device may comprise a digital filter.
- the digital filter may comprise a finite impulse response filter.
- the signal processing device may also be adapted to input the coded values; multiply the coded values by coefficient bits forming a plurality of products; sum the products to produce a processed signal; delay output of the processed signal by a at least one unit delay; and output the processed signal.
- the signal processing device may also be adapted to multiply the coded values by first coefficients in the multipliers to form at least one first product; and multiply the coded values by at least one second coefficient in sign inverters to form at least one second product.
- FIG. 1 is a diagram illustrating a multiplier 111 according to an embodiment of the present invention
- a set of control signals may be applied to the multiplier 111 .
- the values of each of the control signals causes the multiplier 111 to operate upon an incoming coded value, as discussed below, in a particular manner, (i.e., zero, negate, multiply/shift by one or two columns).
- Three digital control signal inputs ( 888 a , 888 b , and 888 c ) may be provided, wherein at each control signal input, either a 1 or 0 may be input.
- the three digital control signals together cooperatively determine the particular multiplication operation that is performed upon the coded input.
- the particular operation that the multiplier 111 performs upon the coded input signal may vary, based upon the relationship of the three control signal inputs ( 888 a , 888 b , and 888 c ) operating together as discussed below.
- Coded input values may be multiplied by a plurality of coefficient bits ( 444 a , 444 b , and 444 c ), which may be input to a plurality of selectors 777 , and a plurality of exclusive or (XOR) gates 666 , and a plurality of AND gates 555 , to modify the coded values, and thus modify the corresponding transmitted signal.
- a plurality of coefficient bits 444 a , 444 b , and 444 c
- XOR exclusive or
- the output of the Booth coder with the input being bits from the multiplier may be as follows:
- the zero signal may indicate whether the multiplicand is zeroed before being used as a product, which may be the same as multiplying by 0.
- the shift signal (x 1 or x 2 ) may be used as a control signal to a 2:1 multiplexer to select whether or not the product bits are shifted left zero or one position, which may be the same as multiplying by 1 or 2.
- the negate signal may indicate whether or not to invert (sign inversion) all of the bits to create a negative product, which may be the same as multiplying by ⁇ 1.
- Table 1 illustrates possible multiplication operations which may be performed by a multiplier according to an embodiment of the present invention.
- row 1 reveals a situation wherein regardless of what the input control signal values are at input 1 988 c and input 2 889 b , (represented by X), when the input control signal value at input 3 888 a is 0, then the outputs, ( 333 a , 333 b , 333 c , and 333 d , etc., for example), are 0, (i.e., being the same as multiplying the coded value by zero, 0*Multiplicand). Alternatively, when the input value at input 3 888 a is 1, then the coded value is passed through unchanged, (being the same as multiplying by 1).
- the method may comprise further reducing the number of digits required to code a particular number or value.
- the method may comprise reducing the coded value by at least one digit, (i.e., eliminating at least one digit in the coding process), resulting in fewer digits being necessary to be transmitted, while transmitting the same amount of data per unit time.
- 5 bits may be required to transmit the numerical value of negative nine.
- n-bit word For an n-bit word, up to n operations are required to perform the multiplications using standard Booth coding. However, according to an embodiment of the present invention, using a modified Radix-4 Booth coding scheme, for an n-bit word, fewer operations are required to perform the multiplications.
- the operations performed may be additions, subtractions, or no operations at all, for every two bits of the original data word. According to an embodiment of the present invention, because half of the multiplication operations have been eliminated, therefore the logic is required to code the values over the standard binary multiplication method.
- a method of optimized coding of a pulse amplitude modulated level 10 (PAM-10) signal may be performed as follows.
- PAM-10 there are 10 levels represented by the values in the following table
- the digit corresponding to X b 4 may be eliminated. This result is possible because only a portion of the range of values, (i.e., ⁇ 9 and +9), of X b 4 digit of a 3 digit Booth coded value are needed.
- the processing hardware may be simplified, the power consumption is reduced, and the circuit chip area used for the processing is reduced.
- the method comprising application of optimum coding as set forth above may provide at least one less adder for every multiplier and eliminate at least one partial product multiplier for the operation [ ⁇ 1, 0, 1]*C resulting in faster data transmission than previous data transmission applications.
- the optimum coding scheme may be distributed with two bits less than previous data transmission application resulting in at least area reduction, i.e., integrated circuit area reductions, and power savings over previous data transmission applications.
- the optimum coding scheme may also be applicable to systems employing an even greater number of pulse amplitude modulation levels, for example, PAM-21, and PAM-40, when a restricted range of levels is used.
- the number of Booth coded digits may be reduced through coding according to an embodiment of the present invention. For example, by coding the following values [ ⁇ 10, ⁇ 9, ⁇ 8, . . . 8, 9, 10] a 21 level coding scheme (PAM-21) may be realized.
- FIG. 2 illustrates a finite impulse response (FR) filter 100 with a 10-level input signal according to an embodiment of the present invention.
- the input 110 to FIR filter 100 may be a 10-level input signal as explained above and may be designated by the value X.
- Encoding the signal sample may be performed by an encoder (not shown) using a coding process to produce symbolic values.
- the signal value X enters the FIR filter 100 at input 110 .
- the input signal having one of the 10 values above is passed through a plurality of multipliers 120 where the signal is multiplied by coefficients, for example C 0 , C 1 , C 2 , . . . , C n creating a plurality of products.
- the products may then be directed to a plurality of adders 130 .
- the outputs of each of the adders 130 may be delayed for a time represented by unit delay 150 before being passed to the next adder 130 and eventually to output 190 .
- the multipliers may perform at least one of the operations discussed above based upon the values of the control signals controlling the multipliers. After the multiplication operations are performed the coded values may be directed to the plurality of adders 130 . The products may be summed and the output maybe delayed by at least one unit delay 150 . The signal may then be output 190 from the filter. The input signal 110 , after multiplications, additions, etc., makes up the output signal 190 from the filter 100 .
- FIG. 3 is a flow chart 300 illustrating processing of signals using a finite impulse response filter with a 10-level input signal according to an embodiment of the present invention
- an analog signal may be received (block 310 ).
- the analog signal may be converted to a digital signal using an A/D converter (block 320 ).
- the signal may then be encoded using a modified Booth coding procedure (block 330 ), as discussed above.
- the coded signal may be input to a signal processing system (block 340 ) which may comprise a FIR filter for signal processing (block 350 ).
- the coded signal values may be passed to multipliers where they may be multiplied by coefficients. Products resulting from the multiplications may be directed to adders. The products may be summed. The processed signal may be delayed by at least one unit delay. The signal may then be output (block 366 ) from the signal processing system.
- Processing signals according to the embodiment illustrated in FIG. 3 enables the complexity of signal processing systems to be reduced by simplifying the complexity of multiplication circuits.
- An advantageous result according to an embodiment of the present invention is decreasing processor chip size and therefore processor cost by processing more information with coded values comprising more information or bits per symbol.
- the signal processing method according to the present invention may avoid interference and signal distortion because the information is transmitted without increasing the frequency of operation to intolerable levels. Signal processing activity is also reduced by recoding the signal values being processed in a more compact form thus permitting an increased throughput, or more bits per symbol being transmitted per unit time. Power consumption may also be reduced because less processing is required to transmit more information with fewer coded values according to an embodiment of the present invention.
- modified Radix-4 Booth coding permits using only 4 digits for the encoding of a PAM-10 signal, resulting in at least a halving of the number of products to be processed.
- the filter chip size may be reduced while at the same time providing a higher bit rate of transmission. The delay in transmission may also be reduced resulting in faster transmission. Additionally the amount of power consumed per operation may also be decreased.
- a 2.5 Gigabit/second data transmission rate may be accomplished by applying the PAM-10 coding method and a standard Cat-5 cables.
- a Cat-5 cable comprises 4 unshielded twisted wire pairs, and by transmitting 3 bits per symbol at a frequency of 208 MHz, the 2.5 Gigabit/second transmission rate may be described as follows: (4 wire pairs)*(208 MHz transmission frequency)*(3 bits per symbol) is approximately 2.5 Gigabits of information transmitted per second.
- more information i.e., a greater number of bits may be transmitted in the same amount of time using PAM-10 coding techniques.
- PAM-10 coding has been described in the present application, PAM-21, PAM-40, etc., may also be applied where appropriate to further increase the bit rate of data transmission by increasing the number of bits per symbol being coded
- the invention may also be used in multipliers.
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Abstract
Description
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Product 0=Multiplicand*−1, shifted left 0 bits; -
Product 1=Multiplicand*2, shifted left 2 bits.
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Product 0=Multiplicand*1, shifted left 0 bits; -
Product 1=Multiplicand*1, shifted left 1 bit; - Product 2=Multiplicand*1, shifted left 2 bits;
- Product 3=Multiplicand*0, shifted left 3 bits.
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- Bits from multiplier→[Booth Coder]→Negate
- Bits from multiplier→[Booth Coder]→Zero
- Bits from multiplier→[Booth Coder]→shift (x1 or x2)
TABLE 1 |
Multiplier Operations and Control Signal Inputs |
Input 2 | Input 3 | ||||
Input 1 (888c) | (888b) | (888a) | Output | ||
Row | (Multiply by 1 or 2) | (Negate) | (Zero) | (Results) | |
1 | | X | 0 | 0 * Multiplicand | |
2 | 0 | 0 | 1 | 1 * Multiplicand | |
3 | 1 | 0 | 1 | 2 * Multiplicand | |
4 | 0 | 1 | 1 | −1 * Multiplicand | |
5 | 1 | 1 | 1 | −2 * Multiplicand | |
TABLE 2 |
Comparison of Various Coding Values |
Optimum | ||||
Booth Coded | Coded |
16 | 4 | 1 | 4 | 1 | ||
Decimal | Binary | Xb 4 | Xb 2 | Xb 0 | Xo 2 | Xo 0 |
−9 | 10111 | −1 | +2 | −1 | −2 | −1 |
−7 | 11001 | 0 | −2 | +1 | −2 | +1 |
−5 | 11011 | 0 | −1 | −1 | −1 | −1 |
−3 | 11101 | 0 | −1 | +1 | −1 | +1 |
−1 | 11111 | 0 | 0 | −1 | 0 | −1 |
1 | 00001 | 0 | 0 | +1 | 0 | +1 |
3 | 00011 | 0 | +1 | −1 | +1 | −1 |
5 | 00101 | 0 | +1 | +1 | +1 | +1 |
7 | 00111 | 0 | +2 | −1 | +2 | −1 |
9 | 01001 | +1 | −2 | +1 | +2 | +1 |
-
- Table 2 illustrates a comparison of a plurality of coded values according to an embodiment of the present invention.
C*X=C*X b 0+4*C*X b 2+16*C*X b 4
C*X=C*X o 0+4*C*X o 2
when X b n=−1, then X b n−2=2; and 1)
when X b n=1, then X b n−2=−2. 2)
X=−9, −7, −5, −3, −1, 1, 3, 5, 7, 9.
Y(k)=C 0 *X(k−1)+C 1 *X(k−2)+C 2 *X(k−3)+ . . . C n *X(k−n+1).
Time | Output Signal |
k = 0 | 0 |
k = 1 | X0 * C0 |
k = 2 | X1 * C0 + X0 * C1 |
k = 3 | X2 * C0 + X1 * C1 + X0 * C2 |
k = 4 | X3 * C0 + X2 * C1 + X1 * C2 + X0 * C3 |
. . . | . . . |
k = n | Xn−1 * C0 + Xn−2 * C1 + Xn−3 * |
C2 + Xn−4 * C3 + . . . + Xn−m * Cm−1 | |
where k is a quantity of time, X is a 10 level coded input signal, and Cj, j = 0 . . . m are the coefficients. |
(4 wire pairs)*(208 MHz transmission frequency)*(3 bits per symbol) is approximately 2.5 Gigabits of information transmitted per second.
Claims (34)
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US20070052557A1 (en) * | 2005-09-02 | 2007-03-08 | Thomas Magdeburger | Shared memory and shared multiplier programmable digital-filter implementation |
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2007
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Also Published As
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US7218253B2 (en) | 2007-05-15 |
US6864812B1 (en) | 2005-03-08 |
US20050175087A1 (en) | 2005-08-11 |
US20070210942A1 (en) | 2007-09-13 |
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