KR950002749B1 - Echo cancellation method and its device - Google Patents

Abstract

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Description

Echo cancellation method and device

1 is a circuit diagram of a conventional echo canceller.

2 is a circuit diagram of the echo canceller of the embodiment according to the present invention.

3 is an operation flowchart of the circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

10: delay line 20: memory line

30: adaptive processing line 40: repair circuit

50: selection circuit 60: shift circuit

70: adder 80: subtractor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full-duplex communication apparatus used for a U interface for a general information communication network, and more particularly, to a method and apparatus for removing echo data signals.

In general, the U interface for a general information communication network refers to a relay device for relaying data signals between a subscriber and a network. The U interface adopts a line coding method that varies depending on the region due to transmission error detection, signal to noise ratio, high frequency and low frequency spectrum, and bandwidth. For example, 2B1Q (2 Binary l Quaternary) track codes are used in North America, MNIS43 track codes are used in Europe, and AMI (Alternate Mark Inversion) track codes are used in Japan and Italy. do.

The full-duplex communication apparatus used for the U interface performs simultaneous transmission and reception of data signals using a hybrid circuit capable of separating incoming and outgoing signals. The echo canceller is used in the full duplex communication device of the U interface together with the hybrid circuit to remove the transmission signal included in the incoming signal, that is, the echo signal, so that the transmission signal is included in the incoming signal due to the impedance mismatch and the influence of the bridge tap.

The full-duplex communication device for the U interface uses the echo canceller shown in FIG. 1 regardless of the line coding method. The echo canceller illustrated in FIG. 1 will be described below.

x-1 delay elements (D _{1 to} Dn _-1 ), n multipliers (MT _{1 to} MTn), n filtering coefficient memories (ME _{1 to} MEn), n adaptive processing units (A 1 to An) and adders (AD) And a subtractor (SB) for detecting incoming data from which echo data has been removed by subtracting the output value of the echo data estimation unit 100 from the received data flowing from the hybrid circuit. have.

However, the echo canceller shown in FIG. 1 is multiplied by a multiplier to multiply the transmission data and the filtering coefficient, thereby reducing the efficiency of the calculation process, complicated circuit configuration, and difficulty in making one chip. The above problem is applied to the echo canceller of the full duplex communication device for the U interface regardless of the line code of the U interface.

Accordingly, an object of the present invention is to provide an echo cancellation method that can remove echo signals contained in an incoming signal by estimating echo data by a simple calculation process in a full duplex communication apparatus transmitting a line code type data signal of 2B1Q. have.

Another object of the present invention is to provide an echo cancellation device with a simple circuit configuration that can be used in a full-duplex communication apparatus for transmitting a data signal in the form of a line code of 2B1Q.

In order to achieve the above object, the method of the present invention comprises the steps of introducing the transmission data, generating the filtering coefficients of the transmission data by the transmission data and the incoming data, the step of complementary replacement of the Peterling coefficient, Selecting one of a transmission data filtering coefficient and a complement-substituted filter run coefficient according to a code state of the transmission data, selectively shifting the selected filtering coefficient according to the size of the transmission data, and selectively shifting the selected filtering coefficient Subtracting the filtering coefficient and the selected filtering coefficient to obtain an echo estimate value, and subtracting the echo estimate value from the received data to generate incoming data.

In order to achieve the above object, the apparatus of the present invention comprises a delay line including at least one delay element for delaying transmission data, and a memory corresponding to the number of transmission data delayed by the delay line in which filtering coefficients having different values are stored. Adaptive to calculate the appropriate filtering coefficient value for each transmission data delayed by the memory line consisting of the element, the delayed transmission data and the incoming data, and the filtering coefficient stored in the memory line 20, and to supply to the memory line 20. A processing circuit, a repair circuit for performing replacement of the filtering coefficients protruding from the memory line, and a filtering coefficient introduced from the memory line for each transmission data delayed by a sign bit of each delayed transmission data, Selector for selecting complementary filtering coefficients And a shift line for selectively shifting the selected filtering coefficients by one bit for each transmission data by the amplitude bits of the delayed transmission data, and adding an output of the shift line and an output of the selection line to calculate an echo estimation value. And an subtractor for generating the incoming data by subtracting the echo estimate from the received data.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Before describing the drawings presented above, a data signal encoded by the 2B1Q scheme will be described.

The 2B1Q signal combines binary information strings transmitted from a data source in two bit units and forms one symbol. The 2B1Q signal has four levels as shown in the following table.

2 is a circuit diagram of the echo canceller of the embodiment according to the present invention.

In FIG. 2, the first input terminal 5 is connected to the input terminal of the delay line 10. As shown in FIG. The first input terminal is connected to a transmission terminal of the system and a transmission data input terminal of the hybrid circuit to introduce transmission data. The output terminals of the odd bit delay elements of the delay line 10 are correspondingly coupled to the control terminal of the selection circuit 50 and one terminal of the first input port of each adaptation processing section of the adaptive processing line 30. The output terminals of the even-numbered bit delay elements of the delay line 10 are correspondingly connected to the control terminal of the shift circuit 60 and the other terminal of the first input port of each adaptive processing unit of the adaptive processing line 30. have. The input and output terminals of the adaptive processing line 30 are connected to the input and output terminals of the memory line 20. The output terminals of the memory line 20 are connected to the input terminals of the maintenance replacement circuit 40 and the first input port of the selection circuit 50. The output terminals of the maintenance replacement circuit 40 are connected to the second input port of the selection circuit 50. The output terminals of the selection circuit 50 are formed of the input terminals of the shift circuit 60 and the adder 70. 1 is connected to the input port. The output terminals of the shift circuit 60 are connected to the second input port of the adder 70. The output terminals of the adder 70 are connected to the first input port of the subtractor 80. The second input terminal 15 is connected to the reception signal transmission terminal of the hybrid circuit for introducing the reception data. The second input terminal 15 is connected to the second input terminal of the subtractor 80. The output terminal of the subtractor 80 is coupled to one output terminal of the output terminal 25 and the second input port of each of the stacking units of the stacking line 30.

FIG. 3 is a flowchart of operation of the echo canceller shown in FIG.

The operation of FIG. 2 will be described in detail according to the flow chart shown in FIG.

The delay line 10 shifts the previously inputted transmission data by 2 bits whenever the transmission data of one symbol is input through the first input terminal 5 (step 201). At this time, positive or negative sign information is stored in the odd bit delayers of the delay line 10, and amplitude information of magnitude is stored in the even bit delayers of the delay line 10. do.

The adaptive processing line 30 composed of a plurality of adaptive processing units uses an appropriate filtering coefficient value corresponding to each incoming data flowing from the delay line 10 and incoming data flowing from the subtractor 80 and each delayed transmission data. The filtering coefficient values used for the filtering are calculated, and the calculated new filtering coefficient values are applied to the memory line 20. The memory line 20 composed of a plurality of memory elements is introduced from the adaptive processing line 30. And supply the stored filtering coefficients to the maintenance circuit 40 and the selection circuit 50, wherein the filtering coefficients have different values. The repair circuit 40 composed of a plurality of complementary replacers repairs and replaces a plurality of filtering coefficients introduced from the memory line 20 to supply the plurality of repaired and substituted filtering coefficients to the selection circuit 50 (S202). step).

The selection circuit 50 composed of a plurality of control switches is provided according to a logic value of code information applied to the control terminals of the control switches from the odd bit delayers of the delay line 10 by the respective control switches. The filtering coefficients flowing from the memory line 20 or the repair-substituted filtering coefficients flowing from the repair circuit 40 are respectively selected to supply the selected filtering coefficients to the adder 70 and the shift circuit 60 (step 203). To step 205). In this case, the selected filtering coefficients may be fill-filling coefficients that are complementarily substituted for each delayed transmission data, and may be filtering coefficients output from the memory line 20. In other words, the selected filtering coefficients are mixed with the complementary substituted filtering coefficients and the filtering coefficients output from the memory line 20. In more detail, when the selection circuit 50 is described, the control switches constituting the selection circuit 50 select the complementary-substituted filtering coefficient when the code information applied to each control terminal is "0", and on the contrary, In the case of "1", the filtering coefficient flowing from the memory line 20 is selected.

The shift circuit 60, which is composed of a plurality of shift elements, is selected to flow into the selection circuit 50 according to a logic value of amplitude information applied from the even-numbered bit delayers of the delay line 10 to the control terminals, respectively. The filtering coefficients are selectively shifted by one bit and then supplied to the adder 70 together with the selected filtering coefficients. Complementing the description of the operation of selectively shifting the selectively selected filtering coefficients, amplitude information having a logic value of 1 (ie, delayed transmission data of +1 or -1) is used as a control terminal among a plurality of shift elements. The incoming shift element sets the selected filtering coefficient to "0". On the contrary, the shift element into which the amplitude information having the logic value "0" (that is, delayed transmission data of -1 or +1) is introduced into the control terminal. Shift 1 bit. The adder 70 calculates an echo estimation value by adding the selectively shifted filtering coefficient flowing from the shift circuit 60 and the selected filtering coefficient flowing from the selection circuit 50 (steps 206 to 209). ).

The subtractor 80 generates incoming call data by subtracting the received data flowing through the second input terminal 15 to the echo peripheral value applied from the adder 70 (step 210).

In the above description, transmission data refers to data transmitted to a counterpart system (subscriber or network) through a transmission line, and incoming data refers to data transmitted from a state system through a transmission line (wired). Refers to incoming data including transmission data.

As described above, the present invention obtains an echo estimation value using a repair circuit and a shift circuit to remove the echo data signal included in the received data, thereby improving the efficiency of the operation process compared to the conventional echo canceller using a multiplier. And there is an advantage that can simplify the circuit configuration and can facilitate one chip,

Claims (2)

2B1Q full-duplex communication of the data of the line code method, the method comprising: introducing transmission data, generating filtering coefficients based on the transmission data and the incoming data, and performing replacement of the fill filtering coefficients; Selecting one of a filtering coefficient and a complement-substituted filtering coefficient according to the code state of the data, selectively shifting the selected filtering coefficients according to the sizes of the transmissions, the selectively shifted filtering coefficients and the Subtracting the selected filtering coefficients to obtain an echo estimation output, and subtracting the echo estimation value from the received data to generate the incoming data; 2B1Q full-duplex communication apparatus for line code type data, comprising: a delay line including at least one base station for delaying transmission data, and the number of transmission data delayed by the delay line in which filtering coefficients having different values are stored. An adaptive processing line which is controlled by a memory line consisting of memory elements, each delayed transmission data and an incoming data, and a filtering coefficient stored in the memory line to calculate an appropriate filtering coefficient value for each delayed transmission data; And a filtering coefficient flowing from the memory line for each transmission data delayed by a code bit of each delayed transmission data of the repair circuit for replacing and replacing the filtering coefficients read from the memory line, and the replacement of the repairing coefficient from the repair circuit. To select filtering coefficients A selection line, a shift line for selectively shifting the selected filtering coefficients by one bit for each delayed transmission data by the amplitude bits of the delayed transmission data, an output of the shift line and an output of the selection line, by adding And an adder for calculating an echo estimation value and a subtractor for generating incoming data by subtracting the echo estimation value from the received data.