US7137056B2 - Low error propagation rate 32/34 trellis code - Google Patents

Low error propagation rate 32/34 trellis code Download PDF

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US7137056B2
US7137056B2 US10/253,903 US25390302A US7137056B2 US 7137056 B2 US7137056 B2 US 7137056B2 US 25390302 A US25390302 A US 25390302A US 7137056 B2 US7137056 B2 US 7137056B2
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codewords
bit
sequence
decoded
encoding
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US20040059993A1 (en
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Jonathan Ashley
William G. Bliss
Razmik Karabed
Kaichi Zhang
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Infineon Technologies AG
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Infineon Technologies North America Corp
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Priority to DE10344340A priority patent/DE10344340B4/de
Priority to CNA031598137A priority patent/CN1527202A/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes
    • H04L1/006—Trellis-coded modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Definitions

  • a compact disc is included herewith and incorporated by reference herein having thereon a computer program listing appendix in the ASCII uncompressed text format with ASCII carriage return, ASCII line feed and all control codes defined in ASCII, having computer compatibility with IBM PC/XT/AT or compatibles, having operating system compatibility with MS-Windows and including file source_code — 3234.txt of 22,800 bytes, created on Sep. 23, 2002.
  • the present invention is directed to a coding system for encoding or decoding data while minimizing propagation of any errors introduced after the encoding and before the decoding and while assuring certain properties of words encoded by the coding system.
  • Encoding typically involves transforming the data and introducing additional information to the data, where the additional information can be used during decoding to recover from or minimize the effect of discrepancies introduced by filtering, conveying, or otherwise manipulating the data after it has been encoded.
  • a coding scheme may be measured by two opposing qualities.
  • a first quality of a coding scheme is the efficiency or rate of the code, which is the amount of input data to be encoded, in proportion to the amount of the input data plus added coding information. For example, if a code adds two coding bits to a 32-bit input word, thus producing a 34-bit codeword, then the rate of the code is 32/34.
  • a low coding rate naturally leads to an efficient rate of conveying the input data, because less total information must be conveyed per unit of input data that is conveyed.
  • a second quality of a coding scheme is the degree to which the added coding information facilitates recovery from or minimization of errors introduced during conveyance. There is a tension between these two coding qualities.
  • FIG. 1 shows a system for using the 32/34 code of the present invention.
  • FIG. 2 shows an example of a trellis 120 of a Viterbi detector.
  • FIG. 3 shows a table 180 describing independently the map FL in terms of mapping a vector (x 1 . . . x 16 ) to a vector (y 1 . . . y 16 z).
  • FIG. 4 shows a table 200 describing the map FR independently in terms of mapping a (x 1 . . . x 16 ) to a vector (y 1 . . . y 16 z).
  • FIG. 5 shows a table 210 that describes a mapping using the maps FL and FR, in terms of input vector d and output vector c.
  • FIG. 6A shows a table 220 describing the map FL ⁇ 1 .
  • FIGS. 6A–6B show further details of the map FL ⁇ 1 .
  • FIG. 7A shows a table 230 describing the map FR ⁇ 1 .
  • FIGS. 7A–7B show further details of the map FR ⁇ 1 .
  • FIG. 8 shows a table 240 describing the mapping of the decoder 114 .
  • FIG. 1 shows a system for using the 32/34 code of the present invention.
  • the pre-conveying half of the system in FIG. 1 may be summarized as: b ⁇ c ⁇ d ⁇ y, where b is encoded to c, c is precoded to d, and d is filtered to y.
  • An encoder 100 receives 32 bits of input data (b 1 . . . b 32 ), where (b 1 . . . b 32 ) denotes a vector or word of 32 bits.
  • the encoder 100 encodes the input data, and outputs 34 bits of encoded data (c 1 . . . c 34 ).
  • a precoder 102 receives the encoded output (c 1 . . .
  • a channel filter 104 receives the sequence (d 1 . . . d 34 ), performs another state transformation based on the sequence (d 1 . . . d 34 ), and outputs resulting sequence (y 1 . . . y 34 ).
  • the data y is then subjected to potential noise at a conveyance stage 106 .
  • the conveyance stage 106 may randomly perturb the symbols in sequence (y 1 . . . y 34 ), thus producing sequence (r 1 . . . r 34 ).
  • sequence (r 1 . . . r 34 ) For each symbol y(i) in word (y 1 . . . y 34 ), there is some probability (usually random) that the conveyance stage 106 will perturb y(i) with noise error n(i).
  • the sequence (r 1 . . . r 34 ) is often called the received sequence.
  • the post-conveying half of the system in FIG. 1 may be summarized as: r ⁇ y′ ⁇ d′ ⁇ c′ ⁇ b′, where r is Viterbi-detected to y′, y′ is filtered to d′, d′ is inverse-precoded to c′, and c′ is decoded to b′.
  • the detector 108 generally a Viterbi detector, receives the possibly perturbed sequence (r 1 . . . r 34 ) and produces (y′ 1 . . . y′ 34 ), which is a reconstruction of (y 1 . . . y 34 ) with possibly one or more bits in error or perturbed.
  • y′(i) is in error, i.e. when y′(i) ⁇ y(i)
  • Channel output error events are typically attributable to noise n.
  • An inverse channel filter 110 receives y′ and transforms (y′ 1 . . . y′ 34 ) to (d′ 1 . . . d′ 34 ).
  • An inverse-precoder 112 receives d′ and transforms (d′ 1 . . . d′ 34 ) to (c′ 1 . . . c′ 34 ) by performing the inverse of the precoder 102 .
  • a bit of d′ say d′(j) differs from its corresponding original bit d(j)
  • a channel input error event is said to have occurred.
  • a channel input error event filtered by the channel filter leads to a corresponding channel output error event.
  • both channel input error events and channel output error events can cross codeword boundaries.
  • the decoder 114 receives (c′ 1 . . . c′ 34 ), applies an inverse of the coder 100 , and outputs a reproduction (b′ 1 . . . b′ 32 ) of the input data (b 1 . . . b 32 ), where some reproduced or decoded bits in b′ may be in error. That is to say, for some original bits b(i) and corresponding reproduced bits b′(i), it is possible that b′(i) ⁇ b(i). Errors in the reproduced data b′ are generally propagations of one or more errors received in c′ and are referred to hereafter as decoder output errors.
  • the functionality of the detector 108 , the inverse channel filter 110 , and the inverse-precoder 112 may have various arrangements.
  • the Viterbi detector 108 may be constructed to include the functionality of the channel filter 110 , the inverse-precoder 112 , or both.
  • An aspect of the present invention is that typical errors going into the decoder result in short errors being outputted by the decoder.
  • an error received by the decoder is propagated to the output of the decoder.
  • the error propagation of a decoder can be understood in terms of the number of output bytes that are in error due to a typical or expected input error.
  • typical short decoder input errors result in short decoder output errors. That is to say, the 32/34 code of the present invention guarantees that small decoder input errors (or input errors within a certain range) result in decoder output errors of no more than 4 bytes, even in the case where an input error crosses a boundary between two codewords. There are some typical error events cross codeword boundaries, in which case it is desirable that both codewords are not entirely corrupted. Typical cross-boundary errors are required to propagate to no more than 4 bytes between the two relevant codewords.
  • errors received and propagated by the decoder are no more than 4 data bytes for all closed error events having squared-distance ⁇ 1.5 ⁇ d mfb 2 , where d mfb 2 is the squared-distance of the matched filter bound (property 6 in the SUMMARY). This property is discussed in detail later.
  • FIG. 2 shows an example of a trellis 120 of a Viterbi detector.
  • the trellis 120 shown in FIG. 2 is referred to only for discussion and its particular construction is not used with the present coding system.
  • Path 122 represents an original or true path 122 .
  • Path 124 represents a detected path 124 corresponding to original path 122 , but where some of y′ bits deviate from their original path 122 .
  • the area 126 is a closed error event, sometimes called a diamond.
  • a closed error event or diamond is a sequence of trellis transitions where the actual transitions through the trellis diverge from the original transitions, and after some transitions the actual transition path returns to the true original transition path.
  • the squared-distance of an error event or diamond is
  • ⁇ i p q ⁇ ⁇ ( y i - y ′ i ) 2 , where p and q are the bounds of an error event.
  • a trellis is a deterministic state machine, and possible error events or diamonds on a trellis can be predicted in advance.
  • d mfb 2 Given a set of likely closed error events for the filter, d mfb 2 can be used to define a maximum squared-distance that will result from one of those closed error events.
  • d min 2 a minimum distance over all error events coming from a trellis.
  • d min 2 is generally the same as d mfb 2 , but may be less for some filters.
  • the encoder 100 maps 32-bit input words to 34-bit codewords.
  • the encoder maps input words to codewords using two maps; FL and FR.
  • One half (16 bits) of each input word is mapped using the FL map, and the other half (16 bits) is mapped using the FR map.
  • FIG. 3 shows a table 180 describing independently the map FL in terms of mapping a vector (x 1 . . . x 16 ) to a vector (y 1 . . . y 16 z).
  • FIG. 4 shows a table 200 describing the map FR independently in terms of mapping a (x 1 . . . x 16 ) to a vector (y 1 . . . y 16 z).
  • mapping a vector (d( 1 , 1 ) d( 1 , 2 ) . . . d( 1 , 16 )) (d( 2 , 1 ) d( 2 , 3 ) . . . d( 2 , 16 )) to a vector (c( 1 , 1 ) c( 1 , 2 ) . . . c( 1 , 16 ) q c( 2 , 1 ) c( 2 , 2 ) . . . c( 2 , 16 ) p).
  • a vector (d( 1 , 1 ) d( 1 , 2 ) . . . d( 1 , 16 )) (d( 2 , 1 ) d( 2 , 3 ) . . . d( 2 , 16 )) to a vector (c( 1 , 1 ) c( 1 , 2 ) . . . c( 1 ,
  • the vectors to which the exemplary x is mapped to are defined according to rows 4 of the tables 180 , 200 .
  • the map FL will map x to the 17-bit vector (g 1 g 2 g 3 g 4 h 1 h 2 h 3 h 4 0 0 0 1 1 1 0 0 0), and the map FR will map x to the 17-bit vector (0 0 0 1 1 1 0 0 g 1 g 2 g 3 g 4 h 1 h 2 h 3 h 4 0).
  • FIG. 5 shows a table 210 that describes a mapping using the maps FL and FR, in terms of input vector d and output vector c.
  • the maps FL and FR are used together to define the mapping of the encoder 100 . If codeword (d( 1 , 1 ) d( 1 , 2 ) . . . d( 1 , 16 )), (d( 2 , 1 ) d( 2 , 2 ) . . . d( 2 , 16 )) is to be encoded, then FL is used to map (d( 1 , 1 ) . . . d( 1 , 16 )) to (a 1 . . .
  • FR is used to map (d( 2 , 1 ) d( 2 , 2 ) . . . d( 2 , 16 )) to (b 1 b 2 . . . b 16 e 2 ).
  • the precoder 102 is a finite state machine. Assuming an input of c, an output of d, and time n, then the states of the precoder 102 are:
  • the channel filter 104 receives (d 1 . . . d 34 ).
  • Other filters may also be used.
  • the decoder 114 maps 34-bit codeword reproductions (c′) to 32-bit reproductions of the input words (b′).
  • the decoder maps codeword reproductions (c′) to input word reproductions (b′) using two maps FL ⁇ 1 and FR ⁇ 1 ; the inverses of maps FL and FR.
  • the first 16 bits of an input word reproduction (a decoded codeword) are generated using the FL ⁇ 1 map, and the last 16 bits of an input word reproduction (a decoded codeword) are mapped using the FR ⁇ 1 map.
  • the maps FL ⁇ 1 and FR ⁇ 1 are described generically below in terms of mapping an input vector (y 1 . . . y 16 z) to an output vector (x 1 . . . x 16 ).
  • mapping input vector (c( 1 , 1 ) c( 1 , 2 ) . . . c( 1 , 16 )) q (c( 2 , 1 ) c( 2 , 2 ) . . . c( 2 , 16 ) p) to output vector (d( 1 , 1 ) d( 1 , 2 ) . . . d( 1 , 16 )) (d( 2 , 1 ) d( 2 , 3 ) . . . d( 2 , 16 )).
  • mapping input vector (c( 1 , 1 ) c( 1 , 2 ) . . . c( 1 , 16 )) q (c( 2 , 1 ) c( 2 , 2 ) . . . c( 2 , 16 ) p) to output vector (d( 1 , 1 ) d( 1 , 2 ) . . . d( 1
  • FIG. 6A shows a table 220 describing the map FL ⁇ 1 .
  • FIGS. 6A–6B show further details of the map FL ⁇ 1 .
  • the map FL ⁇ 1 maps 17 bits (y 1 . . . y 16 z) to 16 bits, (x 1 . . . x 16 ).
  • FIG. 7A shows a table 230 describing the map FR ⁇ 1 .
  • FIGS. 7A–7B show further details of the map FR ⁇ 1 .
  • the map FR ⁇ 1 maps 17 bits (y 1 . . . y 16 z) to 16 bits, (x 1 . . . x 16 ).
  • FIG. 8 shows a table 240 describing the mapping of the decoder 114 .
  • the first 16 bits of the decoded word (d( 1 , 1 ) d( 1 , 2 ) . . . d( 1 , 16 )) are generated using map FL ⁇ 1
  • the later 16 bits of the decoded word are generated using map FR ⁇ 1
  • the input of the inverse maps is based on the conditions in the first column of table 240 .
  • the input c′ and output b′ of decoder 114 in FIG. 1 respectively correspond to vectors (c( 1 , 1 ) c( 1 , 2 ) . . .
  • One advantage of property 3 is that a clock can be adjusted using 1's in a codeword. The same property holds if two consecutive filters are used (e.g. (1 ⁇ D) 2 ⁇ a+bD+cD 2 ), using non-zero output values of the filters.
  • the present invention has been described with respect to a coding system exhibiting various combinations of the properties mentioned above.
  • the invention may be used in magnetic storage systems, data transmission systems, and the like, to improve data throughput and to reduce errors.
  • the many features and advantages of the invention are apparent from the detailed specification and, thus, it is intended by the appended claims to cover all such features and advantages of the invention that fall within the true spirit and scope of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

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US10/253,903 2002-09-25 2002-09-25 Low error propagation rate 32/34 trellis code Expired - Fee Related US7137056B2 (en)

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US10/253,903 US7137056B2 (en) 2002-09-25 2002-09-25 Low error propagation rate 32/34 trellis code
DE10344340A DE10344340B4 (de) 2002-09-25 2003-09-24 31/34 Trelliscode mit geringer Fehlerausbreitung
CNA031598137A CN1527202A (zh) 2002-09-25 2003-09-25 低误差传播率32/34格子码

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080055125A1 (en) * 2005-06-30 2008-03-06 Cideciyan Roy D Data storage systems

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US7486456B2 (en) * 2004-12-17 2009-02-03 Stmicroelectronics, Inc. Finite field based short error propagation modulation codes
US7490284B2 (en) * 2005-02-03 2009-02-10 Broadcom Corporation Meta-Viterbi algorithm for use in communication systems
US7469373B2 (en) * 2005-02-17 2008-12-23 Broadcom Corporation Application of a Meta-Viterbi algorithm for communication systems without intersymbol interference

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US4486739A (en) * 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
US4618955A (en) * 1983-02-25 1986-10-21 U.S. Philips Corporation Digital data transmission system
US6456208B1 (en) * 2000-06-30 2002-09-24 Marvell International, Ltd. Technique to construct 32/33 and other RLL codes
US6753797B2 (en) * 2002-09-25 2004-06-22 Infineon Technologies Ag Multiproperty 16/17 trellis code
US6920604B2 (en) * 2002-04-08 2005-07-19 Galazar Networks, Inc. Systems and methods for high speed serial encoding and decoding for data and control interfaces

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WO2001080238A1 (en) * 2000-04-05 2001-10-25 Infineon Technologies North America Corp. Improved read/write channel

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
US4486739A (en) * 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
US4618955A (en) * 1983-02-25 1986-10-21 U.S. Philips Corporation Digital data transmission system
US6456208B1 (en) * 2000-06-30 2002-09-24 Marvell International, Ltd. Technique to construct 32/33 and other RLL codes
US6920604B2 (en) * 2002-04-08 2005-07-19 Galazar Networks, Inc. Systems and methods for high speed serial encoding and decoding for data and control interfaces
US6753797B2 (en) * 2002-09-25 2004-06-22 Infineon Technologies Ag Multiproperty 16/17 trellis code

Cited By (2)

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Publication number Priority date Publication date Assignee Title
US20080055125A1 (en) * 2005-06-30 2008-03-06 Cideciyan Roy D Data storage systems
US8276038B2 (en) * 2007-08-03 2012-09-25 International Business Machines Corporation Data storage systems

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DE10344340A1 (de) 2004-06-24
CN1527202A (zh) 2004-09-08
DE10344340B4 (de) 2009-04-02

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