US7049248B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- US7049248B2 US7049248B2 US10/876,489 US87648904A US7049248B2 US 7049248 B2 US7049248 B2 US 7049248B2 US 87648904 A US87648904 A US 87648904A US 7049248 B2 US7049248 B2 US 7049248B2
- Authority
- US
- United States
- Prior art keywords
- nitride film
- film
- ion
- cleaning process
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 14
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 12
- 239000007943 implant Substances 0.000 claims description 12
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 27
- 238000000151 deposition Methods 0.000 abstract description 14
- 230000008021 deposition Effects 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 abstract description 12
- 230000003247 decreasing effect Effects 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
Definitions
- the present invention relates to method for manufacturing semiconductor device, and in particular to a improved method for manufacturing semiconductor device, wherein a cleaning process of a buffer layer is performed prior to a formation of a nitride film so that a decrease in a deposition thickness of the nitride film is prevented even when the time between the formation of the buffer layer and the formation of the nitride film is long to improve a reliability of the device.
- the thickness of the film deposited in the device is also reduced.
- a nitride film for gate spacer is deposited directly on a semiconductor substrate, characteristic of the device is degraded due to a stress of the nitride film on the semiconductor substrate during subsequent thermal processes.
- a buffer layer between the semiconductor substrate and the nitride film has been proposed.
- the deposition thickness of the nitride film is drastically decreased.
- the dose of ion-implant for adjusting threshold voltage must be increased to prevent decrease of cell threshold voltage due to a short channel effect.
- the increase in the dose to adjust threshold voltage not only results in increase in resistance and a coulomb fail but also increase in write time and an increase in leakage current due to reduction in high concentration source/drain junction region and depletion region. Moreover, a refresh time is also decreased.
- a method for manufacturing semiconductor device comprising:
- FIGS. 1A through 1D are cross-sectional diagrams illustrating the method for manufacturing semiconductor device in accordance with the present invention.
- FIG. 2 is a graph illustrating an experiment data of refresh time and write time.
- FIGS. 1A through 1D are cross-sectional diagrams illustrating the method for manufacturing semiconductor device in accordance with the present invention.
- the active region 14 is subjected to an ion-implant process for adjusting threshold voltage.
- the ion-implant process may be tilt ion-implant process performed at a tilt angle ranging from 0 to 60° and at a dose ranging from 1.55E13 to 1.65E13 ions/cm 2 .
- the ion-implant process is preferably performed at an orientation ranging from 0 to 90° by rotating 0 to 4 times.
- the dose is 5 to 10% less than that of the conventional method. This is possible because the characteristic of the interface between a TEOS film and a Si 3 N 4 film is improved due to the cleaning process, thereby preventing a reduction of threshold voltage although the dose is less than that of the conventional method.
- a gate electrode 16 is formed on the semiconductor substrate 10 .
- a TEOS film 18 which is a buffer layer, is formed on the semiconductor substrate 10 via a LPCVD method.
- the semiconductor substrate 10 is subjected to a cleaning process.
- the cleaning process is performed using a solution selected from a group consisting of a H 2 SO 4 solution, a SC-1 solution or combinations thereof.
- the H 2 SO 4 solution preferably has a volume ratio of H 2 SO 4 to H 2 O ranging from 1:4 to 1:50.
- SC-1 solution comprises NH 4 OH, H 2 O 2 and de-ionized water.
- a Si 3 N 4 film 20 for gate spacer is formed on the semiconductor substrate 10 via a CVD method. As described above, the cleaning process improves a deposition thickness of the Si 3 N 4 film 20 .
- FIG. 2 is a graph illustrating an experiment data of a refresh time and a write time, wherein a variation of the refresh time and the write time according to a variation of the dose in ion-implant process for adjusting threshold voltage.
- the refresh time (at the left) is increased as the dose is decreased and the write time is decreased as the dose is decreased. That is, after the cleaning process is performed, the device characteristics are significantly improved by an ion-implantation process with a reduced dose compared with the dose of the conventional method.
- the delay time which is the period between the time of deposition of the TEOS film and the time of deposition of the nitride film, and the thickness of the deposited nitride film with and without the cleaning process are shown in Table 1.
- nitride film having a desired thickness of 90 ⁇ is shown.
- the nitride film is deposited after 10 hours and 5 days, respectively, from the time of deposition of the TEOS film having a thickness of 100 ⁇ with and without the cleaning process (R denotes a cleaning process performed using a H 2 SO 4 solution and N denotes a cleaning process performed using a SC-1 solution).
- the nitride film deposited after 10 hours from the time of deposition of the TEOS film without the cleaning process has an average thickness of 76.9 ⁇ , while the nitride film with the cleaning process has an average thickness of 82.6 ⁇ .
- the nitride film deposited after 5 days from the time of deposition of the TEOS film without the cleaning process has an average thickness of 69.3 ⁇ , while the nitride film with the cleaning process has an average thickness of 82.7 ⁇ .
- the deposition thickness is drastically decreased form 76.9 ⁇ to 69.3 ⁇ when the cleaning process is not performed.
- the deposition thicknesses are almost the same when the cleaning process is performed.
- Id sat is increased by 2.3 ⁇ A
- BV dss by 0.1V
- GIDLBV by 0.2V.
- refresh time is improved by 20 ms and write time by 3 ns.
- a cleaning process of a buffer layer is performed prior to a formation of a nitride film so that a decrease in a deposition thickness of the nitride film is prevented even when the time between the formation of the buffer layer and the formation of the nitride film is long to improve a reliability of the device.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
Description
-
- forming an active region defined by a device isolation film on a semiconductor substrate,
- subjecting the active region to an ion-implant process for adjusting therehold voltage,
- forming a gate electrode on the semiconductor substrate,
- forming a TEOS film on the semiconductor substrate by a LPCVD method,
- subjecting the surface of the TEOS film to a cleaning process using a solution selected from the group consisting of H2SO4 solution, SC-1 solution and combination thereof, and
- forming Si3N4 film serving as a gate spacer on the TEOS film by a CVD method.
TABLE 1 | ||
|
100 Å |
Delay |
10 hrs. | 5 days |
Cleaning | RN | RN |
Nitride film | 90 Å |
Thickness | AVG | 82.6 | 76.9 | 82.7 | 69.3 |
of the | MAX | 84.1 | 79.0 | 84.0 | 75.1 |
nitride | MIN | 81.5 | 75.2 | 81.7 | 67.1 |
film | MAX − MIN | 2.6 | 3.8 | 2.3 | 8.0 |
TABLE 1 | |||||
Cell Vt imp. | 1.70E13 | 1.60E13 |
Cleaning | Skip | • | |||
RN | • | • |
Vtsat(V) | 0.741 | 0.787 | 0.740 | ||
Idsat(μA) | 37.7 | 36.3 | 39 | ||
BVdss(V) | 5.0 | 5.0 | 5.1 | ||
GIDLBV(V) | 4.4 | 4.4 | 4.6 | ||
Refresh(ms) | 130 | 130 | 150 | ||
tWR(ns) | 7 | 7 | 4.1 | ||
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2003-0097454 | 2003-12-26 | ||
KR10-2003-0097454A KR100520628B1 (en) | 2003-12-26 | 2003-12-26 | Method for fabricating semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050142893A1 US20050142893A1 (en) | 2005-06-30 |
US7049248B2 true US7049248B2 (en) | 2006-05-23 |
Family
ID=34698525
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/876,489 Expired - Fee Related US7049248B2 (en) | 2003-12-26 | 2004-06-28 | Method for manufacturing semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (1) | US7049248B2 (en) |
KR (1) | KR100520628B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100161073A1 (en) * | 2008-07-28 | 2010-06-24 | Zimmer, Inc. | Mosaicplasty constructs |
US9997530B2 (en) | 2014-06-23 | 2018-06-12 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory device and method of fabricating the same |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0346224A (en) | 1989-07-03 | 1991-02-27 | Motorola Inc | Manufacture of mesfet |
JPH03276718A (en) | 1990-03-27 | 1991-12-06 | Fujitsu Ltd | Manufacture of semiconductor device |
US5936300A (en) * | 1996-03-25 | 1999-08-10 | Sanyo Electric Co., Ltd. | Semiconductor device with film covering |
US6010936A (en) * | 1996-11-27 | 2000-01-04 | Lg Semicon Co., Ltd. | Semiconductor device fabrication method |
US6037204A (en) | 1998-08-07 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Silicon and arsenic double implanted pre-amorphization process for salicide technology |
US6074919A (en) | 1999-01-20 | 2000-06-13 | Advanced Micro Devices, Inc. | Method of forming an ultrathin gate dielectric |
US6083795A (en) | 1998-02-09 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Large angle channel threshold implant for improving reverse narrow width effect |
US6180543B1 (en) | 1999-07-06 | 2001-01-30 | Taiwan Semiconductor Manufacturing Company | Method of generating two nitrogen concentration peak profiles in gate oxide |
US6232164B1 (en) | 1999-05-24 | 2001-05-15 | Taiwan Semiconductor Manufacturing Company | Process of making CMOS device structure having an anti-SCE block implant |
US6294448B1 (en) | 2000-01-18 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method to improve TiSix salicide formation |
US6626967B2 (en) * | 2001-10-31 | 2003-09-30 | Fujimi Incorporated | Polishing composition and polishing method employing it |
US6683356B2 (en) | 2001-06-04 | 2004-01-27 | Kabushiki Kaisha Toshiba | Semiconductor device with oxygen doped regions |
US6858543B2 (en) * | 2003-06-27 | 2005-02-22 | Hynix Semiconductor Inc. | Method of forming tunnel oxide film in semiconductor device |
-
2003
- 2003-12-26 KR KR10-2003-0097454A patent/KR100520628B1/en not_active IP Right Cessation
-
2004
- 2004-06-28 US US10/876,489 patent/US7049248B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0346224A (en) | 1989-07-03 | 1991-02-27 | Motorola Inc | Manufacture of mesfet |
JPH03276718A (en) | 1990-03-27 | 1991-12-06 | Fujitsu Ltd | Manufacture of semiconductor device |
US5936300A (en) * | 1996-03-25 | 1999-08-10 | Sanyo Electric Co., Ltd. | Semiconductor device with film covering |
US6010936A (en) * | 1996-11-27 | 2000-01-04 | Lg Semicon Co., Ltd. | Semiconductor device fabrication method |
US6083795A (en) | 1998-02-09 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Large angle channel threshold implant for improving reverse narrow width effect |
US6037204A (en) | 1998-08-07 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Silicon and arsenic double implanted pre-amorphization process for salicide technology |
US6074919A (en) | 1999-01-20 | 2000-06-13 | Advanced Micro Devices, Inc. | Method of forming an ultrathin gate dielectric |
US6232164B1 (en) | 1999-05-24 | 2001-05-15 | Taiwan Semiconductor Manufacturing Company | Process of making CMOS device structure having an anti-SCE block implant |
US6180543B1 (en) | 1999-07-06 | 2001-01-30 | Taiwan Semiconductor Manufacturing Company | Method of generating two nitrogen concentration peak profiles in gate oxide |
US6294448B1 (en) | 2000-01-18 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method to improve TiSix salicide formation |
US6683356B2 (en) | 2001-06-04 | 2004-01-27 | Kabushiki Kaisha Toshiba | Semiconductor device with oxygen doped regions |
US6626967B2 (en) * | 2001-10-31 | 2003-09-30 | Fujimi Incorporated | Polishing composition and polishing method employing it |
US6858543B2 (en) * | 2003-06-27 | 2005-02-22 | Hynix Semiconductor Inc. | Method of forming tunnel oxide film in semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100161073A1 (en) * | 2008-07-28 | 2010-06-24 | Zimmer, Inc. | Mosaicplasty constructs |
US9289302B2 (en) | 2008-07-28 | 2016-03-22 | Zimmer, Inc. | Mosaicplasty constructs |
US9997530B2 (en) | 2014-06-23 | 2018-06-12 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory device and method of fabricating the same |
US10658375B2 (en) | 2014-06-23 | 2020-05-19 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory device and method of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US20050142893A1 (en) | 2005-06-30 |
KR20050066202A (en) | 2005-06-30 |
KR100520628B1 (en) | 2005-10-13 |
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