US7046040B2 - Bootstrap driver - Google Patents

Bootstrap driver Download PDF

Info

Publication number
US7046040B2
US7046040B2 US10/902,502 US90250204A US7046040B2 US 7046040 B2 US7046040 B2 US 7046040B2 US 90250204 A US90250204 A US 90250204A US 7046040 B2 US7046040 B2 US 7046040B2
Authority
US
United States
Prior art keywords
output
terminal
voltage regulator
transistor
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US10/902,502
Other languages
English (en)
Other versions
US20050110556A1 (en
Inventor
Yannick Guedon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microelectronic Innovations LLC
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Assigned to STMICROELECTRONICS S.A. reassignment STMICROELECTRONICS S.A. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GUEDON, YANNICK
Publication of US20050110556A1 publication Critical patent/US20050110556A1/en
Application granted granted Critical
Publication of US7046040B2 publication Critical patent/US7046040B2/en
Assigned to STMICROELECTRONICS INTERNATIONAL NV reassignment STMICROELECTRONICS INTERNATIONAL NV ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS SA
Assigned to FRANCE BREVETS reassignment FRANCE BREVETS ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS INTERNATIONAL NV
Assigned to MICROELECTRONIC INNOVATIONS, LLC reassignment MICROELECTRONIC INNOVATIONS, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FRANCE BREVETS
Assigned to MICROELECTRONIC INNOVATIONS, LLC reassignment MICROELECTRONIC INNOVATIONS, LLC CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 060161 FRAME: 0346. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: FRANCE BREVETS
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back

Definitions

  • the present invention relates to a bootstrap driver, comprising a power output stage for supplying a load in a full-bridge or half-bridge configuration.
  • BCD bipolar/CMOS/DMOS
  • screens such as CRTs (cathode-ray tubes), computer monitors or television screens, as well as in full-bridge or half-bridge bootstrap systems.
  • FIG. 1 illustrates the working principle of an example of a power output stage, which is suitable for a half-bridge supply.
  • This output stage 30 comprises a high-side transistor MHS and a low-side transistor MLS, which are arranged in series between a positive supply terminal 1 , to which a positive potential +Vcc is applied, and a negative supply terminal 2 , to which a negative potential ⁇ Vcc is applied.
  • the transistors MHS and MLS are for example VDMOS (vertical double-diffused metal-oxide semiconductor) or LDMOS (lateral double-diffused metal-oxide semiconductor) transistors.
  • the voltages referred to below are expressed in relation to the potential ⁇ Vcc.
  • the transistors MHS and MLS are generally both N-type transistors, for example NPN bipolar transistors, or N-type MOS transistors (NMOS transistors) as in the example which is represented.
  • the source of the transistor MHS and the drain of the transistor MLS are connected together, this common node between them forming an output node OUT of the drive circuit, which delivers an output voltage Vout.
  • the drain of the transistor MHS is connected to the terminal 1 and the source of the transistor MLS is connected to the terminal 2 .
  • the output OUT switches between a low state and a high state, corresponding respectively to potentials ⁇ Vcc and +Vcc at this node.
  • the potential at the control gate of transistor MHS must become about 10 V higher than the potential at its source (V Gs ⁇ 10V) when the output OUT changes from the low state to the high state. It therefore needs to become higher than the potential +Vcc. It is conventional to use the bootstrapping technique for this.
  • FIG. 2 illustrates an example of a bootstrap driver.
  • the driver comprises a voltage regulator 3 arranged between the terminal 2 and a regulated-voltage node A.
  • the regulator 3 delivers a regulated voltage Vreg from which control voltages are obtained, these being applied to the control gates of the transistors MHS and MLS.
  • the driver also comprises a high-side control circuit HSD (standing for “high-side driver”) for controlling the transistor MHS, and low-side control circuit LSD (standing for “low-side driver”) for controlling the transistor MLS.
  • HSD high-side driver
  • LSD low-side control circuit
  • the circuit LSD is supplied between the voltages ⁇ Vcc and Vreg, and receives a control signal X.
  • the circuit HSD is supplied between the voltages Vout and Vboot, where the Vout is the voltage at the output terminal OUT and Vboot is a voltage corresponding substantially to the voltage Vout boosted by the voltage Vreg, and it receives a control signal ⁇ overscore (X) ⁇ which is the logical inverse of the signal X.
  • the voltage Vreg is available at the node A.
  • the voltage Vboot is available at the boost-voltage node B.
  • the driver In order to generate the voltage Vboot, the driver also comprises a bootstrap diode Dboot, which is connected by its anode to the node A and by its cathode to the node B, as well as a so-called bootstrap capacitance Cboot connected between the node B and the output node OUT.
  • Dboot bootstrap diode
  • Cboot bootstrap capacitance
  • the bootstrap driver operates in the following way.
  • the diode Dboot conducts some of the current necessary for charging the gate of the transistor MHS while the output node OUT is still at the potential ⁇ Vcc, the rest of this current being obtained later by discharging the capacitance Cboot.
  • the diode Dboot then stores charges.
  • t B the voltage Vout is increasing towards +Vcc so that the voltage Vout at the output node OUT exhibits a variation
  • I _ rev I _ ⁇ ⁇ t B .
  • the reverse current ⁇ rev then flows via the anode of the diode Dboot to the node A. An overvoltage will then be produced at the node A if no low-impedance path is available to the reverse current ⁇ rev , especially if the regulator cannot absorb this current.
  • a capacitance may be provided for decoupling this regulator 3 , so as to provide a low-impedance path leading to the negative supply terminal 2 .
  • this decoupling capacitance needs to have a relatively high value (substantially equal to 100 nF).
  • the overvoltage across the terminals of a 100 nF decoupling capacitance is only
  • One embodiment of the invention provides a bootstrap driver which overcomes the aforementioned drawbacks.
  • the bootstrap driver includes:
  • the driver resolves the problem in question by using two independent regulators, one generating the voltage Vreg for supplying the control circuit LSD, and optionally logic circuits of the system, and the other generating a boosted voltage specifically for supplying the high-side control circuit HSD, this regulator being protected against the overvoltage by the recovery diode, which returns the reverse current of the bootstrap diode to the positive supply terminal when the output voltage rises to +Vcc.
  • this solution does not require any control logic.
  • the energy stored in the bootstrap diode Dboot is recovered since it is returned to the positive supply terminal via the protective diode. This is particularly advantageous in applications where the system is supplied by a battery.
  • FIG. 1 is a diagram of a power output stage with NMOS transistors
  • FIG. 2 is a diagram of an example of a bootstrap driver illustrating the principle of the bootstrap technique
  • FIG. 3 is a diagram of an example of a bootstrap driver according to one embodiment of the invention.
  • FIG. 4 is a diagram of an exemplary embodiment of two voltage regulators according to the invention.
  • FIG. 5 and FIG. 6 are curves illustrating the way in which the voltage regulator operates in order to generate the boosted voltage according to one embodiment of the invention.
  • FIG. 3 shows an exemplary embodiment of a bootstrap driver according to the invention.
  • the driver comprises an output stage 30 , for example similar to one described in the introduction with reference to the diagram in FIG. 1 .
  • This stage has an N-type high-side transistor MHS and a low-side transistor MLS, also of the N-type, which are arranged in series with one another between the positive supply terminal 1 and the negative supply terminal 2 .
  • the potential ⁇ Vcc is equal to ⁇ 18 V and the potential +Vcc is equal to +18 V.
  • the output OUT of the circuit is tapped from the common node between these transistors MHS and MLS, and delivers the output signal Vout.
  • This output stage is suitable for supplying a load in a half-bridge configuration, that is one such that the load is connected between the output OUT and a terminal delivering a potential intermediate between the potentials ⁇ Vcc and +Vcc, for example a reference-earth potential.
  • the invention is not limited to a half-bridge supply, but can easily be generalized to a full-bridge supply in which the load is connected in floating mode between the respective outputs of two stages similar to the stage 30 .
  • the driver also comprises a control circuit HSD for controlling the transistor MHS and a control circuit LSD for controlling the transistor MLS. According to one embodiment of the invention, the respective supplies of these two control circuits are independent.
  • the driver contains one voltage regulator 10 having an output which delivers a voltage Vregboot for supplying the control circuit HSD, and another voltage regulator 20 having an output which delivers a voltage Vreg for supplying the control circuit LSD.
  • These regulators 10 and 20 are mutually independent, that is to say there is no coupling between them.
  • the regulator 10 is connected between the negative supply terminal 2 and a terminal S 1 .
  • the regulator 20 is connected between the negative supply terminal 2 and a terminal S 2 .
  • the control circuit HSD is supplied between the output terminal OUT and the node B, and the control circuit LSD is supplied between the terminals 2 and S 2 .
  • the drive circuit also comprises a bootstrap capacitance Cboot arranged between the output OUT of the circuit and the boost-voltage node B, as well as a bootstrap diode Dboot connected by its anode to the output S 1 of the voltage regulator 10 and by its cathode to the node B.
  • the capacitance Cboot and the diode Dboot form bootstrap means.
  • the driver also comprises a recovery diode Drec connected by its anode to the output of the overvoltage regulator 10 and by its cathode to the positive supply terminal 1 .
  • the function of this recovery diode Drec is to conduct the reverse current of the diode Dboot when the output OUT of the drive circuit switches from the low state, in which the transistor MLS is on and the transistor MHS is off, to the high state in which the transistor MLS is off and the transistor MHS is on.
  • the diode Drec turns itself on automatically, that is without the intervention of any control logic. Furthermore, the reverse current of the diode Dboot is not lost but is re-injected to the positive supply terminal 1 . This energy recovery is particularly beneficial for applications of the invention to battery-operated systems.
  • control circuit HSD is supplied by the regulator 10 , which is separate from and independent of the regulator 20 used for supplying the control circuit LSD. Specifically, this allows the circuits supplied by the regulator 20 , which include the control circuit LSD and optionally logic circuits (not shown) of the system, to be protected against the overvoltage which is produced at the anode of the bootstrap diode Dboot when the output OUT switches to the high state.
  • the regulator 20 comprises two branches in parallel between the positive and negative supply terminals, 1 and 2 respectively.
  • a first branch comprises a Zener diode DZ 2 , for example a 12 V Zener diode, which is connected to the terminal 2 by its anode and to the terminal 1 by its cathode via a leakage resistor Rc 2 , for example a 150 k ⁇ resistor.
  • the function of this branch is to generate a regulated voltage, which is equal to 12 V in the example.
  • a second branch, forming the output stage of the regulator 20 comprises an output transistor M 2 in series with a resistor Rp 2 .
  • This output stage is a follower, the function of which is to draw the large current necessary for supplying the control circuit LSD.
  • the transistor M 2 may be a MOS transistor, in particular an NMOS, for example an LDMOS which has the advantage of withstanding high voltages.
  • the control gate of M 2 is connected to the cathode of the Zener diode DZ 2 .
  • the output of the regulator 20 which delivers the regulated voltage Vreg, is tapped from the source of the resistor M 2 , which is connected to the terminal 2 through the resistor Rp 2 , the drain of M 2 being connected to the terminal 1 .
  • the regulator 10 has basically the same structure as the regulator 20 . The description of this structure is not repeated here. It will merely be pointed out that the components M 2 , Rp 2 , DZ 2 and Rc 2 of the regulator 20 are replaced by respectively identical components in the regulator 10 , which are respectively denoted by the references M 1 , Rp 1 , DZ 1 and Rc 1 . It shall be noted that there is no coupling between the components forming the regulator 10 and those forming the regulator 20 . It is in this meaning that the regulators 10 and 20 are referred to as being independent.
  • the leakage resistor Rp 1 makes it possible to set the output voltage Vregboot of the regulator 10 correctly when the latter is not under load.
  • the regulators 10 and 20 may have differing structures, and the example given above does not imply any limitation. Further, a structure which is complementary to the one given as an example above may also be envisaged for one and/or other of the regulators 10 and 20 , in which the transistors M 1 and M 2 are P-type MOS (PMOS) transistors, especially in the scope of auto-stepdown circuits. It is also possible to use bipolar transistors, either NPN or PNP, in order to produce one and/or other of the regulators 10 and 20 .
  • PMOS P-type MOS
  • the task of the recovery diode Drec may advantageously be fulfilled by an intrinsic diode contained between the source and the drain of the transistor M 1 , as represented on the diagram in FIG. 4 . In this case, there is no need to provide an additional diode such as the diode represented in FIG. 3 .
  • the output transistor M 1 of the regulator 10 is furthermore provided with additional protection means, which will now be described.
  • These means comprise a protective diode, for example a Zener diode DZp, coupled by its anode to the source and by its cathode to the control gate of the transistor M 1 .
  • the purpose of this diode is to allow the potential at the control gate of M 1 to follow the potential at its source, in particular when the potential at the source of M 1 increases because of the reverse current of the bootstrap diode Dboot. This avoids a reverse gate-source voltage ⁇ overscore (V GS ) ⁇ greater than the maximum reverse gate-source voltage ⁇ overscore (V GSmax ) ⁇ of the transistor M 1 being reached before the protective diode Drec is turned on.
  • the diode Drec does not conduct immediately when the overvoltage occurs, since it is first necessary for the voltage across its terminals to exceed its conduction threshold V D , that is the potential at the source of M 1 has to reach V D +VCC. Without the diode DZp there is therefore still a risk, albeit a reduced risk, that the reverse gate-source voltage ⁇ overscore (V GS ) ⁇ of M 1 will exceed the permissible limit.
  • the diode DZp makes it possible to clamp the reverse gate-source voltage ⁇ overscore (V GS ) ⁇ to V D , where V D denotes the threshold voltage of the diode DZp, for example 0.7 V.
  • M 1 is a MOS transistor
  • the choice of a Zener diode for DZp furthermore makes it possible to benefit from protection of the voltage V GS , for example at 5 V, in a normal operating mode by virtue of the Zener threshold.
  • the additional protection means may also comprise a resistor Rp, for example a 10 k ⁇ resistor, arranged in series with the control gate of the resistor M 1 in order to limit the current.
  • This resistor is transparent in the normal operating mode of the regulator (that is when there: is no overvoltage), and has an effect only in the event of an overvoltage at the source of the transistor M 1 .
  • FIGS. 5 and 6 illustrate the way in which the regulator 10 operates in the embodiment with the additional protection means.
  • FIG. 5 represents the waveform of the output voltage Vout of the drive circuit during one period.
  • the circuit Vout oscillates between the reference potential ⁇ Vcc and the voltage +Vcc.
  • the curve 61 gives the waveform of the voltage Vregboot
  • the curve 62 gives the waveform of the gate voltage V G of the output transistor M 1 of the regulator 10 .
  • the voltage Vregboot is substantially equal to 10 V
  • the voltage V G is equal to Vregboot plus the gate-source voltage M 1 , which is substantially equal to 2 V.
  • Vregboot becomes higher than its normal value because of the overvoltage which is produced at the node S 1 , that is at the source of the regulator 10 (source of M 1 ).
  • Vregboot nevertheless reaches a maximum equal to V D +VCC, where V D is the conduction threshold of the recovery diode Drec. Beyond this, the diode Drec starts to conduct so that the voltage Vregboot does not increase any further. The overvoltage is therefore limited.
  • the protective diode DZp conducts so that the gate voltage V G of M 1 follows the voltage Vregboot, to within the forward voltage drop V D of the diode DZp.
  • the reverse gate-source voltage ⁇ overscore (V GS ) ⁇ of M 1 never exceeds this limit V D , which is much less than ⁇ overscore (V GSmax ) ⁇ . This is the case with a transistor M 1 for which, for example, ⁇ overscore (V GSmax ) ⁇ is equal to 10 V.
  • the protective diode DZp is in principle transparent during normal operation of the regulator 10 , but also serves to limit the voltage V GS of M 1 to the Zener voltage, that is to 5 V in the example. This effect provides protection for the transistor M 1 in the event of current demands which may be too much for the transistor M 1 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dc-Dc Converters (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
US10/902,502 2003-07-31 2004-07-29 Bootstrap driver Active US7046040B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0309444A FR2858493B1 (fr) 2003-07-31 2003-07-31 Circuit d'attaque a autoelevation
FR0309444 2003-07-31

Publications (2)

Publication Number Publication Date
US20050110556A1 US20050110556A1 (en) 2005-05-26
US7046040B2 true US7046040B2 (en) 2006-05-16

Family

ID=34043703

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/902,502 Active US7046040B2 (en) 2003-07-31 2004-07-29 Bootstrap driver

Country Status (2)

Country Link
US (1) US7046040B2 (fr)
FR (1) FR2858493B1 (fr)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060034107A1 (en) * 2004-08-14 2006-02-16 Distributed Power, Inc. Bipolar bootstrap top switch gate drive for half-bridge semiconductor power topologies
US20100109433A1 (en) * 2008-10-31 2010-05-06 Chih-Tai Chen Power allocating apparatus
US20100289560A1 (en) * 2009-05-16 2010-11-18 Texas Instruments Incorporated Systems and Methods of Bit Stuffing Pulse Width Modulation
US20120013323A1 (en) * 2010-07-19 2012-01-19 Siemens Aktiengesellschaft Half bridge apparatus and half bridge control method
US8536808B2 (en) 2011-11-23 2013-09-17 Tower Semiconductor Ltd. CMOS bootstrap circuit for DC/DC buck converter using low voltage CMOS diode
US8860494B2 (en) 2007-05-22 2014-10-14 Power Integrations, Inc. Half-bridge circuits employing normally on switches and methods of preventing unintended current flow therein
US20140361759A1 (en) * 2011-12-06 2014-12-11 Shanghai Ruking Electronics Co., Ltd. Bootstrap driving circuit without extra power supply
US9356514B2 (en) 2013-07-05 2016-05-31 Huawei Technologies Co., Ltd. Power supply conversion apparatus with bootstrap unit
US9525411B2 (en) 2014-11-13 2016-12-20 Analog Devices, Inc. Power supply circuits for gate drivers
US9627964B1 (en) 2016-02-25 2017-04-18 Nxp Usa, Inc. Systems and methods for recovering voltage beyond device limits
US10536070B1 (en) 2018-08-01 2020-01-14 Infineon Technologies Ag Driver for switching gallium nitride (GaN) devices
US11251691B2 (en) * 2019-09-23 2022-02-15 Stmicroelectronics Asia Pacific Pte Ltd Floating power supply for a driver circuit configured to drive a high-side switching transistor

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008047323A1 (fr) 2006-10-20 2008-04-24 Nxp B.V. Amplificateur de puissance
US20100171543A1 (en) * 2009-01-08 2010-07-08 Ciclon Semiconductor Device Corp. Packaged power switching device
FR2955699B1 (fr) * 2010-01-26 2013-08-16 St Microelectronics Rousset Structure de protection d'un circuit integre contre des decharges electrostatiques
US9136836B2 (en) 2011-03-21 2015-09-15 Semiconductor Components Industries, Llc Converter including a bootstrap circuit and method
US9331655B2 (en) * 2013-07-10 2016-05-03 Broadcom Corporation Pop-click noise grounding switch design with deep sub-micron CMOS technology
US9419509B2 (en) * 2014-08-11 2016-08-16 Texas Instruments Incorporated Shared bootstrap capacitor for multiple phase buck converter circuit and methods
US11095229B1 (en) * 2020-09-24 2021-08-17 Monolithic Power Systems, Inc. High switching frequency direct AC to AC converter

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0367006A2 (fr) 1988-10-28 1990-05-09 STMicroelectronics S.r.l. Dispositif pour générer une tension de référence pour un circuit de commutation comportant un circuit du type "bootstrap" capacitif
US5747943A (en) * 1994-09-01 1998-05-05 International Rectifier Corporation MOS gate driver integrated circuit for ballast circuits
US5801557A (en) * 1995-10-10 1998-09-01 International Rectifier Corp. High voltage drivers which avoid -Vs failure modes
EP0887933A1 (fr) 1997-06-24 1998-12-30 STMicroelectronics S.r.l. Circuit d'extinction pour un transistor LDMOS en présence d'un courant inverse
US6215329B1 (en) * 1996-07-24 2001-04-10 Sgs-Thomson Microelectronics S.R.L. Output stage for a memory device and for low voltage applications

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0367006A2 (fr) 1988-10-28 1990-05-09 STMicroelectronics S.r.l. Dispositif pour générer une tension de référence pour un circuit de commutation comportant un circuit du type "bootstrap" capacitif
US5747943A (en) * 1994-09-01 1998-05-05 International Rectifier Corporation MOS gate driver integrated circuit for ballast circuits
US5801557A (en) * 1995-10-10 1998-09-01 International Rectifier Corp. High voltage drivers which avoid -Vs failure modes
US6215329B1 (en) * 1996-07-24 2001-04-10 Sgs-Thomson Microelectronics S.R.L. Output stage for a memory device and for low voltage applications
EP0887933A1 (fr) 1997-06-24 1998-12-30 STMicroelectronics S.r.l. Circuit d'extinction pour un transistor LDMOS en présence d'un courant inverse

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060034107A1 (en) * 2004-08-14 2006-02-16 Distributed Power, Inc. Bipolar bootstrap top switch gate drive for half-bridge semiconductor power topologies
US7248093B2 (en) * 2004-08-14 2007-07-24 Distributed Power, Inc. Bipolar bootstrap top switch gate drive for half-bridge semiconductor power topologies
US8860494B2 (en) 2007-05-22 2014-10-14 Power Integrations, Inc. Half-bridge circuits employing normally on switches and methods of preventing unintended current flow therein
US20100109433A1 (en) * 2008-10-31 2010-05-06 Chih-Tai Chen Power allocating apparatus
US7932631B2 (en) * 2008-10-31 2011-04-26 Silitek Electronic (Guangzhou) Co., Ltd. Power allocating apparatus
US20100289560A1 (en) * 2009-05-16 2010-11-18 Texas Instruments Incorporated Systems and Methods of Bit Stuffing Pulse Width Modulation
US8174248B2 (en) * 2009-05-16 2012-05-08 Texas Instruments Incorporated Systems and methods of bit stuffing pulse width modulation
US8749277B2 (en) * 2010-07-19 2014-06-10 Siemens Aktiengesellschaft Half bridge apparatus and half bridge control method
US20120013323A1 (en) * 2010-07-19 2012-01-19 Siemens Aktiengesellschaft Half bridge apparatus and half bridge control method
US8536808B2 (en) 2011-11-23 2013-09-17 Tower Semiconductor Ltd. CMOS bootstrap circuit for DC/DC buck converter using low voltage CMOS diode
US20140361759A1 (en) * 2011-12-06 2014-12-11 Shanghai Ruking Electronics Co., Ltd. Bootstrap driving circuit without extra power supply
US9479041B2 (en) * 2011-12-06 2016-10-25 Shanghai Ruking Electronics Co., Ltd Bootstrap driving circuit without extra power supply
US9356514B2 (en) 2013-07-05 2016-05-31 Huawei Technologies Co., Ltd. Power supply conversion apparatus with bootstrap unit
US9525411B2 (en) 2014-11-13 2016-12-20 Analog Devices, Inc. Power supply circuits for gate drivers
US9627964B1 (en) 2016-02-25 2017-04-18 Nxp Usa, Inc. Systems and methods for recovering voltage beyond device limits
US10536070B1 (en) 2018-08-01 2020-01-14 Infineon Technologies Ag Driver for switching gallium nitride (GaN) devices
US11251691B2 (en) * 2019-09-23 2022-02-15 Stmicroelectronics Asia Pacific Pte Ltd Floating power supply for a driver circuit configured to drive a high-side switching transistor

Also Published As

Publication number Publication date
FR2858493B1 (fr) 2005-10-21
FR2858493A1 (fr) 2005-02-04
US20050110556A1 (en) 2005-05-26

Similar Documents

Publication Publication Date Title
US7046040B2 (en) Bootstrap driver
US8487602B2 (en) Switch driving circuit and driving method thereof
US7310006B2 (en) Semiconductor integrated circuit
EP2164155B1 (fr) Circuit de commande d'élément électronique
JP2639325B2 (ja) 定電圧発生回路
US7791371B2 (en) Level shift circuit and power semiconductor device
US8013642B2 (en) Output drive circuit
US20060034114A1 (en) Gate driving circuit and gate driving method of power MOSFET
EP2315354B1 (fr) Dispositif semi-conducteur
US20110075446A1 (en) Circuit for Converting a Pulsed Input Voltage to a DC Voltage
KR101297460B1 (ko) 게이트 구동 장치
US6747502B2 (en) Level shift circuit including a resistor configured to drive a high-withstand-voltage element
EP2591546A1 (fr) Circuit d'excitation, dispositif semiconducteur doté du circuit d'excitation et régulateur à découpage et équipement électronique utilisant le circuit d'excitation et le dispositif semiconducteur
US6844769B2 (en) Drive circuit
US5467050A (en) Dynamic biasing circuit for semiconductor device
US11128295B1 (en) Semiconductor device
JPH11205112A (ja) 高耐圧パワー集積回路
CN111200353A (zh) 应用于开关管控制的驱动电路
JP4319336B2 (ja) Ｍｏｓスイッチング回路
CN112701885A (zh) 一种组合功率管驱动电路、方法和电源装置
JP5278229B2 (ja) 半導体集積回路の保護装置および保護方法
CN210927585U (zh) 一种自举驱动电路
CN217522739U (zh) 一种降压装置
CN220492852U (zh) 一种驱动电路及开关电源
US11735997B2 (en) Upper arm drive circuit having a reverse current prevention circuit disposed between a power supply of a power conversion device and a first capacitor and control method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: STMICROELECTRONICS S.A., FRANCE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GUEDON, YANNICK;REEL/FRAME:015597/0631

Effective date: 20041130

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: STMICROELECTRONICS INTERNATIONAL NV, NETHERLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS SA;REEL/FRAME:037841/0686

Effective date: 20160217

AS Assignment

Owner name: FRANCE BREVETS, FRANCE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS INTERNATIONAL NV;REEL/FRAME:039140/0584

Effective date: 20160321

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553)

Year of fee payment: 12

AS Assignment

Owner name: MICROELECTRONIC INNOVATIONS, LLC, MICHIGAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FRANCE BREVETS;REEL/FRAME:060161/0346

Effective date: 20220509

AS Assignment

Owner name: MICROELECTRONIC INNOVATIONS, LLC, DELAWARE

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 060161 FRAME: 0346. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:FRANCE BREVETS;REEL/FRAME:060389/0768

Effective date: 20220616