US7036002B1 - System and method for using multiple working memories to improve microprocessor security - Google Patents

System and method for using multiple working memories to improve microprocessor security Download PDF

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Publication number
US7036002B1
US7036002B1 US09/242,974 US24297499A US7036002B1 US 7036002 B1 US7036002 B1 US 7036002B1 US 24297499 A US24297499 A US 24297499A US 7036002 B1 US7036002 B1 US 7036002B1
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Prior art keywords
program
memory
microcomputer according
microprocessor
main
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US09/242,974
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English (en)
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Michel Ugon
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CP8 Technologies SA
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CP8 Technologies SA
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Definitions

  • microprocessor or microcomputer which comprises a processor, an initial working memory, a main memory containing an operating system, a main program and a secondary program, is characterized in that it also has:
  • the operation of the process can then be controlled by the secondary program (P 2 ) which, for example, can trigger a waiting loop of which the length of time depends on a random number derived from the generator ( 2 ).
  • the secondary program can be executed using the parts of the memory unused by the main program so that the latter can resume its normal process as soon as the secondary program transmits the new control to it, or yet again, on the next interruption, or once again, using the timer as previously, or using a combination of the two.
  • the secondary program can also use the shared resources as long as it reestablishes the context of the main program before transferring control back to it.
  • a fourth embodiment also illustrated in FIG. 1 allows the use of RAMs ( 51 ) and ( 52 ) simultaneously. Indeed, if it is assumed that it is possible to detect the switching of the memories and the associated registers, it might be possible to carry out analyses by eliminating the sequences using the dummy memory ( 52 ). To avoid this eventuality, this embodiment means that the memories ( 51 ) and ( 52 ) can be validated in parallel during an initial phase. Obviously, this presupposes that memory ( 52 ) in the case at hand, has a size equal to at least that of the zone used by program (P 1 ) in memory ( 51 ) when working with the latter.
  • Step ( 45 ) by writing into the switching register ( 53 ) to change over to the dummy mode so as to modify the values of lines ( 535 ) and ( 532 ) to enable the use of register stack ( 55 ) and of the dummy memory while locking the circuits under control by ( 531 ) and ( 534 ).

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)
  • Microcomputers (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
US09/242,974 1997-06-26 1998-06-25 System and method for using multiple working memories to improve microprocessor security Expired - Fee Related US7036002B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9707995A FR2765361B1 (fr) 1997-06-26 1997-06-26 Microprocesseur ou microcalculateur imprevisible
PCT/FR1998/001343 WO1999000718A1 (fr) 1997-06-26 1998-06-25 Microprocesseur ou microcalculateur imprévisible

Publications (1)

Publication Number Publication Date
US7036002B1 true US7036002B1 (en) 2006-04-25

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US09/242,974 Expired - Fee Related US7036002B1 (en) 1997-06-26 1998-06-25 System and method for using multiple working memories to improve microprocessor security

Country Status (9)

Country Link
US (1) US7036002B1 (https=)
EP (1) EP0920660B1 (https=)
JP (2) JP2000501541A (https=)
KR (1) KR100578459B1 (https=)
CN (1) CN1239973C (https=)
DE (1) DE69839958D1 (https=)
FR (1) FR2765361B1 (https=)
TW (1) TW457453B (https=)
WO (1) WO1999000718A1 (https=)

Cited By (11)

* Cited by examiner, † Cited by third party
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US20040162993A1 (en) * 2003-02-13 2004-08-19 Yannick Teglia Antifraud method of an algorithm executed by an integrated circuit
US20040162991A1 (en) * 2003-02-13 2004-08-19 Yannick Teglia Antifraud method and circuit for an integrated circuit register containing data obtained from secret quantities
US20060117167A1 (en) * 2002-12-12 2006-06-01 Evrard Christophe J Processing activity masking in a data processing system
WO2008145561A1 (en) * 2007-05-29 2008-12-04 Gemalto Sa Electronic token comprising several microprocessors and method of managing command execution on several microprocessors
ITMI20102476A1 (it) * 2010-12-30 2012-07-01 Incard Sa Metodo per de-correlare segnali elettrici emessi da una carta a circuito integrato
US9378363B1 (en) * 2014-10-08 2016-06-28 Amazon Technologies, Inc. Noise injected virtual timer
US9491112B1 (en) 2014-12-10 2016-11-08 Amazon Technologies, Inc. Allocating processor resources based on a task identifier
US20170046539A1 (en) * 2004-06-30 2017-02-16 Socionext Inc. Secure processor and a program for a secure processor
US9703951B2 (en) 2014-09-30 2017-07-11 Amazon Technologies, Inc. Allocation of shared system resources
US9754103B1 (en) 2014-10-08 2017-09-05 Amazon Technologies, Inc. Micro-architecturally delayed timer
US9864636B1 (en) 2014-12-10 2018-01-09 Amazon Technologies, Inc. Allocating processor resources based on a service-level agreement

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2787900B1 (fr) * 1998-12-28 2001-02-09 Bull Cp8 Circuit integre intelligent
JP2001094550A (ja) * 1999-09-17 2001-04-06 Toshiba Corp 信号処理装置
MX2009012134A (es) * 2007-05-11 2009-11-25 Echostar Technologies Llc Aparato para controlar la ejecucion de un procesador en un ambiente seguro.
CN103164384B (zh) * 2011-12-15 2016-05-18 中国银联股份有限公司 多机系统共享内存的同步实现方法及其系统
CN120653503B (zh) * 2025-08-20 2025-11-07 沐曦集成电路(南京)有限公司 一种多模式的开关系统

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US5029069A (en) * 1987-06-30 1991-07-02 Mitsubishi Denki Kabushiki Kaisha Data processor
US5127098A (en) * 1989-04-12 1992-06-30 Sun Microsystems, Inc. Method and apparatus for the context switching of devices
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US5280618A (en) * 1989-02-27 1994-01-18 Motorola, Inc. Interrupt test circuit for microprocessor system
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
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US5694604A (en) * 1982-09-28 1997-12-02 Reiffin; Martin G. Preemptive multithreading computer system with clock activated interrupt

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US5029069A (en) * 1987-06-30 1991-07-02 Mitsubishi Denki Kabushiki Kaisha Data processor
US5012409A (en) * 1988-03-10 1991-04-30 Fletcher Mitchell S Operating system for a multi-tasking operating environment
US5280618A (en) * 1989-02-27 1994-01-18 Motorola, Inc. Interrupt test circuit for microprocessor system
US5127098A (en) * 1989-04-12 1992-06-30 Sun Microsystems, Inc. Method and apparatus for the context switching of devices
US5361337A (en) * 1989-08-03 1994-11-01 Sun Microsystems, Inc. Method and apparatus for rapidly switching processes in a computer system
US5249294A (en) * 1990-03-20 1993-09-28 General Instrument Corporation Determination of time of execution of predetermined data processing routing in relation to occurrence of prior externally observable event
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5613114A (en) * 1994-04-15 1997-03-18 Apple Computer, Inc System and method for custom context switching

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Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060117167A1 (en) * 2002-12-12 2006-06-01 Evrard Christophe J Processing activity masking in a data processing system
US20040162993A1 (en) * 2003-02-13 2004-08-19 Yannick Teglia Antifraud method of an algorithm executed by an integrated circuit
US20040162991A1 (en) * 2003-02-13 2004-08-19 Yannick Teglia Antifraud method and circuit for an integrated circuit register containing data obtained from secret quantities
US7373463B2 (en) * 2003-02-13 2008-05-13 Stmicroelectronics S.A. Antifraud method and circuit for an integrated circuit register containing data obtained from secret quantities
US10095890B2 (en) * 2004-06-30 2018-10-09 Socionext Inc. Secure processor and a program for a secure processor
US10303901B2 (en) 2004-06-30 2019-05-28 Socionext Inc. Secure processor and a program for a secure processor
US10685145B2 (en) 2004-06-30 2020-06-16 Socionext Inc. Secure processor and a program for a secure processor
US20170046539A1 (en) * 2004-06-30 2017-02-16 Socionext Inc. Secure processor and a program for a secure processor
US11550962B2 (en) 2004-06-30 2023-01-10 Socionext Inc. Secure processor and a program for a secure processor
WO2008145561A1 (en) * 2007-05-29 2008-12-04 Gemalto Sa Electronic token comprising several microprocessors and method of managing command execution on several microprocessors
US20100250962A1 (en) * 2007-05-29 2010-09-30 Gemalto Sa Electronic token comprising several microprocessors and method of managing command execution on several microprocessors
EP2000936A1 (en) * 2007-05-29 2008-12-10 Gemplus Electronic token comprising several microprocessors and method of managing command execution on several microprocessors
US8934628B2 (en) * 2010-12-30 2015-01-13 Stmicroelectronics International Nv Method to de-correlate electric signals emitted by an IC card
US20120170742A1 (en) * 2010-12-30 2012-07-05 STMicroelectronics, NV Method to de-correlate electric signals emitted by an ic card
ITMI20102476A1 (it) * 2010-12-30 2012-07-01 Incard Sa Metodo per de-correlare segnali elettrici emessi da una carta a circuito integrato
US9703951B2 (en) 2014-09-30 2017-07-11 Amazon Technologies, Inc. Allocation of shared system resources
US9898601B2 (en) 2014-09-30 2018-02-20 Amazon Technologies, Inc. Allocation of shared system resources
US9378363B1 (en) * 2014-10-08 2016-06-28 Amazon Technologies, Inc. Noise injected virtual timer
US10146935B1 (en) * 2014-10-08 2018-12-04 Amazon Technologies, Inc. Noise injected virtual timer
US9754103B1 (en) 2014-10-08 2017-09-05 Amazon Technologies, Inc. Micro-architecturally delayed timer
US10104008B1 (en) 2014-12-10 2018-10-16 Amazon Technologies, Inc. Allocating processor resources based on a task identifier
US9864636B1 (en) 2014-12-10 2018-01-09 Amazon Technologies, Inc. Allocating processor resources based on a service-level agreement
US9491112B1 (en) 2014-12-10 2016-11-08 Amazon Technologies, Inc. Allocating processor resources based on a task identifier

Also Published As

Publication number Publication date
FR2765361A1 (fr) 1998-12-31
WO1999000718A1 (fr) 1999-01-07
EP0920660B1 (fr) 2008-09-03
CN1234883A (zh) 1999-11-10
FR2765361B1 (fr) 2001-09-21
KR20000068373A (ko) 2000-11-25
CN1239973C (zh) 2006-02-01
KR100578459B1 (ko) 2006-05-10
JP2002055883A (ja) 2002-02-20
TW457453B (en) 2001-10-01
JP2000501541A (ja) 2000-02-08
DE69839958D1 (de) 2008-10-16
HK1022756A1 (en) 2000-08-18
EP0920660A1 (fr) 1999-06-09

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