US7005890B2 - Device for generating a bit line selection signal of a memory device - Google Patents

Device for generating a bit line selection signal of a memory device Download PDF

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US7005890B2
US7005890B2 US10/887,135 US88713504A US7005890B2 US 7005890 B2 US7005890 B2 US 7005890B2 US 88713504 A US88713504 A US 88713504A US 7005890 B2 US7005890 B2 US 7005890B2
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bit line
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Young Soo Kim
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Intellectual Discovery Co Ltd
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J36/00—Parts, details or accessories of cooking-vessels
    • A47J36/06—Lids or covers for cooking-vessels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J27/00—Cooking-vessels
    • A47J27/002—Construction of cooking-vessels; Methods or processes of manufacturing specially adapted for cooking-vessels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Definitions

  • the present invention relates generally to a device for generating a bit line selection signal in a semiconductor memory device, and more particularly to a device for generating a bit line selection signal to optimally facilitate the high speed operations of a semiconductor memory device.
  • High-speed and high-integration are the two key technological factors in the modern semiconductor memory design.
  • the memory device is becoming highly integrated, meeting every specification of the speed related parameters is becoming increasingly more difficult.
  • the signal lines in a highly integrated memory device are likely to be elongated more thinly, and this tends to cause more RC delays, making more difficult to meet the the speed related parameters.
  • Another factor that should not be neglected to meet the speed related parameters in a memory device is to optimally minimize the time required to transfer data from a bit line to a local line in the memory device.
  • FIG. 1 shows a bit line selection signal generator 102 for use in a memory device to allow transfer of data from bit lines (labeled BIT, /BIT) to local input/output lines (labeled LIO, /LIO).
  • bit lines labeled BIT, /BIT
  • LIO local input/output lines
  • FIG. 1 shows a sense amplifier 100 is located between the bit lines BIT, /BIT.
  • the bit lines BIT, /BIT and the local input/output lines LIO, /LIO are separated by column transistors 11 , 12 .
  • the gates of the column transistors 11 , 12 are connected to a bit line selection signal Yi outputted by a bit line selection signal generator 102 .
  • the bit line selection signal Yi enables particular column transistors 11 , 12 that correspond to a bit line selected according to a column address inputted to a column decoder 200 as shown in FIG. 2 .
  • the bit line selection signal generator 102 includes the column decoder 200 , which has a NAND gate 21 and an inverter 22 .
  • the NAND gate 21 receives the column address signal, and the inverter 22 inverts the output signal of the NAND gate 21 .
  • the bit line selection signal Yi is generated.
  • the bit line selection signal Yi may be understood also as the column address decoder signal.
  • the NAND gate 21 and the inverter 22 of FIG. 2 are driven by an external power voltage VEXT, which is also the driving voltage of the memory device itself. Consequently, the voltage of the bit line selection signal Yi, which would enable the column transistors 11 , 12 , is the same voltage of the VEXT.
  • tAA One speed related parameter that measures the time taken for a semiconductor memory device to output data in response to a read command is known as tAA.
  • One significant factor that affects the tAA is the driving capacity of the column transistors 11 , 12 ( FIG. 1 ).
  • the column transistors 11 , 12 are enabled by the bit line selection signal Yi, which is generated by the bit line selection generator 102 .
  • the driving capacity of the column transistors 11 , 12 becomes greater, the speed for transmitting data from the bit line BIT, /BIT to a local line LIO, /LIO would be faster.
  • the external power voltage VEXT which is the driving voltage for the memory device itself, is typically applied to the gates of the column transistors 11 , 12 as the bit line selection signal Yi.
  • the VEXT in a DDR SDRAM is 2.5 V; thus, voltage of the bit line selection signal Yi in a DDR SDRAM is also 2.5 V. Utilizing 2.5 V to enable the column transistors 11 , 12 in a DDR SDRAM appears to present no serious technical problems for operating the column transistors 11 , 12 .
  • next-generation semiconductor memory devices such as DDR2 SDRAM
  • the external power voltage VEXT utilized is below 2.5 V, and more typically less than 1.8 V.
  • the voltage level of Yi signal in the next generation memory devices applied to the gates of the column transistors would be lower than 1.8 V and cause very poor tAA when it is compared to the tAA of DDR SDRAM.
  • the present invention provides, inter alia, a circuit for securing a sufficient specification margin required for high-speed operations in any semiconductor memory device.
  • the present invention improves signal transmission speed of data from a bit line selected by a column address.
  • a device generates a bit line selection signal for enabling a column transistor connected to a bit line and a local input/output line in a semiconductor memory device.
  • the device of the present invention includes at least a column decoder and a chain of connected inverters.
  • the column decoder decodes a column address signal received during a read operation.
  • the chain of connected inverters has an inverter chain input terminal for receiving a first signal outputted from the column decoder and an inverter chain output terminal for outputting a second signal to drive the column transistor.
  • the voltage of the second signal outputted at the inverter chain output terminal is held substantially same as the voltage of the first signal for a predetermined time.
  • the voltage of the second signal outputted at the inverter chain output terminal is held at a higher voltage than the voltage of the first signal to improve the current driving capacity of the column transistor that increases the transmission speed of the signal transmitted from the bit line to the local input/output line.
  • the column decoder at least includes a NAND gate and an inverter connected to the NAND gate.
  • the NAND gate receives a column address signal.
  • the inverter connected to the NAND gate outputs the first signal based on the output signal of the NAND gate such that the driving voltage applied to the NAND gate and the inverter substantially equals the voltage of the first signal.
  • the chain of inverters at least includes an even number of serially connected inverters.
  • the driving voltage applied to the chain of inverters substantially equals the voltage of the second signal.
  • the predetermined time in which the first signal is generated at the inverter chain output terminal is determined by the number of inverters that are serially connected in the chain.
  • the total duration in which the first and second signals are outputted from the inverter chain output terminal to the gate transistor is substantially determined by the duration of the column address signal being applied to the column decoder.
  • FIG. 1 is a functional block diagram of a conventional bit line selection signal generator for use in one type of semiconductor memory devices.
  • FIG. 2 is an internal circuit diagram of a conventional bit line selection signal generator.
  • FIG. 3 is an internal circuit diagram of a bit line selection signal generator in accordance with an embodiment of the present invention.
  • FIG. 4 is a waveform diagram of a bit line selection signal in accordance with an embodiment of the present invention.
  • a semiconductor memory device outputs data after an active command (such as a read command) is issued to enable a word line. To do so, the memory device outputs the data available on a specific bit line corresponding to the selected column address. Typically, the column address is inputted at the same time when a read command is issued. The data, which has been made available on the bit line selected by the column address, is transmitted to a data output pad through local and global lines.
  • an active command such as a read command
  • the circuit according to an embodiment of the present invention reduces the tAA by enhancing the operational performance of the column transistors that connect the bit line and the local line.
  • FIG. 3 Shown in FIG. 3 is an internal circuit diagram of a bit line selection signal generator according to an embodiment of the present invention. As can be readily understood in view of the foregoing discussions, Yi in FIG. 3 would enable the column transistors in a memory device (such as those 11 , 12 shown in FIG. 1 ), but with a notable improvement in tAA.
  • the bit line selection signal generator includes a column decoder 300 and an inverter chain unit 320 .
  • the column decoder 300 is shown as being identical to the bit line selection signal generator 200 of FIG. 2 ; however, it should be readily understood that other equivalent circuit structures may also be possible.
  • the column decoder 300 as shown in FIG. 3 includes a NAND gate 31 for receiving a column address signal and an inverter 32 for receiving an output signal of the NAND gate 31 .
  • the output node (a) of the column decoder 300 as shown in FIG. 3 is also the output node (b) of the inverter chain unit 320 .
  • the output node (b) is connected to the output node (a) through conductive materials.
  • the inverter chain unit 320 includes one or more (more typically an even number of) inverters 33 , 34 .
  • the delay time can be adjusted.
  • An input terminal of the inverter 33 is connected to the node (a) while an output terminal of the inverter 34 is connected to the node (b).
  • the input terminal of a chain of serially connected even number of inverters is connected to the node (a)
  • the output terminal of the chain of the same serially connected even numbered inverters is connected to the node (b).
  • a bit line selection signal Yi having a voltage level of the node (b) would then be applied to the gates of the column transistors (such as those 11 , 12 shown in FIG. 1 , but not shown in FIG. 3 ).
  • an external power voltage VEXT is fed to the column decoder 300 to drive the NAND gate 31 and the inverter 32 .
  • a driving voltage of the inverters 33 , 34 is a different voltage VPP.
  • the voltage level of VPP, generated from an internal voltage generator, is higher than that of the external power voltage VEXT.
  • the external power voltage VEXT is applied to the column decoder 300 , and thus the voltage at the node (a) outputted from the column decoder 300 is the VEXT.
  • the voltage at node (b) outputted from the inverter chain unit 320 would be the VPP, since the driving voltage of the inverters 33 , 34 is VPP (but at a predetermined time delay adjustable according to the number of inverters in the inverter chain unit 320 ).
  • a column address signal applied according to a read command from the memory device is inputted to the NAND gate 31 . Therefore, the inverter 32 outputs the voltage of VEXT, and thus the voltage level of the bit line selection signal Yi becomes the VEXT at the node (a).
  • the output voltage of the inverter 32 is applied to the inverter chain unit 320 . After a predetermined time, the voltage level outputted from the inverter 34 is therefore the VPP. In other words, the voltage level of the bit line selection signal Yi rises from the VEXT to the VPP.
  • FIG. 4 shows the voltage waveform of the bit line selection signal Yi according to an embodiment of the present invention, which has been explained with reference to FIG. 3 .
  • the voltage level of Yi remains at the VEXT level for a predetermined time and then rises to the VPP level under the influence of the inverter chain unit 320 (in FIG. 3 ).
  • the point in time when the high voltage VPP of the bit line selection signal Yi changes to a low level depends on the point in time when the address signal inputted to the column decoder 300 changes. Therefore, the total pulse width of the bit line selection signal Yi remains unchanged.
  • the circuit of the present invention improves the current driving capacity of the column transistors by gradually increasing a turn-on voltage applied to the gates of the column transistors. This improves the transmission speed of the amplified bit line voltage by the sense amplifier (such as 100 in FIG. 1 ) to the local line (such as LIO, /LIO).
  • the circuit of the present invention therefore can be used advantageously to improve the charge sharing speed of the bit line and the local line, resulting in the reduction of the tAA.
  • the circuit of the present invention can be used for reducing the charge sharing time between the local line and the global line.
  • the inverter chain unit 320 outputs a higher voltage than the output voltage of the column decoder 300 after a predetermined time delay.
  • the inverter chain unit 320 can be implemented for use in other circuits that require a voltage higher than the output voltage of the column decoder 320 to be outputted after a predetermined delay time.
  • the present invention is capable of increasing the turn-on voltage applied to the gate of the column transistor, and of improving the operational characteristics of the column transistor(s) that is enabled by a column address signal.
  • the present invention provides significant advantages and improvements for high-speed operations in the next-generation semiconductor memory devices such as DDR2 SDRAM.

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Abstract

The device for generating the bit line signal to enable a column transistor that is connected to a bit line and a local line in a semiconductor memory device includes at least a column decoder and a chain of connected inverters. The column decoder decodes a column address signal. The chain of connected inverters has an input terminal for receiving a first signal outputted from the column decoder and an output terminal for outputting a second signal to drive the column transistor. The second signal voltage is held substantially same as the first signal voltage for a predetermined time. After the predetermined time, the second signal voltage is held at a higher voltage than the first signal voltage to improve the current driving capacity of the column transistor. This increases the transmission speed of the signal transmitted from the bit line to the local input/output line.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a device for generating a bit line selection signal in a semiconductor memory device, and more particularly to a device for generating a bit line selection signal to optimally facilitate the high speed operations of a semiconductor memory device.
2. Description of the Related Art
High-speed and high-integration are the two key technological factors in the modern semiconductor memory design. However, as the memory device is becoming highly integrated, meeting every specification of the speed related parameters is becoming increasingly more difficult. For example, the signal lines in a highly integrated memory device are likely to be elongated more thinly, and this tends to cause more RC delays, making more difficult to meet the the speed related parameters.
Another factor that should not be neglected to meet the speed related parameters in a memory device is to optimally minimize the time required to transfer data from a bit line to a local line in the memory device.
FIG. 1 shows a bit line selection signal generator 102 for use in a memory device to allow transfer of data from bit lines (labeled BIT, /BIT) to local input/output lines (labeled LIO, /LIO). As shown in FIG. 1, a sense amplifier 100 is located between the bit lines BIT, /BIT. The bit lines BIT, /BIT and the local input/output lines LIO, /LIO are separated by column transistors 11, 12.
The gates of the column transistors 11, 12 are connected to a bit line selection signal Yi outputted by a bit line selection signal generator 102. The bit line selection signal Yi enables particular column transistors 11, 12 that correspond to a bit line selected according to a column address inputted to a column decoder 200 as shown in FIG. 2.
Now referring to FIG. 2, the bit line selection signal generator 102 includes the column decoder 200, which has a NAND gate 21 and an inverter 22. The NAND gate 21 receives the column address signal, and the inverter 22 inverts the output signal of the NAND gate 21. Based on the NAND gate 21 output signal, the bit line selection signal Yi is generated. In this regard, the bit line selection signal Yi may be understood also as the column address decoder signal.
The NAND gate 21 and the inverter 22 of FIG. 2 are driven by an external power voltage VEXT, which is also the driving voltage of the memory device itself. Consequently, the voltage of the bit line selection signal Yi, which would enable the column transistors 11, 12, is the same voltage of the VEXT.
One speed related parameter that measures the time taken for a semiconductor memory device to output data in response to a read command is known as tAA. One significant factor that affects the tAA is the driving capacity of the column transistors 11, 12 (FIG. 1). As already discussed, the column transistors 11, 12 are enabled by the bit line selection signal Yi, which is generated by the bit line selection generator 102. As the driving capacity of the column transistors 11, 12 becomes greater, the speed for transmitting data from the bit line BIT, /BIT to a local line LIO, /LIO would be faster.
The external power voltage VEXT, which is the driving voltage for the memory device itself, is typically applied to the gates of the column transistors 11, 12 as the bit line selection signal Yi. The VEXT in a DDR SDRAM is 2.5 V; thus, voltage of the bit line selection signal Yi in a DDR SDRAM is also 2.5 V. Utilizing 2.5 V to enable the column transistors 11, 12 in a DDR SDRAM appears to present no serious technical problems for operating the column transistors 11, 12.
However, technical problems lie in the next-generation semiconductor memory devices, such as DDR2 SDRAM, in which the external power voltage VEXT utilized is below 2.5 V, and more typically less than 1.8 V. Thus, the voltage level of Yi signal in the next generation memory devices applied to the gates of the column transistors would be lower than 1.8 V and cause very poor tAA when it is compared to the tAA of DDR SDRAM.
SUMMARY OF THE INVENTION
Against this backdrop, the present invention has been developed. The present invention provides, inter alia, a circuit for securing a sufficient specification margin required for high-speed operations in any semiconductor memory device. The present invention improves signal transmission speed of data from a bit line selected by a column address.
A device according to an embodiment of the present invention generates a bit line selection signal for enabling a column transistor connected to a bit line and a local input/output line in a semiconductor memory device. The device of the present invention includes at least a column decoder and a chain of connected inverters.
The column decoder decodes a column address signal received during a read operation. The chain of connected inverters has an inverter chain input terminal for receiving a first signal outputted from the column decoder and an inverter chain output terminal for outputting a second signal to drive the column transistor.
The voltage of the second signal outputted at the inverter chain output terminal is held substantially same as the voltage of the first signal for a predetermined time.
After the predetermined time, the voltage of the second signal outputted at the inverter chain output terminal is held at a higher voltage than the voltage of the first signal to improve the current driving capacity of the column transistor that increases the transmission speed of the signal transmitted from the bit line to the local input/output line.
The column decoder at least includes a NAND gate and an inverter connected to the NAND gate. The NAND gate receives a column address signal. The inverter connected to the NAND gate outputs the first signal based on the output signal of the NAND gate such that the driving voltage applied to the NAND gate and the inverter substantially equals the voltage of the first signal.
The chain of inverters at least includes an even number of serially connected inverters. The driving voltage applied to the chain of inverters substantially equals the voltage of the second signal.
The predetermined time in which the first signal is generated at the inverter chain output terminal is determined by the number of inverters that are serially connected in the chain. The total duration in which the first and second signals are outputted from the inverter chain output terminal to the gate transistor is substantially determined by the duration of the column address signal being applied to the column decoder.
These and other features as well as advantages, which characterize the present invention, will be apparent from a reading of the following detailed description and a review of the associated drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a functional block diagram of a conventional bit line selection signal generator for use in one type of semiconductor memory devices.
FIG. 2 is an internal circuit diagram of a conventional bit line selection signal generator.
FIG. 3 is an internal circuit diagram of a bit line selection signal generator in accordance with an embodiment of the present invention.
FIG. 4 is a waveform diagram of a bit line selection signal in accordance with an embodiment of the present invention.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Wherever appropriate, same reference numerals are used to refer to the same or like parts in the description and/or the drawings.
In general, a semiconductor memory device outputs data after an active command (such as a read command) is issued to enable a word line. To do so, the memory device outputs the data available on a specific bit line corresponding to the selected column address. Typically, the column address is inputted at the same time when a read command is issued. The data, which has been made available on the bit line selected by the column address, is transmitted to a data output pad through local and global lines.
It is desired to optimize the speed parameter tAA in any semiconductor memory devices, especially in those that are highly integrated. The present invention provides solutions to these technical challenges. In general, the circuit according to an embodiment of the present invention reduces the tAA by enhancing the operational performance of the column transistors that connect the bit line and the local line.
Shown in FIG. 3 is an internal circuit diagram of a bit line selection signal generator according to an embodiment of the present invention. As can be readily understood in view of the foregoing discussions, Yi in FIG. 3 would enable the column transistors in a memory device (such as those 11, 12 shown in FIG. 1), but with a notable improvement in tAA.
Referring to FIG. 3, the bit line selection signal generator according to an embodiment of the present invention includes a column decoder 300 and an inverter chain unit 320.
For discussion purposes, the column decoder 300 is shown as being identical to the bit line selection signal generator 200 of FIG. 2; however, it should be readily understood that other equivalent circuit structures may also be possible. The column decoder 300 as shown in FIG. 3 includes a NAND gate 31 for receiving a column address signal and an inverter 32 for receiving an output signal of the NAND gate 31.
The output node (a) of the column decoder 300 as shown in FIG. 3 is also the output node (b) of the inverter chain unit 320. The output node (b) is connected to the output node (a) through conductive materials.
The inverter chain unit 320 includes one or more (more typically an even number of) inverters 33, 34. By adjusting the number of inverters 33, 34, the delay time can be adjusted. An input terminal of the inverter 33 is connected to the node (a) while an output terminal of the inverter 34 is connected to the node (b). For example, the input terminal of a chain of serially connected even number of inverters is connected to the node (a), and the output terminal of the chain of the same serially connected even numbered inverters is connected to the node (b).
A bit line selection signal Yi having a voltage level of the node (b) would then be applied to the gates of the column transistors (such as those 11, 12 shown in FIG. 1, but not shown in FIG. 3).
As shown in FIG. 3, an external power voltage VEXT is fed to the column decoder 300 to drive the NAND gate 31 and the inverter 32. On the other hand, a driving voltage of the inverters 33, 34 is a different voltage VPP. Here, the voltage level of VPP, generated from an internal voltage generator, is higher than that of the external power voltage VEXT.
The external power voltage VEXT is applied to the column decoder 300, and thus the voltage at the node (a) outputted from the column decoder 300 is the VEXT. However, the voltage at node (b) outputted from the inverter chain unit 320 would be the VPP, since the driving voltage of the inverters 33, 34 is VPP (but at a predetermined time delay adjustable according to the number of inverters in the inverter chain unit 320).
A column address signal applied according to a read command from the memory device is inputted to the NAND gate 31. Therefore, the inverter 32 outputs the voltage of VEXT, and thus the voltage level of the bit line selection signal Yi becomes the VEXT at the node (a).
The output voltage of the inverter 32 is applied to the inverter chain unit 320. After a predetermined time, the voltage level outputted from the inverter 34 is therefore the VPP. In other words, the voltage level of the bit line selection signal Yi rises from the VEXT to the VPP.
As the voltage level of the bit line selection signal Yi rises, a current driving capacity of the column transistor also improves. This in turn shortens a charge sharing time between the bit line and the local line. As a result, the tAA is reduced.
FIG. 4 shows the voltage waveform of the bit line selection signal Yi according to an embodiment of the present invention, which has been explained with reference to FIG. 3.
As shown in FIG. 4, the voltage level of Yi remains at the VEXT level for a predetermined time and then rises to the VPP level under the influence of the inverter chain unit 320 (in FIG. 3). The point in time when the high voltage VPP of the bit line selection signal Yi changes to a low level depends on the point in time when the address signal inputted to the column decoder 300 changes. Therefore, the total pulse width of the bit line selection signal Yi remains unchanged.
The circuit of the present invention improves the current driving capacity of the column transistors by gradually increasing a turn-on voltage applied to the gates of the column transistors. This improves the transmission speed of the amplified bit line voltage by the sense amplifier (such as 100 in FIG. 1) to the local line (such as LIO, /LIO). The circuit of the present invention therefore can be used advantageously to improve the charge sharing speed of the bit line and the local line, resulting in the reduction of the tAA. In addition, the circuit of the present invention can be used for reducing the charge sharing time between the local line and the global line.
The inverter chain unit 320 according to an embodiment of the present invention outputs a higher voltage than the output voltage of the column decoder 300 after a predetermined time delay. Thus, the inverter chain unit 320 can be implemented for use in other circuits that require a voltage higher than the output voltage of the column decoder 320 to be outputted after a predetermined delay time.
As already described above, the present invention is capable of increasing the turn-on voltage applied to the gate of the column transistor, and of improving the operational characteristics of the column transistor(s) that is enabled by a column address signal. Thus, the present invention provides significant advantages and improvements for high-speed operations in the next-generation semiconductor memory devices such as DDR2 SDRAM.
It will be clear that the present invention is well adapted to attain the ends and advantages as well as those inherent therein. While a presently preferred embodiment has been described for purposes of this disclosure, various changes and modifications may be made which are well within the scope of the present invention. Numerous other changes may be made which will readily suggest themselves to those skilled in the art and which are encompassed in the spirit of the invention disclosed and as defined in the appended claims.

Claims (5)

1. A device for generating a bit line selection signal for enabling a column transistor connected to a bit line and a local input/output line in a semiconductor memory device, comprising:
a column decoder for decoding a column address signal received during a read operation; and
a chain of connected inverters having an inverter chain input terminal for receiving a first signal outputted from the column decoder and having an inverter chain output terminal for outputting a second signal to drive the column transistor,
wherein the voltage of the second signal is held substantially same as the voltage of the first signal for a predetermined time, and
wherein, after the predetermined time, the voltage of the second signal is held at a higher voltage than the voltage of the first signal to improve the current driving capacity of the column transistor and to increase the transmission speed of the signal transmitted from the bit line to the local input/output line.
2. The device according to claim 1, wherein the column decoder comprises:
a NAND gate for receiving a column address signal; and
an inverter connected to the NAND gate for outputting the first signal based on the output signal of the NAND gate,
wherein the driving voltage applied to the NAND gate and the inverter substantially equals the voltage of the first signal.
3. The device according to claim 1, wherein the chain of inverters comprises an even number of serially connected inverters and the driving voltage applied to the chain of inverters substantially equals the voltage of the second signal.
4. The device according to claim 3, wherein the predetermined time is determined by the number of serially connected inverters in the chain.
5. The device according to claim 4, wherein the total duration in which the first and second signals are outputted from the inverter chain output terminal to the gate transistor is substantially determined by the duration of the column address signal being applied to the column decoder.
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CN103871472A (en) * 2012-12-12 2014-06-18 上海华虹宏力半导体制造有限公司 Column address decoding circuit of memory

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US20050206411A1 (en) 2005-09-22
JP2005267831A (en) 2005-09-29
KR100618695B1 (en) 2006-09-12
CN100437815C (en) 2008-11-26
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CN1670862A (en) 2005-09-21
JP4628026B2 (en) 2011-02-09

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