CN103871472A

CN103871472A - Column address decoding circuit of memory

Info

Publication number: CN103871472A
Application number: CN201210536926.3A
Authority: CN
Inventors: 刘芳芳; 金建明
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2012-12-12
Filing date: 2012-12-12
Publication date: 2014-06-18

Abstract

The present invention discloses a column address decoding circuit of a memory, wherein the selecting tube and the isolating tube of the traditional column address selecting circuit are separated, a high threshold voltage MOS transistor is adopted as an isolation effect, two low threshold voltage MOS transistors are adopted as a selecting effect, and a high voltage produced by a charge pump circuit is applied on the gate level of the high voltage tube so as to reduce influence of the high threshold voltage of the high voltage tube on the setup time and the reading performance, such that the column selecting circuit is substantially simplified, and the setup time of the column selecting circuit is substantially shortened.

Description

The column address decoding scheme of storer

Technical field

The present invention relates to SIC (semiconductor integrated circuit) design field, refer to especially a kind of column address decoding scheme of storer.

Background technology

NVM(Non-Volatile Memory: non-volatility memorizer) circuit that elects when the effect of column select circuit is " reading " operation in sensing circuit, buffer circuit is made in operation with high pressure (" wiping " or " writing ").Traditional implementation method as shown in Figure 1, is made up of two level translator LS1 and LS2 and five metal-oxide-semiconductors, wherein comprises 2 high voltage PMOS P1 and P2, two high pressure NMOS N1 and M2, and the NMOS M1 of a low threshold voltage.The drain terminal of NMOS M1 meets storage unit CL, and source connects the drain terminal of high pressure NMOS M2, the output terminal BL that the source electrode of NMOS M2 is column select circuit.Utilize not only elected pipe but also make isolated tube of high-voltage tube M2, and utilizing grid that level translator LS1 and LS2 be added in voltage Vpwr5 (external power source) high-voltage tube M2 to open M2 pipe, voltage CL while making read operation (storage cell end) transfers to BL.Its principle of work is as follows:

1. when read operation, VCPW=vgnd, selected row Ylv is output as Vpwr5, wherein Yread=0, Hven2=0, high voltage PMOS P1 opens; Control signal Ypre sets high, and Ylvb is vgnd, and high-voltage tube P2 opens, and high pressure NMOS N1 turn-offs, and Voltage-output Ylv is high; Control signal Yev is high, and NMOS M1 and M2 open, selected column circuits transmission CL to BL.Not selected column circuits, voltage Ylv is output as 0, NMOS M2 and turn-offs, and CL voltage is not transferred to BL.

2. when operation with high pressure (wiping or write operation), when control signal VCPW=VNEG_C(" wiping ", VNEG_C=vgnd, when " writing ", VNEG_C=VNEG=-4V), Hven2=1, Yread=1, PMOS P1 turn-offs; Control signal Ypre=0, voltage Ylvb=1, PMOS P2 turn-offs, and NMOS N1 opens, and voltage Ylv output voltage is VCPW, closes high-voltage tube M2, plays the effect of high pressure isolation.

The shortcoming of foregoing circuit is, high-voltage tube M2 had not only done and selected pipe but also do isolated tube, and its high threshold voltage is in the time that external power source Vpwr5 is lower, and Time Created (Setup Time) is long and decoding process is more complicated, also can affect " reading " performance.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of column address decoding scheme of storer, shortens Time Created, improves performance.

For addressing the above problem, the column address decoding scheme of storer of the present invention, comprises:

Two phase inverters, the output of the first phase inverter is connected to form and connects with the input of the second phase inverter, input termination first control signal of the first phase inverter;

Three NMOS pipes, source is leaked and is connected to form cascaded structure successively, and the drain electrode of a NMOS pipe connects storage unit, the output terminal that the source electrode of the 3rd NMOS pipe is described decoding scheme;

One level translator, its input end connects respectively the second control signal and the 3rd control signal, and the output voltage of charge pump, the grid of output termination the 3rd NMOS pipe of level translator;

The grid of a described NMOS pipe connects the 4th control signal, and the grid of the 2nd NMOS pipe connects the output terminal of described the second phase inverter.

Further, described first and second NMOS pipe is for threshold voltage is lower than the low-threshold power pressure pipe of 0.6V, and the 3rd NMOS pipe is for threshold voltage is higher than the high threshold voltage pipe of 1.2V.

Further, described level translator connects charge pump, and the high pressure that charge pump produces offers the grid of the 3rd NMOS pipe of high threshold voltage by level translator, reduces the Time Created of the 3rd NMOS pipe.

Further, in the time of read operation, first, second, third NMOS manages abundant conducting, and memory cell voltages is delivered to the source electrode output of the 3rd NMOS from the drain electrode of a NMOS; While writing or wipe operation, described first, second and third NMOS all turn-offs, and forms isolation.

The column address decoding scheme of storer of the present invention, only uses place's level translator, has simplified circuit structure, and selection pipe is separated with isolated tube.It is nearly 1/3rd that low threshold value pipe makes to shorten Time Created, ensured memory data reading speed, and the circuit structure of simplification has also reduced memory chip area.

Brief description of the drawings

Fig. 1 is common column address decoding scheme schematic diagram;

Fig. 2 is column address decoding scheme schematic diagram of the present invention.

Embodiment

The column address decoding scheme of storer of the present invention, as shown in Figure 2:

After two phase inverter Inv1, Ivn2 input and output are in series, the output terminal of the second phase inverter Ivn2 connects the grid of the 2nd NMOSN2, the drain electrode of the 2nd NMOS N2 connects the source electrode of a NMOS pipe N1, the drain electrode of the one NMOS N1 meets storage unit output voltage CL, and the grid of a NMOS N1 is the input end of the 4th control signal Yev; Input termination the first control signal Ypre of the first phase inverter Inv1.

The drain electrode of the 3rd NMOS M1 connects the source electrode of the 2nd NMOS N2, and the source electrode of the 3rd NMOS M1 is output terminal.

An above-mentioned NMOS pipe N1, the 2nd NMOS pipe N2 is low-threshold power pressure pipe, and the 3rd NMOS pipe M1 is high threshold voltage pipe.

One level translator LS meets respectively the second control signal Hven2, the 3rd control signal VCPW and charge pump output VPOS_R, and the output of level translator LS connects the grid of high-voltage tube M1.

Be more than the circuit structure of described decoding scheme, in the time of the column address decoding scheme work of storer:

When read operation: the 3rd control signal VCPW=vgnd, the second control signal Hven2=0, level translator LS is by charge pump High voltage output Ypump=VPOS_R=4V, the abundant conducting of isolated tube M1, reduce significantly the Time Created that high pressure isolated tube M1 wastes compared with hour conducting at former input voltage Vpwr5, voltage Ylv and the 4th control signal Yev set high (Ylv sets high i.e. the first control signal Ypre and sets high), NMOS pipe N1, N2, the abundant conducting of M1, selected circuit transmission voltage CL to BL; In not selected column circuits, voltage Ylv=vgnd, NMOS N2 turn-offs, and CL voltage can not be transferred to BL end.

When wiping or write operation: when the 3rd control signal VCPW=VNEG_C(" wiping ", VNEG_C=vgnd, when " writing ", VNEG_C=VNEG), Voltage-output Ypump=VNEG_C, NMOS M1 and N2 and N1 all turn-off, and have played buffer action.

More than be the principle of work explanation of this circuit, this circuit has only been used a level translator LS of place, has simplified decoding scheme, and the threshold voltage of NMOS pipe N1 and N2 pipe is lower, and shortened the Time Created of high-voltage tube M1, has improved data reading performance.

These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. a column address decoding scheme for storer, is characterized in that: comprise:

2. the column address decoding scheme of storer as claimed in claim 1, is characterized in that: described first and second NMOS pipe is for threshold voltage is lower than the low-threshold power pressure pipe of 0.6V, and the 3rd NMOS pipe is for threshold voltage is higher than the high threshold voltage pipe of 1.2V.

3. the column address decoding scheme of the storer as described in claim 1 and 2, it is characterized in that: described level translator connects charge pump, the high pressure that charge pump produces offers the grid of the 3rd NMOS pipe of high threshold voltage by level translator, reduce the Time Created of the 3rd NMOS pipe.

4. the column address decoding scheme of storer as claimed in claim 1, is characterized in that: in the time of read operation, first, second, third NMOS manages abundant conducting, and memory cell voltages is delivered to the source electrode output of the 3rd NMOS from the drain electrode of a NMOS; While writing or wipe operation, described first second and third NMOS all turn-offs, and forms isolation.