US6975139B2 - Scalable non-blocking switching network for programmable logic - Google Patents

Scalable non-blocking switching network for programmable logic Download PDF

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US6975139B2
US6975139B2 US10/814,943 US81494304A US6975139B2 US 6975139 B2 US6975139 B2 US 6975139B2 US 81494304 A US81494304 A US 81494304A US 6975139 B2 US6975139 B2 US 6975139B2
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conductors
conductor
switches
sets
different
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US20050218928A1 (en
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Peter M. Pani
Benjamin S. Ting
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RPX Corp
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Advantage Logic Inc
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Priority to US10/814,943 priority Critical patent/US6975139B2/en
Priority to EP05724178A priority patent/EP1730841A4/en
Priority to PCT/US2005/006583 priority patent/WO2005104375A1/en
Priority to KR1020067022720A priority patent/KR101116943B1/ko
Priority to CN201110439666.3A priority patent/CN102571073B/zh
Priority to JP2007506180A priority patent/JP4588068B2/ja
Priority to CN200580010432XA priority patent/CN1938950B/zh
Priority to US11/218,419 priority patent/US7256614B2/en
Publication of US20050218928A1 publication Critical patent/US20050218928A1/en
Publication of US6975139B2 publication Critical patent/US6975139B2/en
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Priority to US11/823,257 priority patent/US7417457B2/en
Assigned to ADVANTAGE LOGIC, INC. reassignment ADVANTAGE LOGIC, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ADVANTAGE LOGIC, INC
Priority to US12/174,080 priority patent/US7557613B2/en
Priority to US12/472,305 priority patent/US7768302B2/en
Priority to US12/794,685 priority patent/US7863932B2/en
Priority to US12/955,738 priority patent/US7986163B2/en
Priority to US13/165,668 priority patent/US8242807B2/en
Priority to US13/551,011 priority patent/US8698519B2/en
Assigned to RPX CORPORATION reassignment RPX CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ADVANTAGE LOGIC, INC.
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1515—Non-blocking multistage, e.g. Clos
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing

Definitions

  • Embodiments of this invention relate to switching networks and, in particular to switching networks used with programmable logic circuits.
  • a programmable logic circuit also referred to as field programmable gate array (FPGA) is an off the shelf integrated logic circuit which can be programmed by the user to perform logic functions. Circuit designers define the desired logic functions and the circuit is programmed to process the signals accordingly. Depending on logic density requirements and production volumes, programmable logic circuits are superior alternatives in terms of cost and time to market.
  • a typical programmable logic circuit is composed of logic cells where each of the logic cells can be programmed to perform logic functions on its input variables. Additionally, interconnect resources are provided throughout the programmable logic circuit which can be programmed to conduct signals from outputs of logic cells to inputs of logic cells according to user specification.
  • Freeman in the U.S. Pat. No. 4,870,302 of 1989 describes a commercial implementation of a FPGA using neighborhood interconnects, short (length one, called single) distance interconnects, and global lines for signals such as clocks.
  • the short distance interconnects interact with the inputs and outputs of logic cells where each input is connected through switches to every short wire neighboring to a logic cell and horizontal and vertical short wires connect through a switch box in a junction.
  • El Gamal et al. in U.S. Pat. No. 4,758,745 introduces segmented routing where inputs and outputs of logic cells interact with routing segments of different lengths in one dimension.
  • the input conductor of a logic cell has full connections to the set of local conductors (e.g. for n-inputs and k-local conductors, there is n ⁇ k switches connecting the inputs to the local conductors.
  • a multiplexer (MUX) scheme may also be used so that the number of transistors is reduced.).
  • MUX multiplexer
  • the general interconnect resources are limited to one or two different lengths (i.e. singles of U.S. Pat. No. 4,870,302, local and chip length in U.S. Pat. No.
  • Camarota et al. in U.S. Pat. No. 5,144,166 and Kean in U.S. Pat. No. 5,469,003 introduce a routing scheme with more than two different lengths in both dimensions with limitations in the reach of those conductors. While U.S. Pat. No. 5,144,166 allows each wire to be selectively driven by more than one possible driving source, U.S. Pat. No. 5,469,003 is limited to be unidirectional in that each wire is hardwired to a MUX output. The connectivity provided in both U.S. Pat. No. 5,144,166 and U.S. Pat. No.
  • 5,469,003 are very low, based on the premises that either connections are neighborhood or relatively local, or logic cells itself can be used as interconnection resources instead of performing logic functions.
  • Ting in U.S. Pat. No. 5,457,410, U.S. Pat. No. 6,507,217, U.S. Pat. No. 6,051,991, U.S. Pat. No. 6,597,196 describe a multiple level architecture where multiple lengths of conductors interconnect through switches in a hierarchy of logic cells.
  • Young et al. in U.S. 2001/0007428 and U.S. Pat. No. 5,914,616 describe an architecture with multiple lengths of wires in two dimensions (three in each dimension) where for short local connections, a near cross-bar scheme is used where a set of logic cells outputs are multiplexed to a reduced set of output ports which then interface to other interconnect resources.
  • the longer wires generally fan-in into shorter length wires in a respective dimension.
  • Reddy et al. in U.S. Pat. No. 6,417,694 discloses another architecture where inter-super-region, inter-region, and local conductors are used.
  • a cross-bar scheme is used at the lowest level (using MUXs) for the local wires to have universal access to the inputs of the logic elements.
  • Reddy et al. in U.S. Pat. No. 5,883,526 discloses various schemes having circuit reduction techniques in the local cross-bar.
  • LUT Look Up Table
  • a common problem to be solved in any programmable logic circuit is that of interconnectivity, namely, how to connect a first set of conductors carrying signals to multiple sets of conductors to receive those signals where the logic cells originating the signals and the logic cells receiving the signals are spread over a wide area in an integrated circuit (i.e., M outputs of M logic cells where each output connects to inputs of multiple number of logic cells).
  • interconnectivity namely, how to connect a first set of conductors carrying signals to multiple sets of conductors to receive those signals where the logic cells originating the signals and the logic cells receiving the signals are spread over a wide area in an integrated circuit (i.e., M outputs of M logic cells where each output connects to inputs of multiple number of logic cells).
  • Complicated software is necessary to track interconnect resources while algorithms are used to improve interconnectability during the place and route stage implementing a custom design using the programmable logic circuit.
  • FIG. 1 illustrates an embodiment of a circuit with four four-input logic cells and two flip flops using a scalable non-blocking switching network (SN).
  • SN scalable non-blocking switching network
  • FIG. 2 illustrates one embodiment of a circuit using a stage-0 scalable non-blocking switching network (0-SN) with eleven M conductors accessing four sets of four N conductors.
  • FIG. 3 illustrates one embodiment of a circuit using two stage-0 scalable non-blocking switching networks with each 0-SN having five M conductors accessing four sets of two N conductors.
  • FIG. 4 illustrates one embodiment of a circuit using a stage-1 scalable non-blocking switching network (1-SN) with eleven M conductors accessing four sets of four N conductors through N sets of four intermediate conductors.
  • (1-SN) stage-1 scalable non-blocking switching network
  • FIG. 5 illustrates one embodiment of a circuit using a stage-1 scalable non-blocking switching network with twelve M conductors accessing four sets of four N conductors through fewer intermediate conductors.
  • FIG. 6 illustrates one embodiment of a circuit using a stage-1 scalable non-blocking switching network with twelve M conductors accessing four sets of four N conductors with stronger connectivity property.
  • FIG. 7 illustrates one embodiment of a reduced stage-1 scalable non-blocking switching network with fewer switches.
  • FIG. 8 illustrates one embodiment of a larger size stage-1 scalable non-blocking switching network.
  • FIG. 9 illustrates one embodiment of a stage-1 scalable non-blocking switching network with sixteen M conductors.
  • FIG. 10 is a block diagram illustrating one embodiment of a stage-2 scalable non-blocking switching network (2-SN) and a circuit with four logic circuits of FIG. 1 , each using the scalable non-blocking switching network of FIG. 9 .
  • FIG. 11A illustrates a block diagram embodiment of the stage-2 scalable non-blocking switching network of FIG. 10 .
  • FIG. 11B illustrates one embodiment of the first part of the stage-2 scalable non-blocking switching network of FIG. 11A .
  • FIG. 12 illustrates one embodiment of a stage-1 scalable non-blocking switching network implementing the second part of the 2-SN of FIG. 11A .
  • An innovative scalable non-blocking switching network which uses switches and includes intermediate stage(s) of conductors connecting a first plurality of conductors to multiple sets of conductors where each conductor of the first plurality of conductors is capable of connecting to one conductor from each of the multiple sets of conductors through the SN, is first described.
  • the scalable non-blocking switching network can be applied in a wide range of applications, when used, either in a single stage, or used hierarchically in multiple stages, to provide a large switch network used in switching, routers, and programmable logic circuits.
  • a scalable non-blocking switching network is used to connect a first set of conductors, through the SN, to multiple sets of conductors whereby the conductors in each of the multiple sets are equivalent or exchangeable, for example, the conductors of one of the multiple sets are the inputs of a logic cell (which can be the inputs of a LUT or inputs to a hierarchy of logic cells).
  • the scalable non-blocking switching network in this present invention allows any subset of a first set of conductors to connect, through the SN, to conductors of a second multiple sets of conductors, so that each conductor of the subset can connect to one conductor from each set of the multiple sets of conductors.
  • program controlled switch and switch are interchangeable in the context of this description: the terms program configured logic cell, logic cell, cell, Look Up Table (LUT), programmable logic cell are interchangeable in the context of this description; the terms conductor, signal, pin, port, line are interchangeable in the context of this description.
  • the present invention describes embodiments which use program control means to set the states of switches utilized, this control means can be one time, such as fuse/anti-fuse technologies, or re-programmable, such as SRAM (which is volatile), FLASH (which is non-volatile), Ferro-electric (which is non-volatile), etc.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • the concept of scalable non-blocking switching networks utilized in a programmable logic circuit described herein can be generally applied to allow unrestricted connections between a plurality of conductors to multiple sets of conductors, as long as the connection requirements do not exceed the available conductors.
  • a driver circuit may be coupled to the switch to improve the speed of the signal traversing those conductors.
  • a MUX scheme if desired, to either reduce loading on the conductor or to reduce circuit size, or both, depending on the process technology used.
  • the multiple switches are converted into a new switch mechanism where, the number of effective states are the same as the number of switches, connectivity is enabled by choosing the particular state (corresponding to the switch if multiple switches were used) in connecting two conductors and the states are determined by programmable control.
  • stage-0 scalable non-blocking switching network (0-SN), stage-1 scalable non-blocking switching network (1-SN), stage-2 scalable non-blocking switching network (2-SN) and extensions to multi-stage scalable non-blocking switching networks and the use of those scalable non-blocking switching networks hierarchically in providing interconnectivity to programmable logic circuits.
  • stage-0 scalable non-blocking switching network (0-SN)
  • stage-1 scalable non-blocking switching network (1-SN)
  • stage-2 scalable non-blocking switching network (2-SN)
  • extensions to multi-stage scalable non-blocking switching networks and the use of those scalable non-blocking switching networks hierarchically in providing interconnectivity to programmable logic circuits.
  • CLST4 cluster
  • Each of the logic cells 10 – 40 has four inputs 101 – 104 (N0[0–3]) for cell 10 , four inputs 105 – 108 (N1[0–3]) for cell 20 , four inputs 109 – 112 (N2[0–3]) for cell 30 and four inputs 113 – 116 (N3[0–3]) for cell 40 , with four conductors 121 – 124 as the four outputs for cells 10 – 40 respectively.
  • Switches 151 – 156 and 159 , 160 are used to control whether a logic cell output drives a Flip-Flop or the logic cell outputs to circuit 100 outputs 125 – 128 directly.
  • the Flip-Flops 50 , 60 output to circuit 100 outputs 125 – 128 using switches 157 , 158 , 161 and 162 .
  • conductor 131 can drive conductor 101 of cell 10 through switch 141 and conductor 105 of cell 20 through switch 142 .
  • conductor 132 can drive cells 30 and 40 through switches 143 and 144 , respectively.
  • Cell 20 can drive a neighboring CLST4 circuit (not shown in FIG. 1 ) through output 122 using switches 145 to conductor 133 .
  • Output 124 of cell 40 drives out to conductor 134 through switch 146 in FIG. 1 .
  • Three other signals 135 – 137 are used to control the Flip-Flops as SET, CLOCK, and CLEAR, respectively. Additionally, FIG.
  • the 1 has (X+1) conductors 180 (M[0 ⁇ X]) fanning in to drive the sixteen inputs 101 – 116 using a switch network MTX 200 .
  • the conductors M[0 ⁇ X] 180 are called M conductors where M is equal to the number of conductors (X+1) in the embodiment of FIG. 1 .
  • each Ni can have a different size without changing the connectivity property described herein.
  • M ⁇ N+1 scalable non-blocking switching network
  • the switch network 0-SN 300 allows any subset of M conductors 201 – 211 to drive one input conductor of each of the logic cells 10 – 40 using the switches of 300 without any blocking as long as the number of connections do not exceed the available interconnect resources (i.e., the number of M conductors driving the inputs of any of the logic cells can not exceed the number of inputs of the logic cell).
  • some area minimization can be accomplished. For example, using a SRAM memory cell with six transistors as the program control for each switch implemented using a passgate, the eight switches 221 – 228 of FIG. 2 per input line 101 will require fifty six transistors. Instead, an eight input MUX using three memory bits can be used to control eight states to effectively replace the eight SRAM bits and eight switches. In the MUX scheme, three bits, fourteen passgates and perhaps one inverter (to regenerate the signal) uses thirty four transistors which is a large reduction from the fifty six transistors used with eight SRAM memory cells as the program control for each switch. The loading on conductor 101 will be reduced using the MUX implementation while there are additional delays due to the eight to one MUX.
  • a first group of conductors is connected to multiple groups of equivalent conductors using a switch network.
  • a switch network For a 0-SN has been presented, where there are (M ⁇ N+1) ⁇ N ⁇ k switches to provide unrestricted connections between a first set of M conductors to multiple k sets of N conductors where any subset of M conductors can connect to one conductor to each of the k sets of N conductors using the 0-SN without any blockage.
  • FIG. 4 illustrates an alternative embodiment scheme where the number of switches used in the switch network can be greatly reduced without changing the connectivity property of the 0-SN.
  • FIG. 4 shows an embodiment where MTX 200 of FIG. 1 is represented by using a stage-1 scalable non-blocking switching network (1-SN).
  • the 1-SN 400 connects a M conductor of conductors 401 – 411 to a N conductor of conductors 101 – 116 using two switches of the 1-SN 400 plus one intermediate conductor. Instead of directly connecting the M conductors 201 – 211 to the k sets of N conductors 101 – 116 through the network 300 of FIG. 2 where 128 switches are used, the 1-SN 400 in FIG.
  • M[6] M[6]
  • N conductor 109 N conductor 109 by first connecting to an intermediate I conductor 454 through switch 437 and then to the N conductor 109 through switch 441 of sub-network 450 .
  • the same M conductor 407 can connect to N conductors 101 , 105 , and 113 through the same intermediate conductor 454 through switches 442 , 443 and 444 , respectively.
  • the 1-SN 400 of FIG. 4 has ninety six switches which is a 25% reduction in the number of switches compared with the 0-SN 300 of FIG. 2 .
  • the scalable non-blocking switching network is capable of connecting a M conductor to more than one conductor from each of k sets of N conductors; however, logically it is not necessary to connect to more than one conductor in each of the N conductors.
  • the first intermediate conductors I 1 are the four conductors 451 – 454 that associate with the first input for each of the N conductors, thus conductors 101 , 105 , 109 and 113 .
  • conductors 461 – 464 are the I 4 conductors associated with conductors 104 , 108 , 112 , and 116 .
  • the (M ⁇ N+1) switches for each conductor of the N conductors in a 0-SN are distributed amongst the corresponding I i conductors in FIG. 4 .
  • the eight switches 431 – 438 coupling the M conductors 401 – 408 are distributed to the I 1 conductors 451 – 454 where each of the I 1 conductors couples to [(M ⁇ N+1)/I 1 ] switches, which is two.
  • the number of intermediate conductors in each of the I i conductors is four.
  • different I i need not be a uniform number (as described below).
  • the 1-SN 400 of FIG. 4 allows the same connectivity property as the respective 0-SN 300 of FIG. 2 , connecting any conductor of the M conductors to one conductor of each k sets of N conductors through two switches and one intermediate conductor in 1-SN 400 .
  • any N-tuple of M conductors have the appropriate choice of switches to different N sets of I i conductors.
  • any subset of the N-tuple of M conductors has the same property connecting to the intermediate conductors.
  • each intermediate conductor of I i conductors is connectable to one N conductor in each of the k sets of N conductors.
  • any conductor of conductors 451 – 454 is connectable, through the switches in sub-network 450 , to conductors 101 , 105 , 109 and 113 .
  • any conductor of conductors 461 – 464 is connectable to conductors 104 , 108 , 112 and 116 through switches in sub-network 420 .
  • FIG. 5 illustrates an alternative embodiment of a 1-SN representing the MTX 200 of FIG. 1 .
  • a corresponding 0-SN would have one hundred and forty four switches and a cross bar would have one hundred and ninety two switches.
  • the connectivity property of the 1-SN 500 of FIG. 5 is the same as those discussed earlier with respect to 1-SN 400 of FIG. 4 with fewer intermediate conductors and switches.
  • the illustrations in FIG. 4 and FIG. 5 have the first set of intermediate I 1 conductors (conductors 451 – 454 of FIG. 4 and conductors 521 – 523 of FIG. 5 ) connecting to conductors 101 , 105 , 109 , 113 , which are the first input of each of the four logic cells 10 – 40 of FIG. 1 , through switches of sub-network 450 of FIG. 4 and switches of sub-network of 540 of FIG.
  • FIG. 6 illustrates an embodiment of a different version of a stage-1 scalable non-blocking switching network having a stronger connectivity property than the 1-SN 500 of FIG. 5 .
  • the twelve M conductors, 601 – 612 (M[0]–M[11]) of 1-SN 600 are connectable to all the conductors in each of the N sets of I i intermediate conductors 621 – 623 , 624 – 626 , 627 – 629 , 630 – 632 . This is in contrast to the coupling to (M ⁇ N+1) conductors of the M conductors in FIG. 4 and FIG. 5 .
  • conductors 601 – 612 are connectable to I 1 conductors 621 – 623 through the switches in sub-network 620 .
  • Conductors 601 – 612 are connectable to I 2 conductors 624 – 626 through the switches in sub-network 640 .
  • Conductors 601 - 612 are connectable to I 3 conductors 627 – 629 through the switches in sub-network 650 .
  • Conductors 601 – 612 are connectable to I 4 conductors 630 – 632 through the switches in sub-network 660 .
  • the twelve M conductors 601 – 612 in FIG. 6 have a stronger connectivity property compared to the 1-SN 500 of FIG.
  • any conductor of M/I i conductors can be program selected to connect to a specific N conductors of any of the k sets.
  • FIG. 7 illustrates an embodiment where the number of switches in the embodiment of FIG. 6 is reduced without much change to the connectivity property of the 1-SN.
  • FIG. 7 represents the reduction where conductor 601 is shorted to conductor 621 , conductor 602 is shorted to conductor 624 , conductor 603 is shorted to conductor 627 , and conductor 604 is shorted to conductor 630 in FIG. 6 ; where the sixteen switches in sub-network 670 of FIG. 6 are deleted and the number of switches is eighty in FIG. 7 instead of ninety six in FIG. 6 .
  • the 1-SN 800 provides a large reduction in number of switches required compared to that of a 0-SN.
  • M is less than k ⁇ N and M conductors are the conductors carrying fan-in signals while the k sets of N conductors are the conductors to receive those fan-in signals. This need not be the case.
  • M is larger than k ⁇ N.
  • the conductors 101 – 104 , 105 – 108 , 109 – 112 and 113 – 116 in FIG. 6 as sixteen outputs from four clusters of logic cells and using the 1-SN for the purpose of output reduction from sixteen to twelve where any subset of twelve outputs out of sixteen outputs can be selected using the 1-SN.
  • the conductors 101 – 104 , 105 – 108 , 109 – 112 and 113 – 116 in the various figures need not be either inputs or outputs of logic cells but may be a plurality of equivalent conductors where connection to any of the conductor in one plurality of equivalent conductors is sufficient as opposed to connection to a particular conductor in the plurality of equivalent conductors.
  • interconnection architecture for programmable logic circuits, it may be important to provide reasonable connectivity and adequate interconnection resources based on engineering trade-offs such a circuit size, speed and ease of software to place and route a customer specified design.
  • R the expansion exponent in building up the hierarchy of circuits using scalable non-blocking switching networks.
  • any subset of the M conductors 901 – 916 can be individually connected through the 1-SN 900 to one conductor in each of the k sets of N conductors. Those M conductors themselves then become logically equivalent.
  • any signal originating somewhere outside the CLST4 circuit 100 of FIG. 1 to connect up to four inputs from each of the four logic cells 10 – 40 (one from conductors 101 – 104 , one from conductors 105 – 108 , one from conductors 109 – 112 , and one from conductors 113 – 116 ) of FIG. 1 ; it is only necessary to connect to one of the M conductors.
  • FIG. 10 illustrates a block diagram embodiment of a next level of circuit hierarchy CLST16 1000 using four sets of CLST4 100 of FIG. 1 (CLST4 1010 , CLST4 1020 , CLST4 1030 , CLST4 1040 of FIG. 10 ) where circuit MTX 200 is implemented using the 1-SN 900 of FIG.
  • M[0–47] sixteen conductors 1056
  • OE[0–7] four sets of N conductors 1060 , 1070 , 1080 , 1090 where each of the N conductors has sixteen conductors which correspond to the sixteen M conductors 901 – 916 of FIG. 9 .
  • sixteen conductors 1056 of the sixty four M conductors 1055 and 1056 directly connect to the four outputs 1065 , 1075 , 1085 , 1095 of the four CLST4 100 circuits 1010 , 1020 , 1030 , 1040 .
  • the sixteen conductors 1056 (OW[0–7], OE[0–7]) having four sets of four conductors and each of the four conductors corresponds to the four outputs 125 – 128 (O[0–3]) of the CLST4 100 circuit of FIG. 1 .
  • the expansion exponent R is again 1.0 in this circuit 1000 .
  • FIG. 11A illustrates an embodiment, in block diagram form, of circuit MTX16 1050 of FIG. 10 where the sixty four M conductors 1101 (M[0–47], OW[0–7], OE[0–7]) correspond to conductors 1055 and 1056 of FIG. 10 .
  • FIG. 11B illustrates a scheme where conductors 1101 connects to conductors 1160 through sub-network 1120 .
  • the connection scheme where conductors 1101 connect to conductors 1150 through sub-network 1110 , and to conductors 1170 through sub-network 1130 , and to conductors 1180 through sub-network 1140 are the same as sub-network 1120 of FIG. 11B .
  • an alternative implementation is to have (M ⁇ N0+1) ⁇ N0 switches instead.
  • Sub-networks 1155 , 1175 , 1185 of FIG. 11A are the same circuit as sub-network 1165 to interconnect conductors 1150 , 1170 , 1180 to conductors 1151 – 1154 , 1171 – 1174 , 1181 – 1184 of FIG. 11A , respectively.
  • the 1-SN 1165 of FIG. 12 uses the same 1-SN 900 of FIG. 9 . However, the 1-SN 1165 is one of four (sub-networks 1155 , 1165 , 1175 , 1185 ) in a second part of a stage-2 scalable non-blocking switching network (2-SN) 1050 of FIG.
  • each of the CLST4 circuits 1010 , 1020 , 1030 , 1040 corresponds to the CLST4 circuit 100 of FIG. 1 along with the 1-SN 900 of FIG. 9 .
  • the TA1 circuit 1165 of FIG. 12 connects conductors 1201 – 1216 selectively to conductors 1241 – 1256 ; 1241 , 1245 , 1249 , 1253 that are conductors 1161 (N0[4–7]) of FIG. 11A which correspond to four of the sixteen M conductors 1060 (C0[4–7] of C0[0–15]) of CLST4 1010 of FIG. 10 .
  • conductors 1242 , 1246 , 1250 , 1254 are conductors 1162 (N1[4–7]) of FIG. 11A which correspond to four of the sixteen M conductors 1080 (C1[4–7] of C1[0–15])of CLST4 1030 of FIG.
  • Conductors 1243 , 1247 , 1251 , 1255 are conductors 1163 (N2[4–7]) of FIG. 11A which correspond to four of the sixteen M conductors 1070 (C2[4–7] of C2[0–15]) of CLST4 1020 of FIG. 10 .
  • Conductors 1244 , 1248 , 1252 , 1256 are conductors 1164 (N3[4–7]) of FIG. 11A which correspond to four of the sixteen M conductors 1090 (C3[4–7] of C3[0–15]) of CLST4 1040 of FIG. 10 .
  • each of the N conductors of the k sets of N conductors in the different SNs does not need to be of uniform size.
  • a SN can be constructed with different sized N i 's where the maximum sized N i is used as the uniform sized new N and virtual conductors and switches can be added to the smaller sized N i making the N i appear to be of size N. Since the interconnection specification will not require the smaller sized N i to have more connections than N i , there is no change in the connectivity property of the SN. As an example, in FIG.
  • logic cell 10 of FIG. 1 instead of four sets of N conductors 101 – 104 , 105 – 108 , 109 – 112 , 113 – 116 as inputs for logic cells 10 – 40 , respectively, logic cell 10 of FIG. 1 has only three inputs 101 – 103 .
  • switches in FIG. 6 and intermediate conductors 621 – 632 stay the same, with the exception that the three switches in sub-network 680 and conductor 104 are “virtual” and can be taken out of the SN in FIG. 6 .
  • the first level of circuit hierarchy includes the circuit CLST4 100 of FIG. 1 with MTX 200 implemented as the 1-SN 900 of FIG. 9 where CLST4 100 has four four-input logic cells 10 – 40 and two flip-flops 50 , 60 as shown in FIG. 1 .
  • the next higher second level of circuit hierarchy is the CLST16 1000 circuits of FIG. 10 having four CLST4 100 circuits with a 2-SN MTX16 1050 as shown in FIG. 10 , where the network 1050 implementation is illustrated in FIG. 11A , FIG. 11B and FIG. 12 .
  • each of sixteen outputs 1065 , 1075 , 1085 , 1095 has unrestricted connectivity to every logic cell in the CLST16 1000 circuit and the other 48 M conductors 1055 of FIG. 10 can be treated as the N conductors of the CLST16 1000 in building up the next level of circuit hierarchy.
  • each of the four CLST4 circuits 1010 , 1020 , 1030 , 1040 of FIG. 10 are directly wired to sixteen M conductors 1056 , whose outputs can further connect, through a SN, to the next third level of circuit hierarchy using CLST16 1000 circuits as building blocks and the forty-eight other M conductors are the equivalent pins or input conductors for the CLST 1000 circuits to provide continued high connectivity in the programmable logic circuit.
  • the CLST 1000 circuit of FIG. 10 is illustrated using a 2-SN cascading four 1-SNs with sixty four M conductors 1055 , 1056 and sixteen four-input logic cells organized in four groups 1010 , 1020 , 1030 , 1040 using a total of 1280 switches amongst the various SNs: SN 1050 of FIG. 10 and SN 200 of FIG. 1 for each group 1010 – 1040 of FIG. 10 .
  • the CLST 1000 circuit of FIG. 10 can have an alternative implementation using a 1-SN with sixty four M conductors, k(e.g., 16) plurality of N(e.g., 4) conductors using the methods discussed in FIG. 9 .
  • a base logic cell (of a logic cell array with a SN) usually has either three inputs or four inputs, and it is reasonable to see, from the illustrated examples discussed above, the number of logic cells, k, in the base logic array should not be a small number, or rather, depending upon the size of N, k ⁇ N should be of reasonable size (e.g., the CLST4 100 circuit of FIG. 1 ) for a SN to be used efficiently as the interconnect network.
  • scalable non-blocking switching networks Using numerous embodiments and illustrations, a detailed description in building various scalable non-blocking switching networks is provided and used in various combinations to provide interconnect, both for inputs and outputs, for programmable logic circuits. Depending on technology and engineering considerations, variations in implementation of the scalable non-blocking switching networks may be used, including, but not exclusive of, the use of MUXs to reduce number of memory controls, switch reductions, etc.

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PCT/US2005/006583 WO2005104375A1 (en) 2004-03-30 2005-02-28 A scalable non-blocking switching network for programmable logic
CN200580010432XA CN1938950B (zh) 2004-03-30 2005-02-28 可编程逻辑的可扩展非阻断交换网络
KR1020067022720A KR101116943B1 (ko) 2004-03-30 2005-02-28 스위칭 네트워크를 사용하여 프로그래머블 로직을 구축하기 위한, 집적 회로, 전자 시스템, 방법, 상기 집적 회로의 접속 방법 및 상기 전자 시스템을 제공하는 방법
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US11/218,419 US7256614B2 (en) 2004-03-30 2005-09-01 Scalable non-blocking switching network for programmable logic
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US12/472,305 US7768302B2 (en) 2004-03-30 2009-05-26 Scalable non-blocking switching network for programmable logic
US12/794,685 US7863932B2 (en) 2004-03-30 2010-06-04 Scalable non-blocking switching network for programmable logic
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