US6952054B2 - Semiconductor package having interconnect with conductive members - Google Patents
Semiconductor package having interconnect with conductive members Download PDFInfo
- Publication number
- US6952054B2 US6952054B2 US10/820,674 US82067404A US6952054B2 US 6952054 B2 US6952054 B2 US 6952054B2 US 82067404 A US82067404 A US 82067404A US 6952054 B2 US6952054 B2 US 6952054B2
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- United States
- Prior art keywords
- interconnect
- contacts
- substrate
- conductive
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
Definitions
- This invention relates generally to semiconductor manufacture, and specifically to an interconnect having laser machined contacts for electrically engaging external contacts on semiconductor components such as dice, wafers and chip scale packages.
- Semiconductor components include external contacts that allow electrical connections to be made from the outside to the integrated circuits contained on the components.
- a semiconductor die for example, includes patterns of bond pads formed on a face of the die. At the wafer level, the bond pads are used for probe testing the integrated circuits on the die. At the die level, the bond pads are used for testing, and also for making electrical connections, such as wire bonds, for packaging. Typically, the bond pads comprise planar aluminum pads, or alternately solder bumps on solder wettable pads.
- chip scale packages also include external contacts.
- One type of chip scale package includes solder balls arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA).
- BGA ball grid array
- FBGA fine ball grid array
- the solder balls can be mounted on a substrate attached to a face of the die contained in the package.
- Metal traces, or other conductive elements associated with the substrate, form separate electrical paths between the solder balls on the substrate, and the bond pads on the die.
- a wafer probe card is one type of semiconductor interconnect.
- the probe card makes electrical connections between external contacts on a wafer under test, and test circuitry associated with a wafer handler.
- Another type of semiconductor interconnect is adapted to electrically engage unpackaged dice, or chip scale packages, packaged within a test carrier.
- the test carrier interfaces with a burn-in board, or other testing apparatus, adapted to apply test signals to the dice contained within the test carrier.
- This type of interconnect is described in U.S. Pat. No. 5,686,317 to Akram et al., and in U.S. Pat. No. 5,487,999 to Farnworth et al.
- a representative test carrier is described in U.S. Pat. No. 5,541,525 to Wood et al.
- a conventional multi chip module includes an interconnect formed of ceramic material or a glass filled resin.
- a multi chip module with a silicon interconnect is described in U.S. Pat. No. 5,578,526 to Akram et al.
- the interconnect includes contacts adapted to electrically engage the external contacts on the semiconductor component.
- the contacts comprise probe needles.
- the interconnect contacts can comprise projections formed on a silicon substrate and covered with a conductive layer.
- Interconnect contacts for multi chip modules can be configured to allow the dice to be flip chip mounted, or chip on board mounted, to the substrate.
- a semiconductor die, or chip scale package can include a hundred, or more, external contacts each having a diameter of only about 10 mils, and a pitch of only about 30 mils.
- a semiconductor wafer can include thousands of external contacts.
- interconnect contacts Making physical and electrical contact with small, densely spaced, external contacts on a semiconductor component requires small, densely spaced interconnect contacts.
- the external contacts typically include a native oxide layer that must be penetrated by the interconnect contacts to make low resistance electrical connections.
- the interconnects must include separate electrical paths, such as conductive traces, to each interconnect contact. Because of the required size and spacing of the interconnect contacts complex electrical paths must be formed on the interconnects. Signal delays and high resistivity can result from complex routing of electrical paths on the interconnects. Electrical problems, such as cross talk, and parasitic signals, can also occur between the interconnect contacts, and between associated electrical paths on the interconnect.
- the present invention is directed to an improved interconnect having contacts adapted to make reliable electrical connections to small, closely spaced external contacts on semiconductor components.
- an improved interconnect for semiconductor components and a method for fabricating the interconnect are provided.
- the interconnect broadly stated, comprises: a substrate; patterns of interconnect contacts on a face of the substrate, configured to electrically engage external contacts on the components; and conductive members in the substrate for providing direct electrical paths from the interconnect contacts to a backside of the substrate.
- the locations of the interconnect contacts matches the locations of the external contacts on the semiconductor components.
- the interconnect contacts For electrically engaging bumped external contacts, such as solder balls, the interconnect contacts comprise recesses covered with conductive layers.
- the interconnect contacts For electrically engaging planar external contacts, such as thin film bond pads, the interconnect contacts comprise projections covered with conductive layers.
- the interconnect contacts can include penetrating members adapted to penetrate native oxide layers on the external contacts.
- the conductive members of the interconnect comprise openings in the substrate and a conductive material, such as a metal, or a conductive polymer, deposited within the openings.
- the openings can be formed with a desired size and pitch using a laser machining process, and then insulated using a deposition process, or an oxidation process.
- the conductive members can also include external pads, and contact balls on the backside of the interconnect.
- the pads and contact balls facilitate electrical interface between the interconnect, and a mating electrical component, such as a test carrier, or a probe card fixture of a wafer handler.
- a pitch of the pads and contact balls on the backside of the interconnect can exactly matches a pitch of the interconnect contacts on the face of the interconnect.
- the interconnect can be used with the test carrier to provide a test system for testing singulated dice and chip scale packages.
- the interconnect can be used with a wafer handler to provide a test system for testing semiconductor wafers.
- the interconnect can be used to construct chip scale packages, and electronic assemblies, such as multi chip modules.
- FIGS. 1A-1D are schematic cross sectional views illustrating a method for fabricating an interconnect in accordance with the invention
- FIG. 2 is a plan view of the completed interconnect taken along section line 2 — 2 of FIG. 1 D and illustrating interconnect contacts on a substrate of the interconnect;
- FIG. 2A is a enlarged plan view of an alternate embodiment interconnect contact having a square peripheral configuration
- FIG. 2B is an enlarged plan view of an alternate embodiment interconnect contact having a pattern of penetrating members
- FIG. 3 is an enlarged schematic cross section view taken along section line 3 — 3 of FIG. 2 illustrating an interconnect contact electrically engaging a bumped external contact on a semiconductor component;
- FIG. 3A is an enlarged schematic cross sectional view of an alternate embodiment interconnect contact having a penetrating member
- FIG. 3B is an enlarged schematic cross sectional view of an alternate embodiment interconnect contact having a stepped configuration
- FIG. 3C is a schematic bottom view of alternate embodiment interconnect contacts formed with a pitch (P 1 ) that is offset from a pitch (P 2 ) of laser machined openings for the contacts;
- FIGS. 4A-4C are schematic cross sectional views illustrating a method for fabricating an alternate embodiment interconnect
- FIG. 5 is a schematic cross sectional view illustrating an interconnect contact for the interconnect of FIGS. 4A-4C electrically engaging a planar external contact on a semiconductor component;
- FIG. 6 is an exploded perspective view of a test carrier that includes an interconnect constructed in accordance with the invention.
- FIG. 6A is an end view of the test carrier taken along line 6 A- 6 A of FIG. 6 ;
- FIG. 6B is a bottom view of the test carrier taken along line 6 B- 6 B of FIG. 6 ;
- FIGS. 6C-6G are enlarged schematic cross sectional views taken along section lines ( 6 C- 6 G)—( 6 C- 6 G) of FIG. 6A illustrating different methods for mounting the interconnect to a base of the carrier;
- FIG. 7 is a schematic cross sectional view of a wafer level test system that includes an interconnect constructed in accordance with the invention.
- FIGS. 7A-7C are enlarged schematic cross sectional views of a portion of the wafer level test system illustrating electrical interface with different embodiments of the interconnect;
- FIG. 8 is a schematic cross sectional view of a chip scale package that includes an interconnect constructed in accordance with the invention.
- FIGS. 9A-9E are schematic cross sectional views of multi chip modules constructed in accordance with the invention.
- a substrate 10 can be provided.
- the substrate 10 comprises a wafer of material on which multiple interconnects will be fabricated using semiconductor circuit fabrication techniques, and then singulated by cutting the wafer. Such a process is referred to as a wafer level fabrication process.
- the substrate 10 comprises a semiconductor material such as monocrystalline silicon, germanium, silicon-on-glass, or silicon-on-sapphire.
- the substrate 10 can comprise a ceramic material, or of a glass filled resin material, such as FR-4.
- the substrate 10 includes a face side 14 and an opposing backside 16 .
- the face side 14 and backside 16 of the substrate are planar surfaces generally parallel to one another.
- a representative thickness of the substrate 10 can be from about 12 mils to 38 mils.
- patterns of recesses 12 can be formed on the face side 14 of the substrate 10 .
- the recesses 12 are etched, but can also be formed using a laser, or using a machining process.
- the recesses 12 can be etched by forming a mask (not shown) on the substrate 10 , such as a photopatterned resist mask, or a hard mask, and then etching the substrate 10 through openings in the mask, using a wet or dry etchant.
- the etch process can be either anisotropic or isotropic. With an anisotropic etch process, the recesses 12 will have planar sidewalls, sloped at an angle of about 54.6° with respect to the face side 14 of the substrate 10 , substantially as shown in FIG. 1 A.
- One suitable etchant for performing an anisotropic etch of the substrate 10 is a solution of KOH:H 2 O. With an isotropic etch process, the recesses 12 will have curved sidewalls (not shown).
- One suitable etchant for performing an isotropic etch of the substrate 10 is a mixture of HF, HNO 3 and H 2 O.
- a size and shape of the recesses 12 will be determined by the openings in the etch mask used to etch the substrate 10 .
- the size and shape of the recesses 12 corresponds to a size and shape of external contacts 18 ( FIG. 3 ) on a semiconductor component 20 ( FIG. 3 ) to be electrically engaged by the interconnect.
- the external contacts 18 comprise metal bumps on a die, or a chip scale package.
- the external contacts can be arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA).
- the recesses 12 are sized and shaped to retain and electrically engage the external contacts 18 (FIG. 3 ).
- a representative diameter, or width, of the recesses 12 can be from 2 mils to 50 mils or more. This diameter can be less than a diameter of the external contacts 18 so that only portions of the external contacts 18 will be contacted.
- a depth of the recesses 12 will be determined by an endpoint of the etch process.
- a representative depth for the recesses 12 can be from 0.25 mils to 25 mils or greater. Again this depth can be less than a height of the external contacts 18 , so that only portions of the external contacts will be contacted.
- a pitch or spacing of the recesses 12 will exactly match a pitch or spacing of the external contacts 18 ( FIG. 3 ) on the component (FIG. 3 ).
- a representative pitch or spacing between the recesses 12 can be from about 6 mils to 50 mils or greater.
- the recesses 12 For forming the interconnect contacts 32 shown in FIG. 2 , the recesses 12 have a generally circular peripheral configuration. For the interconnect contact 32 A shown in FIG. 2A , the recesses 12 have a generally square (or rectangular) peripheral configuration. For the interconnect contact 32 B shown in FIG. 2B , the recesses 12 can include penetrating members 22 adapted to penetrate the bumped external contacts 18 (FIG. 3 ).
- an insulating layer 24 can be formed on the surface of the face side 14 of the substrate 10 , and on the surfaces of the recesses 12 .
- an insulating layer 24 B can be formed on the backside 16 of the substrate 10 .
- the insulating layer 24 functions to insulate a bulk of the substrate 10 from conductive layers 26 to be subsequently formed on the substrate 10 .
- the insulating layer 24 B functions to insulate the bulk of the substrate 10 from components to be subsequently formed on the backside 16 of the substrate 10 .
- the insulating layers 24 and 24 B can be an insulating material, such as SiO 2 , or Si 3 N 4 , deposited to a desired thickness using CVD, or other deposition process.
- a SiO 2 layer can also be grown on exposed surfaces of the substrate 10 using an oxidizing atmosphere such as steam and O 2 at an elevated temperature (e.g., 950° C.).
- the insulating layers 24 and 24 B can also be a polymer, such as polyimide, deposited and planarized using a suitable process (e.g., spin-on-process).
- a suitable process e.g., spin-on-process
- a representative process includes spinning the polymer onto the front side 14 of the substrate and then onto the backside of the substrate 16 .
- a representative thickness of the insulating layer 24 can be from about a 100 ⁇ to several mils.
- conductive layers 26 are formed within the recesses 12 . Peripheral edges 28 of the conductive layers 26 are adapted to penetrate native oxide layers on the bumped external contacts 18 ( FIG. 3 ) to contact the underlying metal.
- the conductive layers 26 can be formed as a layer of a highly conductive metal such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals. Rather than being a single layer of metal, the conductive layers 26 can be formed as multi-layered stacks of metals (e.g., bonding layer/barrier layer).
- the conductive layers 26 can be formed using a metallization process (e.g., deposition, photopatterning, etching).
- a metallization process e.g., deposition, photopatterning, etching.
- An exemplary metallization process is disclosed in U.S. Pat. No. 5,607,818, incorporated herein by reference.
- the conductive layers 36 can also be formed using a plating process, such as electrolytic deposition, or electroless deposition.
- a representative thickness of the conductive layers 26 is from 600 ⁇ to 20000 ⁇ .
- the conductive layers 26 can also comprise a metal silicide, such as TiSi 2 , WSi 2 , TaSi 2 , MoSi 2 , and PtSi 2 .
- a metal silicide such as TiSi 2 , WSi 2 , TaSi 2 , MoSi 2 , and PtSi 2 .
- a silicon containing layer and a metal layer can be deposited on the substrate 10 , and then reacted to form a metal silicide.
- An exemplary metal silicide deposition process is disclosed in U.S. Pat. No. 5,686,317, incorporated herein by reference.
- other alloys such as TiN, TiW, TiC and NiB can be deposited using CVD or other deposition process.
- openings 30 can be formed through the conductive layers 26 , and through the substrate 10 to the backside 16 thereof.
- the openings 30 are formed using a laser machining process.
- a suitable laser machining apparatus is manufactured by General Scanning of Sommerville, Mass. and is designated a model no. 670-W.
- a representative diameter of the openings 30 is from 10 ⁇ m to 2 mils or greater.
- a representative laser fluence for forming the openings 30 through a substrate 10 comprising silicon and having a thickness of about 28 mils is from 2 to 10 watts/per opening at a pulse duration of 20-25 ns and at a repetition rate of up to several thousand per second.
- the wavelength of the laser beam 32 can be a standard infrared or green wavelength (e.g., 1064 nm-532 nm).
- the openings 30 are generally perpendicular to the face side 14 and backside 16 of the substrate 10 .
- the openings 30 are located along a longitudinal axis 31 which will be the center line of the completed contacts 32 (FIG. 1 D).
- the openings 30 can be offset from the center line of the interconnect contacts 32 C.
- the openings 30 can be outside of the contacts 32 E as in the embodiment shown in FIG. 5 .
- an additional insulating layer 24 A can be formed on the inside surfaces of the openings 30 , and on the back side 16 of the substrate.
- the insulating layer 24 A can be a grown or deposited oxide, such as SiO 2 , formed as previously described for insulating layer 24 . If the substrate 10 comprises an electrically insulating material, such as ceramic, or a glass filled resin, such as FR-4, the insulating layer 24 A (and also 24 ) is not required.
- conductive members 34 can be formed within the openings 30 .
- the conductive members 34 can comprise a metal, such as the previously described metals for the conductive layers 26 .
- the metal can be deposited within the openings 30 using a deposition process, such as CVD, electrolytic deposition or electroless deposition.
- a solder metal can be screen printed in the openings 30 , as well as with capillary action, or with a vacuum system using a hot solder wave.
- the conductive members 34 can be plugs that completely fill the openings 30 , or alternately as shown in FIG. 3B , can be layers that cover just the inside surfaces or sidewalls of the openings 30 .
- the conductive members 34 can comprise a conductive polymer, such as a metal filled silicone, or an isotropic epoxy. Suitable conductive polymers are sold by A.I. Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; and 3M, St. Paul, Minn. A conductive polymer can be deposited within the openings 30 , as a viscous material, and then cured as required. A suitable deposition process, such as screen printing, or stenciling, can be used to deposit the conductive polymer into the openings 30 .
- the conductive members 34 are formed within the openings in electrical contact with the conductive layers 26 .
- the conductive members 34 provide straight line electrical paths from the conductive layers 26 to the back side 16 of the substrate 10 .
- the electrical paths in addition to being direct also are insulated from one another by the insulating layers 24 A and by the bulk of the substrate 10 .
- the conductive members 34 can include pads 36 formed along the back side 16 of the substrate 10 .
- the pads 36 can have a circular, square, rectangular or other peripheral configuration.
- the pads 36 can be formed along a center line coincident to an axis 31 ( FIG. 1B ) of the conductive members 34 and to a center line of the conductive layers 26 .
- the pads 36 can be offset from a center line of the conductive layers 26 .
- the pads 36 (or 36 B) can be formed during formation of the conductive members 34 using a suitable mask (not shown), such as a hard mask, or a stencil mask.
- a suitable mask such as a hard mask, or a stencil mask.
- a metal can be blanket deposited on the back side 16 of the substrate and into the openings 30 and then etched to form the pads 36 (or 36 B).
- the pads 36 (or 36 B) can comprise a different material than the conductive members 34 , and can be formed using a separate deposition process.
- the conductive members 34 can include contact balls 38 formed on the pads 36 (or 36 B).
- the contact balls 38 can be formed of metal or a conductive polymer.
- the contact balls 38 provide connection points for making electrical connections from the outside to the conductive members 34 and conductive layers 26 . If the contact balls 38 are not provided on the pads 36 (or 36 B), the electrical connections from the outside can be made directly to the pads 36 (or 36 B).
- the electrical connections from the outside to the contact balls 38 can be by physical contact with a mating electrical connector (e.g., “POGO PIN”) of a test apparatus, or other electrical assembly, that will employ the completed interconnect 40 .
- the electrical connections to the contact balls 38 can also be a bonded connection such as a reflowed metal bond, or a cured conductive polymer bond.
- the contact balls 38 can be formed of a relatively hard metal such as nickel, copper, beryllium copper, alloys of nickel, alloys of copper, alloys of beryllium copper, nickel-cobalt-iron alloys and iron-nickel alloys. These relatively hard metals will allow the contact balls 38 to resist wear and deformation during continued usage of the interconnect 40 .
- the contact balls 38 can also comprise a base metal and an outer layer formed of a non-oxidizing metal such as gold, silver, copper or palladium.
- the contact balls 38 can comprise a solder alloy such as 95% Pb/5% Sn, 60% Pb/40% Sn, 63% In/37% Sn, or 62% Pb/36% Sn/2% Ag.
- the contact balls 38 can also be a conductive polymer such as an isotropic or anisotropic adhesive.
- One method for attaching the contact balls 38 to the pads 36 is by bonding pre-fabricated metal balls to the pads 36 (or 36 B).
- pre-fabricated metal balls are manufactured by Mitsui Comtek Corp. of Saratoga, Calif. under the trademark “SENJU SPARKLE BALLS”.
- the metal balls can be attached to the pads 36 (or 36 B) by soldering, laser reflow, brazing, welding, or applying a conductive adhesive.
- a solder ball bumper can also be used to bond the contact balls 38 to the pads 36 (or 36 B).
- a suitable solder ball bumper is manufactured by Pac Tech Packaging Technologies of Falkensee, Germany.
- the contact balls 38 can also be formed on the pads 36 (or 36 B) using a conventional wire bonder apparatus adapted to form a ball bond, and then to sever the attached wire.
- the contact balls 38 can also be formed by electrolytic deposition or electroless deposition of a metal to form bumps.
- a representative diameter for the contact balls 38 can be from about 4 mils to 50 mils or more.
- a pitch of the contact balls 38 can be from about 6 mils to 50 mils or more.
- the pitch of the pads 36 and the contact balls 38 can exactly match the pitch of the interconnect contacts 32 .
- the pitch of offset pads 36 B ( FIG. 1E ) can be different than the pitch of the interconnect contacts 32 .
- the pitch of the pads 36 B can be greater or smaller than the pitch of the contacts 32 .
- the completed interconnect 40 includes a dense array of interconnect contacts 32 formed on the face side 14 of the substrate 10 .
- Each interconnect contact 32 includes an associated opening 30 ( FIG. 3 ) and conductive member 34 (FIG. 3 ), which provide an insulated electrical path from the conductive layer 26 for the contact 32 , to the backside 16 of the substrate 10 .
- the openings 30 also permit the interconnect contacts 32 to be formed with a pitch small enough to accommodate dense arrays of external contacts 18 ( FIG. 3 ) on semiconductor components 20 (FIG. 3 ).
- the fabrication process illustrated in FIGS. 1A-1D can also be performed in a sequence wherein the recesses 12 and openings 30 are formed in the substrate 10 , and then the conductive layers 26 are formed.
- the conductive members 34 FIG. 1D
- the openings 30 can be formed first, followed by formation of an insulating layer 24 .
- a layer of metal can be blanket deposited on the face side 14 of the substrate 10 and into the openings 30 .
- the metal can then be patterned and etched to form the conductive layers 26 (FIG. 1 A).
- a metal can then be deposited on the backside 16 of the substrate 10 and patterned to form the pads 36 .
- the interconnect contact 32 is illustrated in electrical engagement with the external contact 18 on the semiconductor component 20 .
- the semiconductor component 20 can be a singulated bare semiconductor die, a semiconductor die contained on a wafer, or a semiconductor die contained in a chip scale package.
- the component 20 includes a passivation layer 42 on which the external contact 18 has been provided in electrical communication with integrated circuits on the component 20 .
- the interconnect contact 32 comprises the recess 12 in the substrate 10 , covered with the conductive layer 26 , and sized to electrically engage the bumped external contact 18 .
- the peripheral edge 28 of the conductive layer 26 penetrates native oxide layers present on the bumped external contact 18 .
- the component 20 and interconnect 40 are biased together to aid in the electrical engagement and penetration of the bumped external contact 18 .
- the interconnect contact 32 also includes the pad 36 and metal ball 38 .
- the pad 36 and metal ball 38 can be omitted for some applications.
- the pad 36 and metal ball 38 allow the interconnect 40 to be placed in electrical communication with corresponding contacts on a test apparatus, such as a test carrier or probe card fixture.
- interconnect contact 32 C with the penetrating member 22 is illustrated.
- the penetrating member 22 comprises a blade formed in the substrate 10 .
- the penetrating member 22 is adapted to penetrate the bumped external contact 18 and electrically engage the underlying metal.
- One method for forming the penetrating member 22 is to etch the substrate 10 at the same time that the recess 12 is etched.
- an etch mask for etching the recess 12 can include a portion adapted to cover the substrate 10 to form the penetrating member 22 .
- the penetrating member 22 becomes sharper as the etch process proceeds.
- two or more penetrating members 22 as in the interconnect contact 32 B (FIG. 2 B), rather than a single penetrating member can be formed in a desired pattern (e.g., cross pattern, parallel spaced pattern) within the same recess 12 .
- both can be covered by the conductive layer 26 , as previously described.
- the opening 30 can then be formed using a laser machining process as previously described. With the interconnect contact 32 C illustrated in FIG. 3A , the opening 30 is offset from a center line of the contact 32 C. This provides clearance for the penetrating member 22 which can be located along the center line of the contact 32 C.
- interconnect contact 32 D is illustrated.
- the interconnect contact 32 D is fabricated essentially as previously described for interconnect contact 32 (FIG. 3 ).
- the recess 12 A is stepped, and the conductive layer 26 A is formed over the stepped recess 12 A.
- the stepped recess 12 A allows the external contact 18 to deform to accommodate size variations in the external contacts 18 .
- some external contacts 18 may be oversized, and some may be undersized from a desired average diameter.
- the oversized external contacts 18 can deform into the lower portion of the recess 12 A.
- the undersized external contacts 18 can electrically engage only the upper portion of the recess 12 A.
- the substrate 10 A comprises ceramic or a glass filled resin, so that insulating layers 24 and 24 A ( FIG. 3 ) are not required.
- the conductive member 34 A comprises a conductive layer deposited on the sidewalls of the opening 30 rather than filling the entire opening 30 .
- the conductive member 34 A is configured for mating electrical engagement with an electrical connector 44 of a testing apparatus.
- the electrical connector 44 comprises a bump with a cylindrical portion 50 adapted to extend into the opening 30 , and electrically contact the conductive member 34 A.
- the conductive member 34 A can be formed using an ultrasonic forging process as described in U.S. Pat. No. 5,249,450, which is incorporated herein by reference.
- interconnect contacts 32 H are illustrated in a schematic bottom view.
- the interconnect contacts 32 H are fabricated substantially as previously described for interconnect contacts 32 (FIG. 3 ).
- the axis 31 ( FIG. 1B ) of the laser machined openings 30 are offset from a center line (or axis) of the interconnect contacts 32 H.
- the openings 30 are formed in an alternating pattern on opposite sides of adjacent interconnect contacts 32 H.
- a pitch P 1 of the interconnect contacts 32 H to match the pitch of the external contacts 18 ( FIG. 3 ) on the component 20 (FIG. 3 ).
- This arrangement permits an increased pitch P 2 for forming electrical connections to the pads 36 ( FIG. 3 ) and contact balls 38 ( FIG. 3 ) for the conductive members 34 ( FIG. 3 ) formed in the openings 30 .
- the increased pitch P 2 may be necessary to accommodate the pitch of mating electrical connectors (e.g., “POGO PIN”) of a test apparatus, or other electrical assembly, that will employ the completed interconnect.
- conductive traces 37 can be provided to form electrical paths between the interconnect contacts 32 H and the conductive members 34 ( FIG. 3 ) within the openings 30 . If desired, the conductive traces 37 can be portions of the conductive layers 26 (FIG. 3 ), or alternately separate members fabricated separately from the conductive layers 26 .
- the interconnect 40 A includes contacts 32 E ( FIG. 5 ) adapted to electrically engage planar external contacts 18 A ( FIG. 5 ) on a semiconductor component 20 A.
- the component 20 A comprises an unpackaged semiconductor die, and the external contacts 18 A comprise thin film bond pads.
- a substrate 10 B can be provided.
- the substrate 10 B is preferably a wafer of silicon on which multiple interconnects 40 A can be formed using a wafer level fabrication process. Following fabrication, the individual interconnects 40 A can be singulated from the wafer.
- projections 48 and penetrating members 22 A can be formed on the substrate 10 B using an etch process.
- An etch process for forming the projections 48 and penetrating members 22 A is disclosed in previously cited U.S. Pat. No. 5,686,317, which is incorporated herein by reference.
- the locations of the projections 48 corresponds to the locations of the external contacts 18 A ( FIG. 5 ) on the component 20 A.
- the penetrating members 22 A are adapted to penetrate the external contacts 18 A ( FIG. 5 ) to a limited penetration depth.
- the projections 48 are sized and shaped to electrically engage the contacts 18 A ( FIG. 5 ) while maintaining separation of the component 20 A and substrate 10 B of the interconnect 40 A. This separation helps to clear particulates and reduce cross talk between the component 20 A and interconnect 40 A.
- the openings 30 can be formed through the substrate 10 B using a laser machining process as previously described. With the openings 30 formed, an insulating layer 24 E can be formed on the surface of the substrate 10 B, and on the sidewalls of the openings 30 . The insulating layer 24 E also covers the projections 48 , and the penetrating members 22 A. The insulating layer 24 E can be formed using a deposition process, or an oxidation process as previously described for insulating layers 24 and 24 A (FIG. 1 D).
- conductive layers 26 E can be formed over the projections 48 and penetrating members 22 A.
- the conductive layers 26 E can be formed using the same materials and processes as previously described for conductive layers 26 (FIG. 1 A).
- conductive members 34 E can be formed in the insulated openings 30 using the same materials and processes as previously described for conductive members 34 (FIG. 1 D). Each conductive member 34 E is in electrical communication with an associated conductive layer 26 E.
- Pads 36 E and contact balls 38 E can also be formed on the conductive members 34 E as previously described for pads 36 ( FIG. 1D ) and contact balls 38 (FIG. 1 D).
- a test carrier 46 incorporating the interconnect 40 or 40 A is illustrated.
- the carrier 46 is adapted to hold a semiconductor component 20 A such as an unpackaged die or a chip scale package.
- the carrier 46 is adapted to electrically connect to a test apparatus such as a burn-in board 64 ( FIG. 6B ) in electrical communication with test circuitry 66 (FIG. 6 B).
- the test circuitry 66 is configured to apply test signals through the carrier 46 and the interconnect 40 or 40 A to the component 20 A.
- the carrier 46 includes a base 60 having a dense array of terminal contacts 70 (FIG. 6 B).
- the terminal contacts 70 electrically mate with corresponding electrical connectors, such as clips or socket contacts, on the burn-in board 64 .
- the carrier 46 also includes a force applying mechanism comprising a pressure plate 54 , a spring 56 and a clamp 58 .
- the clamp 58 includes clip portions 72 that mate with clip receiving portions 72 A on the base 60 .
- the spring 56 attaches to the clamp 58 and presses the pressure plate 54 against the interconnect 40 or 40 A. In the assembled carrier 46 , the spring 56 , clamp 58 and pressure plate 54 cooperate to bias the component 20 A against the interconnect 40 or 40 A.
- a seal member 68 surrounds the component 20 A and interconnect 40 or 40 A to prevent contaminants from entering an interior of the assembled carrier 46 .
- Assembly of the carrier 46 can be accomplished by optically aligning the component 20 A with the interconnect 40 or 40 A.
- a method of assembly using optical alignment is disclosed in U.S. Pat. No. 5,634,267, which is incorporated herein by reference.
- the interconnect 40 or 40 A establishes temporary electrical communication with the component 20 A.
- the interconnect 40 or 40 A can be mounted to the carrier base 60 in electrical communication with the terminal contacts 70 on the base 60 .
- FIGS. 6C-6G illustrate different methods for mounting and electrically connecting the interconnect 40 or 40 A to the base 60 .
- the interconnect 40 or 40 A includes pads 36 , as previously described, which are in electrical communication with the interconnect contacts 32 (FIG. 3 ).
- the carrier base 60 also includes pads 62 configured to physically and electrically contact the pads 36 on the interconnect 40 or 40 A.
- the pads 62 ( FIG. 6C ) on the carrier base 60 are in electrical communication with the terminal contacts 70 ( FIG. 6B ) on the carrier base 60 .
- the carrier base 60 can include a ceramic, plastic or glass filled resin substrate having internal conductors (not shown) which electrically connect the pads 62 ( FIG. 6C ) and the terminal contacts 70 (FIG. 6 B).
- the carrier spring 56 FIG. 6
- bonded connections 74 are formed between the pads 36 on the interconnect 40 or 40 A, and the pads 62 on the carrier base 60 . Again the pads 62 on the carrier base 60 are in electrical communication with the terminal contacts 70 (FIG. 6 B).
- the bonded connections 74 can be made by forming one of the pads 36 , 62 of solder, and another of the pads 36 , 62 of a solder wettable metal, and then reflowing one or both of the pads 36 , 62 .
- the interconnect 40 or 40 A includes pads 36 and contact balls 38 as previously described, which are in electrical communication with the interconnect contacts 32 (FIG. 3 ).
- the carrier base 60 includes a mating electrical connector 76 in electrical communication with the terminal contacts 70 (FIG. 6 B).
- the electrical connector 76 includes recesses sized and shaped to retain and electrically engage the contact balls 38 .
- the carrier spring 56 FIG. 6 ) provides the force for biasing the contact balls 38 on the interconnect 40 or 40 A, against the electrical connectors 76 on the base 60 .
- the interconnect 40 or 40 A includes the conductive member 34 A having an opening for receiving the cylindrical portion 50 of electrical connector 44 .
- the electrical connector 44 is in electrical communication with the terminal contacts 70 ( FIG. 6B ) on the carrier base 60 .
- the carrier spring 56 ( FIG. 6 ) provides the force for biasing the electrical connectors 44 on the base 60 into the openings provided by the conductive members 34 A.
- the interconnect 40 or 40 A includes pads 36 and contact balls 38 as previously described, which are in electrical communication with the interconnect contacts 32 (FIG. 3 ).
- the carrier base 60 includes conductive polymer pads 78 in electrical communication with the terminal contacts 70 (FIG. 6 B).
- the conductive polymer pads 78 can be an isotropic adhesive as previously described, or an anisotropic adhesive, such as a z-axis epoxy.
- the carrier spring 56 FIG. 6
- a bonded connection can be formed between the metal ball 38 and the conductive polymer pads 78 .
- the conductive polymer pads 78 can be deposited on the carrier base 60 in a B-stage, or semi-cured condition, and then cured under compression in contact with the metal balls.
- a wafer test system 80 constructed in accordance with the invention is shown.
- the test system 80 is configured to test semiconductor dice 52 contained on a wafer 20 W.
- the test system 80 includes a probe card 82 which includes the interconnect 40 or 40 A.
- the interconnect 40 or 40 A makes temporary electrical connections with external contacts 18 or 18 A on the wafer 20 W.
- the test system 80 also includes a wafer handler 84 , and a tester 86 having test circuitry 88 for applying and analyzing test signals.
- the wafer handler 84 interfaces with a test head 90 wherein the probe card 82 is mounted.
- the wafer handler 84 includes a wafer chuck 92 configured to move in X and Y directions to align the wafer 20 W with the probe card 82 , and in the Z direction to move the wafer 20 W into contact with the interconnect 40 or 40 A.
- the wafer handler 84 can also include an optical or mechanical alignment system (not shown) for aligning the wafer 20 W to the interconnect 40 or 40 A.
- One suitable wafer handler 84 is manufactured by Electroglass and is designated a Model 4080.
- the test system 80 also includes a prober interface board 94 for routing test signals from the tester 86 to the test head 90 to the probe card 82 .
- the prober interface board 94 can be mounted to the test head 90 .
- the prober interface board 94 can be in electrical communication with the tester pin electronics 96 in the test head 90 . Separate electrical paths 98 are provided from the test circuitry 88 in the tester 86 to the tester pin electronics 96 , and to the prober interface board 94 .
- the prober interface board 94 includes separate electrical paths 98 to the probe card 82 .
- the probe card 82 generally stated, comprises: a probe card substrate 100 , the interconnect 40 or 40 A, and a force applying mechanism 102 .
- the probe card substrate 100 preferably comprises an electrically insulating material such as a glass filled resin (e.g., FR-4), a ceramic or plastic.
- the probe card substrate 100 includes an opening 104 wherein the force applying mechanism 102 is mounted. Viewed from above, the opening 104 is generally rectangular shaped to accommodate a mating rectangular shape of the force applying mechanism 102 . However, as is apparent, a rectangular shape is merely exemplary.
- the probe card substrate 100 can be attached to a probe card fixture 106 mounted within the test head 90 . Threaded fasteners 108 can be used to removably attach the probe card substrate 100 to the probe card fixture 106 . If desired, the probe card substrate 100 can be a conventional probe card having the middle portion removed to form the opening 104 .
- the probe card fixture 106 can also be a conventional component. Conventional probe cards and probe card fixtures are available from Packard Hughes Interconnect, Los Angeles, Calif., and Wentworth Laboratories, Sunnyvale, Calif.
- the force applying mechanism 102 includes a base 110 which attaches to the probe card substrate 100 .
- the force applying mechanism 102 includes a plurality of spring loaded electrical connectors 112 mounted to a pin mounting plate 114 attached to the base 110 .
- the electrical connectors 112 physically and electrically engage the pads 36 (FIG. 7 A).
- electrical connectors 112 A ( FIG. 7B ) are configured to physically and electrically engage the contact balls 38 (FIG. 7 B).
- the electrical connectors 112 or 112 A can be commercially available spring loaded electrical connectors, such as “POGO PINS” manufactured by Pogo Industries of Kansas City, Kans. Other suitable spring loaded electrical connectors include “DURASEAL” connectors manufactured by IDI, Kansas City, Kans.
- FIG. 7C illustrates the embodiment wherein interconnect contacts 32 H are offset from the conductive members 34 as previously explained with reference to FIG. 3 C. In this embodiment the pitch of the pads 36 can be increased to match the pitch of the electrical connectors 112 .
- the interconnect 40 or 40 A is slidably mounted to a two piece interconnect support plate 116 that attaches to the probe card substrate 100 with threaded fasteners 118 .
- spring biased threaded fasteners 120 allow a planarity of the interconnect support plate 116 to be adjusted.
- the interconnect support plate 116 includes an opening 122 formed with a peripheral lip 124 for supporting the interconnect 40 or 40 A.
- the interconnect 40 or 40 A includes a stepped surface 126 that engages the lip 124 and allows the interconnect contacts 32 E ( FIG. 7A ) or 32 ( FIG. 7B ) to project from the interconnect support plate 116 .
- the stepped surface 126 of the interconnect 40 or 40 A can be formed by an etching process during fabrication of the interconnect 40 or 40 A.
- the peripheral lip 124 of the interconnect support plate 116 prevents the interconnect 40 or 40 A from separating from the interconnect support plate 116 .
- the interconnect 40 or 40 A is movable within the opening 122 in the Z-direction towards the electrical connectors 112 .
- the opening 122 can be sized to prevent excessive movement of the interconnect 40 or 40 A in the X and Y directions.
- dots of a compliant material such as silicone can be placed in a gap between the interconnect 40 or 40 A and opening 122 . The dots of compliant material can be used to retain the interconnect 40 or 40 A while allowing some Z-direction movement of the interconnect 40 or 40 A.
- the interconnect 40 or 40 A is maintained in a stationary position within the opening 122 by spring pressure exerted by the electrical connectors 112 or 112 A.
- the wafer 20 W can be overdriven in the Z-direction with respect to the interconnect 40 or 40 A, to move the interconnect 40 or 40 A in the Z-direction towards the electrical connectors 112 or 112 A.
- a contact force (F) with which the interconnect contacts 32 E ( FIG. 7E ) or 32 ( FIG. 7B ) press into the external contacts 18 A or 18 is generated by compression of the spring components of the electrical connectors 112 or 112 A.
- the force F exerted by the electrical connectors 112 or 112 A will be dependent on a spring constant, and amount of compression, of the spring components of the electrical connectors 112 or 112 A.
- a representative value for the force F can be from 0.10 oz to 1.5 oz per electrical connector 112 or 112 A.
- the term Z-direction overdrive refers to movement of the wafer 20 W or probe card 82 towards one another past the initial point of contact between the interconnect contacts 32 E or 32 and the external contacts 18 A or 18 .
- the Z-direction overdrive determines the amount of compression in the spring components of the electrical connectors 112 or 112 A and thus the magnitude of the force F.
- a representative amount of Z-direction overdrive can be from 0.25 mils to 8 mils.
- the force F can include two components F 1 and F 2 .
- F 1 is the force applied by the electrical connectors 112 or 112 A without overdrive.
- F 2 is the force applied by the electrical connectors 112 or 112 A from being deflected by the Z-direction overdrive distance.
- the chip scale package 130 includes a conventional semiconductor die 20 D having a face with bumped external contacts 18 formed thereon as previously described.
- the chip scale package 130 also includes an interconnect 40 C attached to the die 20 D.
- the interconnect 40 C comprises a substrate 10 C having interconnect contacts 32 F configured to electrically engage the bumped external contacts 18 .
- the interconnect contacts 32 F can be bonded to the bumped external contacts 18 using a compressive, or a non-compressive, bonding technique.
- the interconnect 40 C also includes conductive members 34 C in electrical communication with external contact balls 38 C.
- An underfill layer 128 can be used to fill the gap between the interconnect 40 C and the die 20 D.
- One suitable underfill material is “HYSOL BRAND FP4520” sold by Dexter Electronic Materials.
- FIG. 9A a chip scale package 130 A and a multi chip module 132 constructed in accordance with the invention is illustrated.
- the multi chip module 132 includes two or more chip scale packages 130 A in a stacked configuration.
- Each chip scale package 130 A includes an interconnect substrate 10 D and a semiconductor die 20 E.
- the interconnect substrate 10 D can be fabricated substantially as previously described for substrate 10 (FIG. 1 A).
- Each interconnect substrate 10 D includes patterns of conductors 138 having external bumps 140 formed thereon. Each interconnect substrate 10 D also includes an interconnect opening 136 wherein reflowed external contacts 18 R on bond pads 134 of the dice 20 E are bonded to the conductors 138 on the substrate 10 D.
- the chip scale packages 130 A can be fabricated substantially as described in U.S. Pat. No. 5,674,785, which is incorporated herein by reference.
- Each interconnect substrate 10 D also includes conductive members 34 D and pads 36 D in electrical communication with the conductors 138 .
- the conductive members 34 D and pads 36 D can be fabricated substantially as previously described for conductive members 34 and pads 36 shown in FIG. 1 D.
- the external bumps 140 can comprise a metal, or a conductive polymer, configured to form bonded connections with the pads 36 D on the conductive members 34 D.
- the multi chip module 132 A includes two or more stacked chip scale packages 130 B.
- Each chip scale package 130 B includes a semiconductor die 20 F mounted to an interconnect substrate 10 E in a chip on board configuration.
- the interconnect substrate 10 E can be fabricated substantially as previously described for substrate 10 (FIG. 1 A).
- wires 142 are wire bonded to the bond pads 134 on the dice 20 F, and to corresponding bond pads 144 on the interconnect substrate 10 E.
- a bumped die can be mounted to an interconnect substrate in a flip chip configuration substantially as shown in FIG. 8 .
- the interconnect substrate 10 E includes pads 36 F in electrical communication with the bond pads 144 .
- the interconnect substrate 10 E includes conductive members 34 F in electrical communication with the pads 36 F.
- the conductive members 34 F and pads 36 F can be fabricated substantially as previously described for the conductive members 34 and pads 36 shown in FIG. 1 D.
- the external bumps 140 A shown in FIG. 9B can comprise a metal, or a conductive polymer, configured to form bonded connections with the pads 36 F on the adjacent chip scale package 130 B.
- the bonded connections can be formed by a non-compressive process, such as reflowing bumps 140 A formed of solder onto pads 36 F formed of a solder wettable material.
- a compressive process such as thermocompression bonding, thermosonic bonding, or conductive polymer bonding, as previously described can be employed.
- the multi chip module 132 B includes an interconnect substrate 10 G having interconnect contacts 32 G comprising projections covered with conductive layers 26 G.
- the contacts 32 G are formed substantially as previously described for interconnect contacts 32 E (FIG. 5 ).
- Multiple patterns of contacts 32 G are formed on the substrate 10 G such that multiple semiconductor dice 20 F can be mounted to the substrate 10 G.
- the contacts 32 G establish electrical communication with the bond pads 134 on the dice 20 F.
- a similar multi chip module is described in U.S. Pat. No. 5,578,526, which is incorporated herein by reference.
- the interconnect substrate 10 G also includes conductive members 34 G in electrical contact with the conductive layers 26 G.
- the conductive members 34 G can be fabricated substantially as previously described for conductive members 34 (FIG. 1 D).
- the pads 36 G and contact balls 38 G can also be fabricated as previously described.
- two or more multi chip modules 132 B can be bonded to one another in a stacked configuration as previously described for multi chip modules 132 ( FIG. 9A ) and 132 A (FIG. 9 B).
- FIG. 9D illustrates a multi chip module 132 C in which bond pads 134 on multiple components 20 F are electrically engaged by interconnect contacts 32 I, substantially as previously described for multi chip module 132 B (FIG. 9 C).
- conductive members 34 H are offset from the contacts 32 I and from contact balls 38 H.
- Conductive layers 26 H establish electrical communication between the conductive members 34 H and the contacts 32 I.
- Conductive traces 37 H establish electrical communication between the conductive members 34 H and the contact balls 38 H.
- FIG. 9E illustrates a multi chip module 132 D in which external contacts 18 on multiple components 20 are electrically engaged by contacts 32 J, substantially as previously described for package 130 (FIG. 8 ).
- conductive members 34 J are offset from the contacts 32 J and from contact balls 38 J.
- Conductive layers 26 J establish electrical communication between the conductive members 34 J and the contacts 32 J.
- Conductive traces 37 J establish electrical communication between the conductive members 34 J and the contact balls 38 J.
- the invention provides an interconnect for semiconductor components and test system employing the interconnect.
- the interconnect can also be used to electrically engage semiconductor components in the construction of chip scale packages and other electrical components, such as multi chip modules.
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Abstract
Description
Claims (17)
Priority Applications (1)
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US10/820,674 US6952054B2 (en) | 1997-12-18 | 2004-04-08 | Semiconductor package having interconnect with conductive members |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US08/993,965 US6107109A (en) | 1997-12-18 | 1997-12-18 | Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate |
US09/385,606 US6294837B1 (en) | 1997-12-18 | 1999-08-30 | Semiconductor interconnect having laser machined contacts |
US09/961,646 US6833613B1 (en) | 1997-12-18 | 2001-09-25 | Stacked semiconductor package having laser machined contacts |
US10/820,674 US6952054B2 (en) | 1997-12-18 | 2004-04-08 | Semiconductor package having interconnect with conductive members |
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US09/961,646 Division US6833613B1 (en) | 1997-12-18 | 2001-09-25 | Stacked semiconductor package having laser machined contacts |
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US20040188824A1 US20040188824A1 (en) | 2004-09-30 |
US6952054B2 true US6952054B2 (en) | 2005-10-04 |
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US10/815,083 Expired - Fee Related US6998344B2 (en) | 1997-12-18 | 2004-03-31 | Method for fabricating semiconductor components by forming conductive members using solder |
US10/820,674 Expired - Fee Related US6952054B2 (en) | 1997-12-18 | 2004-04-08 | Semiconductor package having interconnect with conductive members |
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US09/961,646 Expired - Lifetime US6833613B1 (en) | 1997-12-18 | 2001-09-25 | Stacked semiconductor package having laser machined contacts |
US10/815,083 Expired - Fee Related US6998344B2 (en) | 1997-12-18 | 2004-03-31 | Method for fabricating semiconductor components by forming conductive members using solder |
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Also Published As
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US20040188824A1 (en) | 2004-09-30 |
US6998344B2 (en) | 2006-02-14 |
US6833613B1 (en) | 2004-12-21 |
US20040178491A1 (en) | 2004-09-16 |
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