US6867076B2 - Liquid crystal display for preventing galvanic phenomenon - Google Patents
Liquid crystal display for preventing galvanic phenomenon Download PDFInfo
- Publication number
- US6867076B2 US6867076B2 US10/396,333 US39633303A US6867076B2 US 6867076 B2 US6867076 B2 US 6867076B2 US 39633303 A US39633303 A US 39633303A US 6867076 B2 US6867076 B2 US 6867076B2
- Authority
- US
- United States
- Prior art keywords
- layer
- metal oxide
- source
- oxide layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 59
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 158
- 238000000034 method Methods 0.000 claims description 57
- 239000011241 protective layer Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 11
- 239000010936 titanium Substances 0.000 description 9
- 239000010408 film Substances 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910010252 TiO3 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Definitions
- the present invention relates to a method of manufacturing and structure of a liquid crystal display device. More specifically, the present invention relates to a method for manufacturing and structure of a liquid crystal display device that prevent the occurrence of the galvanic phenomenon, which occurs when a source/drain electrode formed of metal contacts a pixel electrode formed of ITO (Indium Tin Oxide).
- ITO Indium Tin Oxide
- Amorphous silicon (a-Si) TFT LCDs Thin Film Transistor Liquid Crystal Displays
- a-Si Amorphous silicon
- TFT LCDs Thin Film Transistor Liquid Crystal Displays
- the growth of the TFT-LCD industry along with wider acceptance of TFT-LCD related applications have occurred because of the improvements in screen resolution and screen size of TFT LCDs.
- the key to sustaining this growth trend is manufacturing TFT LCDs with greater productivity so that the price of TFT LCDs becomes more affordable to consumers.
- the manufacturing process must be simplified, and this can only occur if there is cooperation among all those involved in the manufacture of LCDs.
- FIGS. 1A-1C are cross-sectional views illustrating a process for manufacturing a LCD according to the related art.
- a buffer layer 102 is formed on an insulating substrate 100 such as glass. Thereafter, polysilicon is deposited on the buffer layer 102 . The polysilicon is then patterned by etching a selected portion so that the patterned polysilicon forms an active layer 108 . Alternatively, the active layer 108 may be formed by depositing amorphous silicon and then crystallizing it using laser radiation. Thereafter, a gate insulating layer 106 is formed on the buffer layer 102 and covers the active layer 108 . Next, a metal film is deposited on the gate insulating layer 106 by a method such as a sputtering process. The metal film is then patterned by an etching process and defines a gate electrode 110 .
- the gate electrode 110 is used as an ion-blocking mask while the entire surface of the structure is heavily doped with N type or P type impurities 112 .
- the doping process creates an active layer 108 on each side of the gate electrode 110 , thus forming an impurity region 108 a .
- the region 108 a will be used later as a source/drain region.
- a first contact hole h 1 is formed, which leaves the source/drain region 108 a exposed.
- the first contact hole h 1 formed within the first protective layer 120 , will be used as an electrical passage that connects the source/drain region 108 a to a source/drain electrode 122 .
- the source/drain electrode 122 is formed by depositing a metal film on the first protective layer 120 and patterning the metal film via an etching process so that the patterned metal film covers the first contact hole h 1 .
- the metal film is usually made of aluminum.
- a second protective layer 124 is formed so as to cover the entire surface of the structure.
- a second contact hole h 2 is now created which exposes the source/drain electrode 122 .
- This second contact hole h 2 formed within the second protective layer 124 , will be used as a passage for electrically connecting the source/drain electrode 122 and a metal connector line 126 .
- the metal connector line 126 is formed by depositing an ITO on the second protective layer 124 and then patterning the ITO via an etching process so that the patterned ITO covers the second contact hole h 2 . By this process, the metal connector line 126 is now connected to the source/drain electrode 122 .
- the ITO is deposited directly on the source/drain electrode 122 . Further, the ITO penetrates into the material forming the source/drain electrode due to the heat generated during the deposition process. However, this penetration results in the galvanic phenomenon occurring.
- the related art process tries to control the extent of the galvanic phenomenon by minimizing the contact area between the source/drain electrode and the metal connector line. Minimizing the contact area requires that the protective layer and the contact hole be formed in two steps. However, a two-step process results in an extremely complex manufacturing process and significantly increases the time and expense required for manufacturing the liquid crystal display device.
- preferred embodiments of the present invention provide a thin film transistor and a method of forming a thin film transistor in which a galvanic phenomenon is prevented without requiring additional etching steps.
- a method for manufacturing a thin film transistor includes providing a substrate including a source/drain electrode and a connector line and forming a metal oxide layer between the source/drain electrode and the connector line.
- a method for manufacturing a thin film transistor having a source/drain electrode on an insulating substrate includes forming a conductive layer to cover the source/drain electrode, heat treating the conductive layer in an oxygen atmosphere to form a metal oxide layer and forming a metal connector line on the metal oxide layer such that the metal connector line and the source/drain electrode are connected via the metal oxide layer.
- a method for manufacturing a thin film transistor having a source/drain electrode on an insulating substrate includes forming a data line on an insulating substrate, the data line being provided with a source electrode, forming an interlevel insulating layer on the insulating substrate so as to cover the data line, forming an active layer on the interlevel insulating layer, depositing a gate insulating layer on the active layer to form a gate electrode, selectively doping the active layer with impurities to form a source/drain region, forming a protective layer so to cover the interlevel layer, the active layer and the gate insulating layer, etching the gate insulating layer and the protective layer so as to expose the source electrode and the source/drain region, forming a conductive layer on the interlevel layer, the active layer, the gate insulating layer, the protective layer, the source electrode and the source/drain region, heat treating the conductive layer in an oxygen atmosphere to form a metal oxide layer, and forming a metal connector line
- a thin film transistor which includes an insulating substrate, a source/drain electrode on the insulating substrate, and a conductive layer that covers at least the source/drain electrode, and which defines a metal oxide layer after being heat treated.
- the thin film transistor has an insulating substrate, a source/drain electrode over a source/drain active region on a supporting surface of the insulating substrate, and a protective layer over the portions or the source/drain active region and a gate.
- the protective layer has via holes through which the source/drain electrode extends.
- a conductive layer covers the source/drain electrode and the supporting surface of the insulating substrate, and the conductive layer includes a metal oxide layer entirely covering the source drain electrode and entirely covering an upper surface of the protective layer.
- a metal connector line is formed on the metal oxide layer such that the metal connector line and the source/drain electrode are connected via the metal oxide layer.
- FIGS. 1A-1C are cross-sectional views illustrating a process for manufacturing a liquid crystal display apparatus according to the related art
- FIGS. 2A-2D are cross-sectional views illustrating a process for manufacturing a liquid crystal display apparatus according to a preferred embodiment of the present invention, where the preferred embodiment is applied to a coplanar structure;
- FIGS. 3A-3D are cross-sectional views illustrating a process for manufacturing a liquid crystal display apparatus according to another preferred embodiment of the present invention, where the preferred embodiment is applied to a reverse-staggered structure;
- FIGS. 4A-4C are cross-sectional views illustrating a process for manufacturing a liquid crystal display apparatus according to another preferred embodiment of the present invention, where the preferred embodiment is applied to a BBC (Buried Bus Coplanar) structure.
- a BBC Buried Bus Coplanar
- FIGS. 2A-2D are cross-sectional views illustrating a process for manufacturing a liquid crystal display apparatus according to a preferred embodiment of the present invention, where this preferred embodiment is applied to a coplanar structure.
- a buffer layer 202 is formed on an insulating substrate 200 such as glass.
- Polysilicon is then deposited on the buffer layer 202 preferably via chemical vapor deposition (CVD) and patterned preferably via an etching process to form an active layer 208 .
- the active layer 208 may be formed by crystallizing amorphous silicon.
- the buffer layer 202 is formed to prevent the silicon component of the polysilicon from diffusing into the insulating substrate 200 when it is deposited on the substrate 200 .
- a gate insulating layer 206 is formed on the insulating layer 200 and covers the active layer 208 .
- a metal such as aluminum (Al) or molybdenum (Mo) or other suitable metal is deposited preferably via a sputtering method to form a metal film on the gate insulating layer 206 .
- the metal film is used to form a gate electrode 212 .
- N type or P type impurity ions 214 are used to heavily dope the entire surface of the structure. Note that the energy intensity of the dopants 214 preferably varies depending upon the thickness of the gate insulating layer 206 . After the doping, on each side of the gate electrode 212 , there exists an impurity region 208 a within the active layer 208 . This impurity region 208 a is used as a source/drain region.
- a contact hole C 1 is formed and exposes the source/drain region 208 a .
- a source/drain electrode 222 is formed on the protective layer 220 .
- the source/drain electrode 222 is created by depositing a metal such as aluminum or molybdenum or other suitable metal preferably via the sputtering method and then patterning the deposited metal.
- the source/drain electrode 222 covers the contact hole C 1 and is in contact with the source/drain region 208 a.
- a conductive layer 224 is formed on the protective layer 220 and covers the source/drain electrode 222 .
- the types of metals commonly used for the conductive layer 224 includes titanium (Ti), indium (In), and zinc (Zn), but may include other suitable conductive materials.
- the conductive layer 224 undergoes a heat treatment 226 in which the heating temperature is preferably less than about 300° C.
- the conductive layer is oxidized and becomes a metal oxide layer 230 .
- the metal oxide layer 230 is transparent and remains conductive with good optical transmittance.
- titanium oxide TiO x
- TiO x titanium oxide
- Titanium is itself opaque, but only TiO is transparent while TiO 2 and TiO 3 are not.
- it is preferable to form TiO so that the metal oxide layer is transparent and conductive.
- the oxidation process is preferably to be controlled to produce TiO.
- an ITO is now deposited on the metal oxide layer 230 and then patterned preferably via an etching process so that an electrical connection with the source/drain electrode 222 is created.
- the ITO forms a metal connector line 232 which is connected to the source/drain electrode 222 and the source/drain region 208 a through the metal oxide layer 230 .
- metal oxide layer 230 is conductive at a portion which corresponds to a position of the source/drain electrode 222 and insulative at a portion which corresponds to a position of the insulating layer 206 .
- the present preferred embodiment of the present invention does not require a separate etching process due to the above properties.
- the metal oxide layer 230 is sufficiently transparent so that the underlying source/drain electrode 222 is shown, and thus, there is no need for a photo-etching process to remove the metal oxide layer 230 . Further, the galvanic phenomenon does not occur because the metal connector line 232 is not in direct contact with the source/drain electrode 222 .
- a variation of the preferred embodiment described above method involves patterning the ITO and the metal oxide layer 230 preferably via a simultaneous etching process which includes the use of a photo-mask for patterning the metal connector line 232 while the metal connector line 232 is being formed.
- FIGS. 3A-3D are cross-sectional views illustrating a process for manufacturing a liquid crystal display apparatus according to another preferred embodiment of the present invention, wherein this preferred embodiment is applied to a reverse staggered structure.
- a metal such as aluminum is sputtered on an insulating substrate 300 such as glass.
- the sputtered metal is then patterned preferably via an etching process to form a gate electrode 310 .
- a gate insulating layer 306 is then deposited on the insulating substrate 300 so as to cover the gate electrode 310 .
- an amorphous silicon layer and a metal layer are sequentially formed on the gate insulating layer 306 .
- the amorphous silicon layer and the metal layer are then patterned preferably via an etching process to form an active layer 308 and a source/drain electrode 322 .
- the patterning step also exposes a select portion of the gate electrode 310 .
- reference numeral 314 denotes an ohmic contact layer 314 interposed between the active layer 308 and the source/drain electrode 322 .
- a conductive layer 324 is formed on the structure and undergoes a heat treatment 326 in which the heating temperature is preferably less than about 300° C. During the heat treatment 326 , the conductive layer 324 is exposed to the air or to the oxygen in the surrounding atmosphere.
- a metal such as titanium (Ti), indium (In) or zinc (Zn) or other suitable metal is used for forming the conductive layer 324 .
- the conductive layer is oxidized into a metal oxide layer 330 .
- a metal connector line 332 preferably made of ITO is formed on the metal oxide layer 330 .
- the metal oxide layer 330 is transparent and remains conductive.
- the metal connector line 332 is now electrically connected to the source/drain electrode 322 through the metal oxide layer 330 .
- the metal oxide layer is transparent with excellent optical transmittance, it is possible to form the metal connector line 332 directly on the metal oxide layer 330 without performing a separate etching process. Similarly, the metal oxide layer 330 can be patterned while forming the metal connector line 332 .
- FIGS. 4A-4C are cross-sectional views illustrating a process for manufacturing a liquid crystal display apparatus according to another preferred embodiment of the present invention, wherein this preferred embodiment is applied to a BBC structure.
- a data line (not shown) provided with a source electrode 422 is formed on an insulating substrate 400 such as glass.
- silicon oxide is preferably deposited on the insulating layer 400 so as to cover the data line, and the deposited silicon oxide forms an interlevel insulating layer 406 .
- amorphous silicon is deposited on the interlevel insulating layer 406 and then crystallized using laser radiation.
- the crystallized silicon layer is then patterned preferably via an etching process such that the remaining portion of the crystallized silicon layer-forms an active layer 408 .
- a gate insulating layer 410 is deposited on the interlevel insulating layer 406 and covers the active layer 408 . Then a gate line (not shown) which is provided with a gate electrode 412 is formed on the gate insulating layer 410 . Using the gate electrode 412 as an ion-blocking mask, the entire surface of the structure is heavily doped with N type or P type impurities 414 . During this process, a source/drain region 408 a is created on each side of the gate electrode 412 . Note that the source/drain region 408 a is an impurity region within the active layer 408 .
- a protective layer 420 is formed on the gate insulating layer 410 . Thereafter, a contact hole is formed, which exposes the source electrode 422 and the source/drain region 408 a . Next, a conductive layer 424 is created on the protective layer 420 so as to cover the contact hole. As stated previously, preferred embodiments of the present invention use a metal such as titanium (Ti), indium (In) or zinc (Zn) or other suitable metal for forming the conductive layer 424 .
- the conductive layer 424 now undergoes a heat treatment 426 wherein the heating temperature is preferably less than about 300° C. During the heat treatment, the conductive layer 424 is exposed to air or oxygen in the surrounding atmosphere.
- the conductive layer becomes oxidized and turns into a metal oxide layer 430 .
- a metal connector line 432 is formed of ITO on the metal oxide layer 430 .
- the metal oxide layer 430 is transparent and remains conductive. Further, the transparency of the metal oxide layer 430 should be sufficient to permit the underlying layer to be shown, and it also should have excellent optical transmittance.
- the metal oxide layer 430 exhibits the dual property of being conductive at portions covering the source electrode 422 and the source/drain region 408 a while also being insulative at those portions covering the protective layer 420 , it is possible to form the metal connector line 432 without a separate etching process. Similarly, the metal oxide layer 430 can be patterned simultaneously with the metal connector line 432 while the metal connector line 432 is being formed.
- preferred embodiments of the present invention prevent the galvanic phenomenon from occurring without requiring an additional masking process by interposing a metal oxide layer between the source/drain electrode and the metal connector line.
- the metal oxide layer is transparent and remains conductive, and therefore does not need to be separately etched while forming the metal connector line. This eliminates the need to photo-etch the metal oxide layer, and thus simplifies the entire manufacturing process.
Abstract
Description
Claims (16)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/396,333 US6867076B2 (en) | 1998-12-21 | 2003-03-26 | Liquid crystal display for preventing galvanic phenomenon |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR98-56785 | 1998-12-21 | ||
KR1019980056785A KR100308854B1 (en) | 1998-12-21 | 1998-12-21 | Manufacturing method of liquid crystal display device |
US09/435,579 US6570183B1 (en) | 1998-12-19 | 1999-11-08 | Liquid crystal display for preventing galvanic phenomenon |
US10/396,333 US6867076B2 (en) | 1998-12-21 | 2003-03-26 | Liquid crystal display for preventing galvanic phenomenon |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/435,579 Division US6570183B1 (en) | 1998-12-19 | 1999-11-08 | Liquid crystal display for preventing galvanic phenomenon |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030183820A1 US20030183820A1 (en) | 2003-10-02 |
US6867076B2 true US6867076B2 (en) | 2005-03-15 |
Family
ID=19564253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/396,333 Expired - Lifetime US6867076B2 (en) | 1998-12-21 | 2003-03-26 | Liquid crystal display for preventing galvanic phenomenon |
Country Status (2)
Country | Link |
---|---|
US (1) | US6867076B2 (en) |
KR (1) | KR100308854B1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100973801B1 (en) * | 2003-04-23 | 2010-08-03 | 삼성전자주식회사 | Method for forming a metal wire, thin film transistor array panel the metal wire, and manufacturing method thereof |
KR100667087B1 (en) * | 2005-09-30 | 2007-01-11 | 삼성에스디아이 주식회사 | Thin film transistor and fabricating method of the same |
KR101472082B1 (en) | 2008-10-10 | 2014-12-16 | 삼성디스플레이 주식회사 | Liquid crystal display and method of fabricating the same |
KR20110081694A (en) * | 2010-01-08 | 2011-07-14 | 삼성모바일디스플레이주식회사 | Method for manufacturing thin film transistor and display device |
KR102002858B1 (en) * | 2012-08-10 | 2019-10-02 | 삼성디스플레이 주식회사 | Thin-film transistor substrate and method of manufacturing the same |
FR3033447B1 (en) * | 2015-03-03 | 2017-03-24 | Commissariat Energie Atomique | CONNECTED TRANSISTOR AND METHOD OF MANUFACTURING |
KR102461212B1 (en) * | 2016-02-17 | 2022-11-01 | 티씨엘 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | Display device and method for fabricating the same |
CN107863356A (en) * | 2017-11-06 | 2018-03-30 | 武汉华星光电半导体显示技术有限公司 | TFT substrate and preparation method thereof |
CN114690493B (en) * | 2022-03-18 | 2024-04-09 | 武汉华星光电技术有限公司 | Display Panel |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5422921A (en) * | 1991-11-15 | 1995-06-06 | Canon Kabushiki Kaisha | X-ray mask structure and manufacturing methods including forming a metal oxide film on a portion of an X-ray permeable film having no X-ray absorber thereon |
US5434439A (en) | 1990-01-26 | 1995-07-18 | Mitsubishi Denki Kabushiki Kaisha | Dynamic random access memory having stacked type capacitor and manufacturing method therefor |
JPH0862628A (en) | 1994-08-16 | 1996-03-08 | Toshiba Corp | Liquid crystal display element and its production |
JPH09203911A (en) | 1995-11-24 | 1997-08-05 | Semiconductor Energy Lab Co Ltd | Display device and manufacture of display device |
US5847410A (en) | 1995-11-24 | 1998-12-08 | Semiconductor Energy Laboratory Co. | Semiconductor electro-optical device |
-
1998
- 1998-12-21 KR KR1019980056785A patent/KR100308854B1/en not_active IP Right Cessation
-
2003
- 2003-03-26 US US10/396,333 patent/US6867076B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5434439A (en) | 1990-01-26 | 1995-07-18 | Mitsubishi Denki Kabushiki Kaisha | Dynamic random access memory having stacked type capacitor and manufacturing method therefor |
US5422921A (en) * | 1991-11-15 | 1995-06-06 | Canon Kabushiki Kaisha | X-ray mask structure and manufacturing methods including forming a metal oxide film on a portion of an X-ray permeable film having no X-ray absorber thereon |
JPH0862628A (en) | 1994-08-16 | 1996-03-08 | Toshiba Corp | Liquid crystal display element and its production |
JPH09203911A (en) | 1995-11-24 | 1997-08-05 | Semiconductor Energy Lab Co Ltd | Display device and manufacture of display device |
US5847410A (en) | 1995-11-24 | 1998-12-08 | Semiconductor Energy Laboratory Co. | Semiconductor electro-optical device |
Also Published As
Publication number | Publication date |
---|---|
US20030183820A1 (en) | 2003-10-02 |
KR20000041018A (en) | 2000-07-15 |
KR100308854B1 (en) | 2002-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI396885B (en) | Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating the thin film transistor substrate | |
US4778560A (en) | Method for production of thin film transistor array substrates | |
CA2167396C (en) | Silicon pixel electrode | |
US5995187A (en) | Liquid crystal display device in-plane-switching system with counter electrode in contact with liquid crystal | |
US7470572B2 (en) | Thin film transistor liquid crystal display and manufacturing method thereof | |
US6191452B1 (en) | Thin film transistor having a stopper layer | |
WO1999031720A2 (en) | Thin film transistors and electronic devices comprising such | |
US20070218576A1 (en) | Method for fabricating polysilicon liquid crystal display device | |
US6867076B2 (en) | Liquid crystal display for preventing galvanic phenomenon | |
US5989782A (en) | Method for producing liquid crystal display device | |
KR20010095001A (en) | Electrode substrate, method for producing the same, and display device including the same | |
KR20020001733A (en) | Thin film transistor and method of manufacturing the same | |
US6570183B1 (en) | Liquid crystal display for preventing galvanic phenomenon | |
US20040087064A1 (en) | Method of forming polysilicon thin film transistor | |
US6548828B2 (en) | Thin-film transistor and method of manufacturing thin-film transistor with tapered gate of 20 degrees or less | |
US5466618A (en) | Method for fabricating a thin film transistor for a liquid crystal display | |
US6569721B1 (en) | Method of manufacturing a thin film transistor to reduce contact resistance between a drain region and an interconnecting metal line | |
KR100490041B1 (en) | Thin Film Transistor for Liquid Crystal Display and Manufacturing Method | |
KR100195253B1 (en) | Manufacturing method of polysilicon thin film transistor | |
KR100329600B1 (en) | Method of Thin film Transistor | |
KR100275953B1 (en) | Method of manufacturing thin film transistor | |
KR100336899B1 (en) | Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device | |
KR100569265B1 (en) | Method for manufacturing tft-lcd | |
KR20000052288A (en) | Method of fabricating Thin film Transistor | |
KR970010688B1 (en) | Method for manufacturing thin film transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: LG DISPLAY CO., LTD., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:LG.PHILIPS LCD CO., LTD.;REEL/FRAME:020985/0675 Effective date: 20080304 Owner name: LG DISPLAY CO., LTD.,KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:LG.PHILIPS LCD CO., LTD.;REEL/FRAME:020985/0675 Effective date: 20080304 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |