KR20000052288A - Method of fabricating Thin film Transistor - Google Patents
Method of fabricating Thin film Transistor Download PDFInfo
- Publication number
- KR20000052288A KR20000052288A KR1019990020007A KR19990020007A KR20000052288A KR 20000052288 A KR20000052288 A KR 20000052288A KR 1019990020007 A KR1019990020007 A KR 1019990020007A KR 19990020007 A KR19990020007 A KR 19990020007A KR 20000052288 A KR20000052288 A KR 20000052288A
- Authority
- KR
- South Korea
- Prior art keywords
- metal film
- forming
- film
- etching
- impurity region
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 112
- 239000002184 metal Substances 0.000 claims abstract description 112
- 239000010410 layer Substances 0.000 claims abstract description 86
- 239000012535 impurity Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000010408 film Substances 0.000 claims description 171
- 238000005530 etching Methods 0.000 claims description 35
- 239000010936 titanium Substances 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- 239000011651 chromium Substances 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 43
- 229910052710 silicon Inorganic materials 0.000 abstract description 43
- 239000010703 silicon Substances 0.000 abstract description 43
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 박막 트랜지스터의 제조방법에 관한 것으로, 특히, 불순물이 도핑된 실리콘층에 연결되는 연결배선 형성 시, 도핑된 실리콘층과 이에 접촉되는 연결배선 형성용 투명도전막 간의 접촉저항을 효과적으로 개선시키고, 그에 따른 공정을 단순화시킬 수 있는 박막 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a thin film transistor, in particular, when forming a connection wiring connected to the doped silicon layer, the impurities effectively improve the contact resistance between the doped silicon layer and the transparent conductive film for forming a connection wiring contacted thereto, It relates to a method for manufacturing a thin film transistor that can simplify the process accordingly.
비정질실리콘(amorphous silicon) TFT-LCD(Thin Film Transistor -Liquid Crystal Display)는 노트북 PC 응용을 시작으로 모니터 등 다른 응용분야로 그 비중이 점차 증대하고 있다.Amorphous silicon thin-film transistor-liquid crystal displays (TFT-LCDs) are increasingly being used in other applications such as monitors, starting with notebook PC applications.
TFT-LCD 산업의 발전과 그 응용의 보편화는 크기의 증가와 해상도 증가에 의해 가속되었으며, 현재는 생산성 증대와 저가격화가 관건으로, 이를 위한 시도로 제조공정의 단순화의 수율 향상의 관점에서 노력이 요구되고 있다.The development of the TFT-LCD industry and its universal application have been accelerated by the increase in size and resolution, and nowadays, the increase in productivity and low price are the key issues. It is becoming.
도 1a 내지 도 1c는 종래기술에 따른 트랜지스터 제조공정도이다.1A to 1C are transistor manufacturing process diagrams according to the prior art.
도 1a와 같이, 유리 등의 절연기판(100) 상에 완충산화막(102)을 형성한다. 그리고, 절연기판(100)상에 완충산화막(102)을 덮도록 다결정실리콘을 증착한 후, 패턴식각하여 활성층(104)을 형성한다.As shown in FIG. 1A, a buffer oxide film 102 is formed on an insulating substrate 100 such as glass. After the polycrystalline silicon is deposited on the insulating substrate 100 to cover the buffer oxide film 102, the active layer 104 is formed by pattern etching.
이어서, 절연기판(100)상에 활성층(104)을 덮도록 절연막 및 금속막을 순차적으로 형성한 후, 활성층(104)의 일부를 덮도록 패턴식각하여 게이트절연막(106) 및 게이트전극(108)을 형성한다. 게이트전극(108) 형성용 금속막은 알루미늄(Al) 또는 몰리브덴(Mo) 등의 금속을 스퍼터링(sputtering)하여 얻는다.Subsequently, an insulating film and a metal film are sequentially formed on the insulating substrate 100 to cover the active layer 104, and then pattern-etched to cover a portion of the active layer 104 to form the gate insulating film 106 and the gate electrode 108. Form. The metal film for forming the gate electrode 108 is obtained by sputtering a metal such as aluminum (Al) or molybdenum (Mo).
이 후, 게이트전극(108)을 마스크로 이용하여 상기 구조를 갖는 기판(200) 전면에 p형 또는 n형의 불순물을 도핑시킨다. 불순물 도핑 결과, 활성층(104)에는 게이트전극(108) 양측에 불순물영역이 형성된다. 이 영역은 이 후의 공정에서 형성되는 소오스/드레인전극과 전기적으로 연결되는 소오스/드레인영역(S1)(D1)이 된다.After that, the p-type or n-type impurities are doped into the entire surface of the substrate 200 having the structure using the gate electrode 108 as a mask. As a result of impurity doping, an impurity region is formed in both sides of the gate electrode 108 in the active layer 104. This region becomes a source / drain region S1 (D1) electrically connected to a source / drain electrode formed in a later step.
도 1b와 같이, 상기 구조 전면에 산화실리콘 등을 증착한 후, 활성층(104)의 소오스/드레인영역(S1)(D1)의 일부를 노출시키는 각각의 콘택홀(h1)을 갖도록 패턴식각하여 층간절연막(110)을 형성한다.As shown in FIG. 1B, silicon oxide or the like is deposited on the entire surface of the structure, and then pattern-etched to have respective contact holes h1 exposing portions of the source / drain regions S1 and D1 of the active layer 104. The insulating film 110 is formed.
이 후, 층간절연막(110)상에 금속막을 형성한 후, 각각의 콘택홀(h1)을 덮어 소오스/드레인영역(S1)(D1)과 연결되도록 패턴식각하여 베리어금속막(buried metal layer)(112)을 형성한다.Subsequently, a metal film is formed on the interlayer insulating film 110, and then a pattern is etched so as to be connected to the source / drain regions S1 and D1 by covering each contact hole h1 to form a buried metal layer ( 112).
이 베리어금속막(112)은 저저항을 갖는 크롬(Cr) 또는 몰리브덴(Mo) 등의 금속을 스퍼터링하여 형성하며, 이 후에 형성될 불순물이 도핑된 실리콘층과 이에 연결되는 소오스/드레인전극 형성용 ITO(Indium Tin Oxide)금속 사이에 개재되어 실리콘층과 ITO금속 간의 접촉저항을 개선시키기 위한 것이다.The barrier metal film 112 is formed by sputtering a metal such as chromium (Cr) or molybdenum (Mo) having low resistance, and thereafter, for forming a silicon layer doped with impurities to be formed and a source / drain electrode connected thereto. It is interposed between ITO (Indium Tin Oxide) metal to improve the contact resistance between the silicon layer and the ITO metal.
도 1c와 같이, 절연막(110)상에 ITO 또는 SnOX등의 금속을 증착하여 투명도전막을 형성한 후, 베리어금속막(burried metal layer)(112)을 충분히 덮도록 패턴식각하여 소오스/드레인전극(116)(114)을 형성한다.As shown in FIG. 1C, a transparent conductive film is formed by depositing a metal such as ITO or SnO X on the insulating film 110, and then pattern-etched to sufficiently cover the burried metal layer 112. 116, 114.
불순물이 도핑된 실리콘층(소오스/드레인영역)에 투명도전막 형성 시, 실리콘이 산소와 반응하면서 실리콘층 표면에 산화막이 형성된다. 따라서, 도핑된 실리콘층과 투명도전막 간의 접촉저항이 커지게 된다. 이 접촉저항은 픽셀 TFT의 동작속도, 회로속도, 정전기방지회로에 영향을 준다. 따라서, 상기에서 언급한 종래의 기술에서는 불순물이 도핑된 실리콘층과 투명도전막 사이에 저저항금속인 베리어금속막을 개재시킴으로써 산화막이 형성되는 것이 방지된다.When the transparent conductive film is formed on the silicon layer (source / drain region) doped with impurities, an oxide film is formed on the surface of the silicon layer while silicon reacts with oxygen. Therefore, the contact resistance between the doped silicon layer and the transparent conductive film is increased. This contact resistance affects the operation speed, circuit speed, and antistatic circuit of the pixel TFT. Therefore, in the above-mentioned conventional technique, the oxide film is prevented from being formed by interposing a barrier metal film, which is a low resistance metal, between the silicon layer doped with impurities and the transparent conductive film.
그러나, 종래의 기술에서는 불순물이 도핑된 실리콘층과 투명도전막 사이에 저저항금속인 베리어금속막 형성할 경우, 베리어금속막을 패터닝하기 위하여 별도의 포토마스크가 추가됨에 따라 전체 공정절차가 복잡해졌다. 또한, 소오스/드레인전극용 콘택홀 형성 시, 콘택홀의 개구폭이 작은 경우에는 스텝커버리지(step coverage)가 불량하게 되어 투명도전막이 베리어금속막을 충분히 덮지 못하였다. 따라서, 콘택불량을 초래하는 문제점이 있었다.However, in the related art, when a barrier metal film, which is a low resistance metal, is formed between an impurity doped silicon layer and a transparent conductive film, the entire process procedure is complicated by adding a separate photomask to pattern the barrier metal film. In addition, when forming the contact hole for the source / drain electrode, when the contact hole has a small opening width, the step coverage is poor and the transparent conductive film does not sufficiently cover the barrier metal film. Thus, there is a problem that causes poor contact.
상기의 문제점을 해결하고자, 본 발명의 목적은 불순물이 도핑된 실리콘층과 이에 접촉되는 투명도전막 간의 접촉저항을 효과적으로 개선시킬 수 있는 박막 트랜지스터의 제조방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a thin film transistor that can effectively improve the contact resistance between the silicon layer doped with impurities and the transparent conductive film in contact therewith.
본 발명의 다른 목적은 포토공정 수를 줄여 공정단순화를 가져올 수 있는 박막 트랜지스터의 제조방법을 제공하려는 것이다.Another object of the present invention is to provide a method of manufacturing a thin film transistor which can reduce the number of photo processes to bring process simplicity.
상기 목적들을 달성하고자, 본 발명의 박막 트랜지스터의 제조방법은 절연기판 상에 활성층을 형성하는 공정과, 활성층 상에 게이트절연막을 개재시키어 게이트전극을 형성하는 공정과, 활성층에 게이트전극을 마스크로 이용하여 불순물을 도핑시키어 불순물영역을 형성하는 공정과, 상기 구조를 덮되, 불순물영역을 노출시키는 층간절연막을 형성하는 공정과, 노출된 불순물영역에 부분적으로 잔류되도록 금속막을 형성하는 공정과, 잔류된 금속막을 덮어 불순물영역과 연결되는 연결배선을 형성하는 공정을 구비한 것이 특징이다.In order to achieve the above objects, a method of manufacturing a thin film transistor of the present invention comprises the steps of forming an active layer on an insulating substrate, forming a gate electrode by interposing a gate insulating film on the active layer, using the gate electrode as a mask in the active layer Doping impurities to form an impurity region, forming an interlayer insulating film covering the structure, exposing the impurity region, forming a metal film to partially remain in the exposed impurity region, And a step of forming a connection wiring which covers the film and is connected to the impurity region.
본 발명의 박막 트랜지스터의 제조방법은 절연기판 상에 활성층을 형성하는 공정과, 활성층 상에 게이트절연막을 개재시키어 게이트전극을 형성하는 공정과, 활성층에 게이트전극을 마스크로 이용하여 불순물을 도핑시키어 불순물영역을 형성하는 공정과, 상기 구조를 덮되, 불순물영역을 노출시키는 층간절연막을 형성하는 공정과, 층간절연막 상에 식각선택비가 서로 다른 제 1금속막과 제 2금속막을 각각 형성하는 공정과, 제 1금속막 상에 제 2금속막 식각잔류물이 형성되도록 제 2금속막을 식각하는 공정과, 불순물영역과 제 2금속막 식각잔류물 사이에 제 1금속막 식각잔류물이 잔류되도록 제 1금속막을 식각하는 공정과, 제 1, 제 2금속막 식각잔류물을 덮어 불순물영역과 연결되도록 연결배선을 형성하는 공정을 구비한 것이 특징이다.The method of manufacturing a thin film transistor of the present invention comprises the steps of forming an active layer on an insulating substrate, forming a gate electrode through a gate insulating film on the active layer, and doping impurities using a gate electrode as a mask in the active layer. Forming a region, forming an interlayer insulating film covering the structure but exposing the impurity region, forming a first metal film and a second metal film having different etching selectivity on the interlayer insulating film, respectively; Etching the second metal film so that a second metal film etch residue is formed on the first metal film; and forming a first metal film etch residue between the impurity region and the second metal film etch residue. And a step of forming a connection wiring so as to be connected to the impurity region by covering the etching process and covering the first and second metal film etching residues.
도 1a 내지 도 1c는 종래기술에 따른 박막 트랜지스터 제조공정도이다.1A to 1C illustrate a thin film transistor manufacturing process according to the related art.
도 2a 내지 도 2c는 본 발명에 따른 제 1실시예로, 불순물이 도핑된 실리콘층과 이에 접촉되는 투명도전막 간의 접촉저항을 개선하기 위한 박막 트랜지스터 제조공정도이다.2A to 2C illustrate a thin film transistor manufacturing process for improving contact resistance between a silicon layer doped with impurities and a transparent conductive film contacting the doped silicon layer.
도 3a 내지 도 3c는 본 발명에 따른 제 2실시예로, 불순물이 도핑된 실리콘층과 이에 접촉되는 투명도전막 간의 접촉저항을 개선하기 위한 박막 트랜지스터 제조공정도이다.3A to 3C illustrate a thin film transistor manufacturing process for improving contact resistance between a silicon layer doped with impurities and a transparent conductive film contacting the doped silicon layer.
도 4a 내지 도 4d는 본 발명에 따른 제 3실시예로, 불순물이 도핑된 실리콘층과 이에 접촉되는 투명도전막 간의 접촉저항을 개선하기 위한 박막 트랜지스터 제조공정도이다.4A to 4D illustrate a thin film transistor manufacturing process for improving contact resistance between a silicon layer doped with impurities and a transparent conductive film contacting the doped silicon layer.
도 5a 및 도 5b는 본 발명에 따른 제 3실시예에 있어서, 콘택홀이 형성된 부분을 확대한 도면이다.5A and 5B are enlarged views of a portion where a contact hole is formed in a third embodiment according to the present invention.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200. 절연기판 102, 202, 302. 완충산화막100, 200. Insulation substrate 102, 202, 302. Buffered oxide film
104, 204, 304. 활성층 106, 206, 306. 게이트절연막104, 204, 304. Active layers 106, 206, 306. Gate insulating film
108, 208, 308. 게이트전극 110, 210, 310. 층간절연막108, 208, 308. Gate electrodes 110, 210, 310. Interlayer insulating film
114, 214, 314. 드레인전극 116, 216, 316. 소오스전극114, 214, 314. Drain electrodes 116, 216, 316. Source electrodes
220, 316, 318. 금속막 316a, 318a, ℓ. 금속막 식각잔류물220, 316, 318. Metal films 316a, 318a, l. Metal film etching residue
S1, S2, S3. 소오스영역 D1, D2, D3. 드레인영역S1, S2, S3. Source region D1, D2, D3. Drain area
h1, h2, h3. 콘택홀h1, h2, h3. Contact hole
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2c는 본 발명에 따른 제 1실시예로, 불순물이 도핑된 실리콘층과 이에 접촉되는 투명도전막 간의 접촉저항을 개선할 수 있는 박막 트랜지스터 제조공정도이다.2A to 2C illustrate a thin film transistor manufacturing process for improving contact resistance between a silicon layer doped with impurities and a transparent conductive film contacting the doped silicon layer.
도 2a 와 같이, 유리 등의 절연기판(200)상에 완충산화막(202)을 형성한다.As shown in FIG. 2A, a buffer oxide film 202 is formed on an insulating substrate 200 such as glass.
그리고, 완충산화막(202) 상에 다결정실리콘을 증착한 후, 소정영역 잔류되도록 식각패턴하여 활성층(204)을 형성한다. 활성층(204)은 다결정실리콘을 이용하는 방법 외에도 비정질실리콘을 증착한 후, 레이저빔 조사 등의 방법으로 결정화시킴으로서 얻을 수도 있다.After depositing polysilicon on the buffer oxide film 202, the active layer 204 is formed by etching patterns to remain in a predetermined region. The active layer 204 may be obtained by depositing amorphous silicon in addition to the method of using polycrystalline silicon and then crystallizing it by a method such as laser beam irradiation.
완충산화막(202)은 다결정실리콘 증착 시에 가해지는 열에 의해 실리콘 성분이 기판 쪽으로 확산됨으로써 발생되는 결점(defect)유발현상을 정지시키기 위한 것으로, 절연기판(200)과 활성층(204) 사이에서 완충역할을 한다.The buffer oxide film 202 is used to stop defects caused by diffusion of silicon components toward the substrate by heat applied during polycrystalline silicon deposition, and serves as a buffer between the insulating substrate 200 and the active layer 204. Do it.
그리고, 절연기판(200) 상에 활성층(204)을 덮도록 절연막 및 금속막을 순차적으로 형성한다. 이 후, 활성층(204)의 일부를 덮도록 금속막을 식각패턴함으로써 게이트전극(208)을 형성한다. 게이트전극(208)형성용 금속막은 알루미늄(Al) 또는 몰리브덴(Mo)등의 금속을 스퍼터링하여 얻는다. 이어서, 게이트전극(208)을 마스크로 이용하여 절연막을 식각함으로써 게이트절연막(206)을 형성한다.An insulating film and a metal film are sequentially formed on the insulating substrate 200 to cover the active layer 204. Thereafter, the gate electrode 208 is formed by etching the metal film to cover a part of the active layer 204. The metal film for forming the gate electrode 208 is obtained by sputtering a metal such as aluminum (Al) or molybdenum (Mo). Next, the gate insulating film 206 is formed by etching the insulating film using the gate electrode 208 as a mask.
그리고, 게이트전극(208)을 마스크로 이용하여 기판(200) 전면에 n형 또는 p형 불순물을 도핑시킨다. 불순물을 도핑시킨 결과, 활성층(204)에는 게이트전극(208) 양측부분에 불순물영역(첨선처리된 부분)이 형성되며, 이 영역은 이 후의 공정을 거쳐서 소오스/드레인전극과 연결되는 소오스/드레인영역(S2)(D2)이 된다.The n-type or p-type impurity is doped on the entire surface of the substrate 200 using the gate electrode 208 as a mask. As a result of doping impurities, impurity regions (wired portions) are formed on both sides of the gate electrode 208 in the active layer 204, which are source / drain regions connected to the source / drain electrodes through a subsequent process. (S2) (D2).
도 2b와 같이, 상기 구조 전면에 산화실리콘을 증착한 후, 활성층(204)이 소오스/드레인영역(S2)(D2)의 일부를 노출시키는 각각의 콘택홀(h2)을 갖도록 패턴식각하여 층간절연막(210)을 형성한다. 이 후, 층간절연막(210) 상에 각각의 콘택홀(h2)을 덮도록 금속막(220)을 형성한 후, 에치백(etch back)한다.As shown in FIG. 2B, after the silicon oxide is deposited on the entire structure, the interlayer insulating layer is etched by patterning the active layer 204 to have respective contact holes h2 exposing portions of the source / drain regions S2 and D2. Form 210. Thereafter, the metal film 220 is formed on the interlayer insulating film 210 to cover each contact hole h2, and then etched back.
이 금속막(220)으로는 저저항을 갖는 크롬(Cr), 몰리브덴(Mo), 티타늄(Ti), 니켈(Ni) 등이 이용된다.As the metal film 220, chromium (Cr), molybdenum (Mo), titanium (Ti), nickel (Ni), or the like having low resistance is used.
도 2c와 같이, 금속막 식각결과, 각각의 콘택홀(h2) 내의 소오스/드레인영역(S2)(D2)에는 건식식각 시 발생하는 마이크로 로딩효과(micro loading effect)에 의해 금속막이 식각되지 않고 잔류되어 있다. 잔류된 금속막은 도면번호 220a로 표시된다.As shown in FIG. 2C, the metal film is not etched and remains in the source / drain regions S2 and D2 in each contact hole h2 due to the micro loading effect generated during dry etching. It is. The remaining metal film is indicated by reference numeral 220a.
그리고 층간절연막(210) 상에 각각의 콘택홀(h2) 내의 소오스/드레인영역(S2)(D2)에 잔류된 금속막(220a)을 덮도록 ITO금속을 증착하여 투명도전막(214)(216)을 형성한다. 투명도전막(214)(216)은 불순물이 도핑된 실리콘층과 연결되는 연결배선이 된다.The ITO metal is deposited on the interlayer insulating film 210 to cover the metal film 220a remaining in the source / drain regions S2 and D2 in each contact hole h2, and thus, the transparent conductive films 214 and 216. To form. The transparent conductive films 214 and 216 become connection wirings connected to the silicon layer doped with impurities.
이 때, 소오스/드레인영역(S2)(D2)에는 잔류된 금속막(220a)이 덮고 있으므로, 실리콘이 산소와 반응하지 못한다.At this time, since the remaining metal film 220a is covered in the source / drain regions S2 and D2, silicon does not react with oxygen.
따라서, 본 발명에 따른 제 1실시예에서는 불순물이 도핑된 실리콘층과 투명도전막 사이에 건식식각 방법에 의해 금속막(220a)을 잔류시킴에 따라, ITO증착 시, 불순물이 도핑된 실리콘층(소오스/드레인영역)상에 산화막이 형성되는 것이 방지된다.Therefore, in the first embodiment according to the present invention, as the metal film 220a is left between the silicon layer doped with impurities and the transparent conductive film by a dry etching method, the silicon layer doped with impurities during ITO deposition (source (Drain region) is prevented from forming.
도 3a 내지 도3c는 본 발명에 따른 제 2실시예로, 불순물이 도핑된 실리콘층과 이에 접촉되는 투명도전막 간의 접촉저하됨을 개선할 수 있는 박막 트랜지스터의 제조를 보인 공정단면도이다.3A to 3C are cross-sectional views illustrating a fabrication of a thin film transistor capable of improving contact degradation between a silicon layer doped with impurities and a transparent conductive film contacting the doped silicon layer.
도 3a와 같이, 유리 등의 절연기판(200) 상에 완충산화막(202)을 형성한다.As shown in FIG. 3A, a buffer oxide film 202 is formed on an insulating substrate 200 such as glass.
그리고, 완충산화막(202) 상의 소정영역에 활성층(204)을 형성한 후, 게이트절연막을 개재시키어 게이트전극(208)을 형성한다. 이 후, 게이트전극(208)을 마스크로 이용하여 기판(200) 전면에 n형 또는 p형 불순물을 도핑시킴으로써 이 후의 공정을 거쳐서 소오스/드레인전극과 연결되는 소오스/드레인영역(S2)(D2)을 형성한다. 이상의 공정은 본 발명에 따른 제 1실시예에서의 도 2a와 동일한 방법으로 진행된다.After the active layer 204 is formed in a predetermined region on the buffer oxide film 202, the gate electrode 208 is formed through the gate insulating film. Thereafter, by doping n-type or p-type impurities on the entire surface of the substrate 200 using the gate electrode 208 as a mask, source / drain regions S2 (D2) connected to the source / drain electrodes through a subsequent process. To form. The above process proceeds in the same manner as in FIG. 2A in the first embodiment according to the present invention.
도 3b와 같이, 상기 구조 전면에 소오스/드레인영역(S2)(D2)의 일부를 노출시키는 각각의 콘택홀(h2)을 갖도록 패턴식각하여 층간절연막(210)을 형성한다.As shown in FIG. 3B, the interlayer insulating layer 210 is formed by pattern etching to have respective contact holes h2 exposing portions of the source / drain regions S2 and D2 on the entire structure.
그리고, 층간절연막(210) 상에 각각의 콘택홀(h2)을 덮도록 금속막(220)을 형성한 후, 습식 식각방법으로 케미컬처리함으로써 콘택홀(h2) 바닥면에 금속막을 잔류시킨다.Then, after forming the metal film 220 to cover each contact hole (h2) on the interlayer insulating film 210, the metal film is left on the bottom surface of the contact hole (h2) by chemical treatment by a wet etching method.
금속막은 크롬(Cr), 몰리브덴(Mo), 티타늄(Ti) 또는 니켈(Ni) 등이 이용되며, 약 50Å 두께로 형성된다. 처리액으로는 순수 (DI water:DeIonized water)에 희석된 HF(불산)용액이 이용된다.The metal film is made of chromium (Cr), molybdenum (Mo), titanium (Ti), nickel (Ni), or the like, and is formed to a thickness of about 50 GPa. As the treatment solution, HF (fluoric acid) solution diluted in pure water (DI water: Deionized water) is used.
즉, 습식 식각방법에 의해, 금속막(220)은 층간절연막(210) 상부 표면 및 콘택홀 측면 부분이 쉽게 제거된 반면, 콘택홀(h2) 바닥면 부분이 제거되지 않고 잔류된다.That is, by the wet etching method, the upper surface and the contact hole side portion of the interlayer insulating layer 210 are easily removed, whereas the bottom portion of the contact hole h2 is not removed.
도 3c와 같이, 콘택홀(h2) 바닥면에 잔류된 금속막은 도면번호 220b로 표시되며, 이하에서 220b는 잔류금속막이라 칭한다.As shown in FIG. 3C, the metal film remaining on the bottom surface of the contact hole h2 is denoted by reference numeral 220b, and hereinafter, 220b is referred to as a residual metal film.
그리고 층간절연막(210) 상에 각각의 콘택홀(h2) 내의 소오스/드레인영역(S2)(D2)에 잔류금속막(220b)을 덮도록 ITO금속을 증착하여 투명도전막(214)(216)을 형성한다.The transparent conductive films 214 and 216 are deposited by depositing ITO metal on the interlayer insulating film 210 to cover the residual metal film 220b in the source / drain regions S2 and D2 in each contact hole h2. Form.
이 투명도전막(214)(216)은 불순물이 도핑된 실리콘층과 연결되는 연결배선이 된다.The transparent conductive films 214 and 216 become connection wirings connected to the silicon layer doped with impurities.
이 때, 소오스/드레인영역(S2)(D2)에는 잔류금속막(220b)이 덮고 있으므로, 실리콘이 산소와 반응하지 못한다.At this time, since the residual metal film 220b is covered in the source / drain regions S2 and D2, silicon does not react with oxygen.
따라서, 본 발명에 따른 제 2실시예에서는 콘택홀(h2) 바닥면으로부터 노출되어 있는 불순물이 도핑된 실리콘층(소오스/드레인영역(S2)(D2))과 연결배선 형성용 투명도전막 사이에 습식식각 방법에 의해서 잔류금속막(220b)을 개재시킴에 따라, 투명도전막 증착 시에 상기 실리콘층 상에 산화막이 형성되는 것이 방지되며, 실리콘층과 투명도전막 간의 접착력을 강화시키어 접촉불량을 방지할 수 있다.Therefore, in the second embodiment according to the present invention, a wet layer is formed between a silicon layer doped with impurities exposed from the bottom surface of the contact hole h2 (source / drain regions S2 and D2) and a transparent conductive film for forming connection wiring. By interposing the residual metal film 220b by an etching method, an oxide film is prevented from being formed on the silicon layer during the deposition of the transparent conductive film, and the adhesion between the silicon layer and the transparent conductive film can be enhanced to prevent contact failure. have.
상술한 바와 같이, 제 1, 2실시예는 건식식각 또는 습식식각 등의 방법에 의해 콘택홀 바닥면으로부터 노출되어 있는 불순물이 도핑된 실리콘층(소오스/드레인영역(S2)(D2))과 투명도전막 사이에 잔류금속막{(220a)(220b)}을 개재시킨 것을 보였다.As described above, in the first and second embodiments, the dopant-doped silicon layer (source / drain region S2 (D2)) and transparency that are exposed from the bottom of the contact hole by a method such as dry etching or wet etching are used. It was shown that a residual metal film {(220a) (220b)} was interposed between the entire films.
도 4a 내지 도 4c는 본 발명에 따른 제 3실시예로, 불순물이 도핑된 실리콘층과 이에 접촉되는 투명도전막 간의 접촉저하됨을 개선할 수 있는 박막 트랜지스터 제조공정도이다. 도 5a 및 도 5b는 콘택홀이 형성된 부분만을 확대한 도면이다.4A to 4C illustrate a third embodiment of the present invention, which is a manufacturing process diagram of a thin film transistor capable of improving contact degradation between a silicon layer doped with an impurity and a transparent conductive layer contacting it. 5A and 5B are enlarged views of portions where contact holes are formed.
도 4a 와 같이, 본 발명에 따른 제 2실시예와 동일한 방법으로, 유리 등의 절연기판(300)상에 완충산화막(302) 및 활성층(304)을 순차적으로 형성한다. 그리고, 활성층(304)의 일부를 덮도록 게이트절연막(306)을 개재시키어 게이트전극(308)을 형성한다.As shown in FIG. 4A, the buffer oxide film 302 and the active layer 304 are sequentially formed on an insulating substrate 300 such as glass in the same manner as in the second embodiment of the present invention. The gate electrode 308 is formed with the gate insulating film 306 interposed to cover a portion of the active layer 304.
이 후, 게이트전극(308)을 마스크로 이용하여 기판(300) 전면에 n형 또는 p형의 불순물을 도핑시킴으로써 불순물영역을 형성한다. 이 영역은 이 후 공정을 거쳐서 소오스/드레인전극과 연결되는 소오스/드레인영역(S3)(D3)이 된다.Thereafter, an impurity region is formed by doping an n-type or p-type impurity on the entire surface of the substrate 300 using the gate electrode 308 as a mask. This region becomes a source / drain region S3 (D3) connected to the source / drain electrode through a subsequent process.
도 4b와 같이, 상기 구조 전면에 산화실리콘 등을 증착한 후, 활성층(304)의 소오스/드레인영역(S3)(D3)을 노출시키는 각각의 콘택홀(h3)을 갖도록 패턴식각하여 층간절연막(310)을 형성한다. 그리고, 층간절연막(310) 상에 각각의 콘택홀(h3)을 덮도록 제 1금속막(316) 및 제 2금속막(318)을 순차적으로 형성한다.As shown in FIG. 4B, silicon oxide or the like is deposited on the entire structure, and then pattern-etched to have respective contact holes h3 exposing the source / drain regions S3 and D3 of the active layer 304. 310). The first metal film 316 and the second metal film 318 are sequentially formed on the interlayer insulating film 310 to cover each contact hole h3.
제 1금속막(316) 및 제 2금속막(318)은 식각선택비가 다른 금속을 이용한다.The first metal film 316 and the second metal film 318 use metals having different etching selectivity.
예를 들면, 제 1금속막(316)으로 티타늄(Ti)을, 제 2금속막으로는 몰리브덴(Mo)을 각각 50 ∼ 150Å두께범위로 스퍼터링하여 형성한다.For example, the first metal film 316 is formed by sputtering titanium (Ti) and the second metal film is molybdenum (Mo) in a thickness range of 50 to 150 kPa.
이 후, 상기 구조를 갖는 기판에 CF/O2식각가스를 수십초동안 공급시키어 제 2금속막(318)을 식각한다. 상기의 CF/O2식각가스는 제 2금속막과 반응하여 일부를 식각시키지만, 제 1금속막(316)과는 거의 반응하지 않는다.Thereafter, the second metal film 318 is etched by supplying the CF / O 2 etching gas to the substrate having the structure for several tens of seconds. The CF / O 2 etching gas reacts with the second metal film to etch a portion thereof, but hardly reacts with the first metal film 316.
따라서, 도 5a와 같이, 제 1금속막(316) 표면에는 특히, 콘택홀(h3) 내의 제 1금속막(316) 표면에는 건식식각 시 발생하는 마이크로 로딩효과에 의해 제 2금속막(318)이 완전히 식각되지 않고 남은 제 2금속막 식각잔류물(318a)이 잔재되어 있다.Accordingly, as shown in FIG. 5A, the second metal film 318 may be formed on the surface of the first metal film 316, in particular, on the surface of the first metal film 316 in the contact hole h3 by a micro loading effect generated during dry etching. The second metal film etch residue 318a remaining without being completely etched remains.
도 4c와 같이, 제 1금속막(316)상에 Cl2/CF4/O2식각가스를 수십초 동안 공급시킨다.As shown in FIG. 4C, the Cl 2 / CF 4 / O 2 etching gas is supplied onto the first metal layer 316 for several tens of seconds.
상기의 Cl2/CF4/O2식각가스는 제 1금속막(316)과 반응함으로써 제 1금속막(316)을 식각하지만, 제 2금속막 식각잔류물(318a)과는 거의 반응하지 않는다. 따라서, 제 2금속막 식각잔류물(318a)은 상기의 Cl2/CF4/O2식각가스와 거의 반응하지 않으므로, 제 1금속막(316)을 식각하기 위한 마스크로서의 역할을 한다.The Cl 2 / CF 4 / O 2 etching gas etches the first metal film 316 by reacting with the first metal film 316, but hardly reacts with the second metal film etching residue 318a. . Therefore, since the second metal film etching residue 318a hardly reacts with the Cl 2 / CF 4 / O 2 etching gas, the second metal film etching residue 318a serves as a mask for etching the first metal film 316.
이 결과, 도 5b와 같이, 층간절연막(310) 표면에는 특히, 콘택홀(h3) 내의 층간절연막(310) 표면에는 제 2금속막 식각잔류물(316a) 및 제 1금속막 식각잔류물(318a)이 순차적으로 적층되어 잔재되어 있다. 도 4c에서, 도면번호 320은 표면에 제 2금속막 식각잔류물(318a)이 잔재되어 표면이 거친 제 1금속막을 도시한 것이다.As a result, as shown in FIG. 5B, the second metal film etch residue 316a and the first metal film etch residue 318a are formed on the surface of the interlayer insulating film 310, particularly on the surface of the interlayer insulating film 310 in the contact hole h3. ) Are sequentially stacked and remain. In FIG. 4C, reference numeral 320 illustrates a first metal film having a rough surface with a second metal film etch residue 318a remaining on the surface thereof.
도 4d와 같이, 상기 구조에 제 1, 제 2금속막 식각잔류물(316a)(318a)을 덮도록 ITO를 증착하여 투명도전막(314)을 형성한다. 도면부호 ℓ은 금속막 식각잔류물을 총칭한 것으로, 제 1, 제 2금속막 식각잔류물을 도시한 것이다.As shown in FIG. 4D, ITO is deposited on the structure to cover the first and second metal film etching residues 316a and 318a to form a transparent conductive film 314. Reference numeral L denotes a metal film etch residue, and shows first and second metal film etch residues.
따라서, 본 발명에 따른 제 3실시예에서는 불순물이 도핑된 실리콘층 표면에 제 1, 제 2금속막 식각잔류물(316a)(318a)이 잔재됨에 따라, 투명도전막 형성 시, 투명도전막이 불순물이 도핑된 실리콘층 표면에 잔재된 제 1, 제 2금속막 식각잔류물(316a)(318a)을 덮으므로, 결과적으로, 투명도전막과 금속막 식각잔류물이 접촉함으로써 접촉저항이 개선된다.Therefore, in the third embodiment according to the present invention, since the first and second metal film etching residues 316a and 318a remain on the surface of the silicon layer doped with impurities, the transparent conductive film may contain impurities when the transparent conductive film is formed. Since the first and second metal film etch residues 316a and 318a remaining on the surface of the doped silicon layer are covered, as a result, the contact resistance is improved by the contact between the transparent conductive film and the metal film etch residue.
상술한 바와 같이, 본 발명에 따른 제 1, 2실시예에서는 불순물이 도핑된 실리콘층과 투명도전막 사이에 건식식각 또는 습식식각 방법에 의해 저저항을 갖는 금속막을 개재시킴에 따라, 연결배선 형성용 투명도전막 증착 시에 실리콘이 산소와 반응하지 못하게 된다. 따라서, 불순물이 도핑된 실리콘층 상에 산화막이 형성되는 것이 방지되어 실리콘층과 투명도전막 간의 접촉저항이 개선된다.As described above, in the first and second embodiments of the present invention, a metal film having a low resistance is interposed between the silicon layer doped with impurities and the transparent conductive film by a dry etching method or a wet etching method, thereby forming connection wiring. During the deposition of the transparent conductive film, silicon does not react with oxygen. Therefore, the formation of an oxide film on the silicon layer doped with impurities is prevented, thereby improving the contact resistance between the silicon layer and the transparent conductive film.
본 발명에 따른 제 3실시예에서는 불순물이 도핑된 실리콘층과 투명도전막 사이에 식각선택비가 서로 다른 제 1, 제 2금속막 식각잔류물이 개재됨에 따라, 연결배선 형성용 투명도전막이 제 1, 제 2금속막 식각잔류물과 접촉하므로써 그에따른 접촉저항이 개선된다.According to the third embodiment of the present invention, since the first and second metal film etching residues having different etching selectivity are interposed between the silicon layer doped with the impurity and the transparent conductive film, the transparent conductive film for forming the connection wiring is formed as the first, second, and second conductive film layers. Contact with the second metal film etch residue is thereby improved.
또한, 본 발명에서는 불순물이 도핑된 실리콘층과 투명도전막 사이에 개재된 막(저저항 금속막 또는 금속막 식각잔류물 등)이 별도의 포토공정없이 형성가능함에 따라, 전체 공정이 단순화된 이점이 있다.In addition, in the present invention, since a film (such as a low resistance metal film or a metal film etch residue) interposed between an impurity doped silicon layer and a transparent conductive film can be formed without a separate photo process, the entire process is simplified. have.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990020007A KR100296112B1 (en) | 1999-01-15 | 1999-06-01 | Method of fabricating Thin film Transistor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR19990000909 | 1999-01-15 | ||
| KR1019990000909 | 1999-01-15 | ||
| KR1019990020007A KR100296112B1 (en) | 1999-01-15 | 1999-06-01 | Method of fabricating Thin film Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000052288A true KR20000052288A (en) | 2000-08-16 |
| KR100296112B1 KR100296112B1 (en) | 2001-07-12 |
Family
ID=26634589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990020007A KR100296112B1 (en) | 1999-01-15 | 1999-06-01 | Method of fabricating Thin film Transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100296112B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030020524A (en) * | 2001-08-29 | 2003-03-10 | 주식회사 현대 디스플레이 테크놀로지 | Method for manufacturing of thin film transistor |
| KR100504536B1 (en) * | 2002-03-29 | 2005-08-04 | 엘지.필립스 엘시디 주식회사 | Method for Manufacturing Liquid Crystal Display devices |
| KR100658069B1 (en) * | 2000-11-21 | 2006-12-15 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing liquid crystal display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210007074A (en) | 2019-07-09 | 2021-01-20 | 삼성디스플레이 주식회사 | Display device |
-
1999
- 1999-06-01 KR KR1019990020007A patent/KR100296112B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100658069B1 (en) * | 2000-11-21 | 2006-12-15 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing liquid crystal display device |
| KR20030020524A (en) * | 2001-08-29 | 2003-03-10 | 주식회사 현대 디스플레이 테크놀로지 | Method for manufacturing of thin film transistor |
| KR100504536B1 (en) * | 2002-03-29 | 2005-08-04 | 엘지.필립스 엘시디 주식회사 | Method for Manufacturing Liquid Crystal Display devices |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100296112B1 (en) | 2001-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6350995B1 (en) | Thin film transistor and manufacturing method therefore | |
| EP0304657B1 (en) | Active matrix cell and method of manufacturing the same | |
| US9761616B2 (en) | Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device | |
| US7755708B2 (en) | Pixel structure for flat panel display | |
| KR980012071A (en) | Manufacturing method of thin film transistor | |
| US7674658B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20020005968A (en) | Active matrix substrate, display device and method for manufacturing active matrix substrate | |
| KR100296112B1 (en) | Method of fabricating Thin film Transistor | |
| KR20110058356A (en) | Array substrate and method of fabricating the same | |
| KR100308854B1 (en) | Manufacturing method of liquid crystal display device | |
| US6713328B2 (en) | Manufacturing method of thin film transistor panel | |
| KR20000003173A (en) | Method of forming tft(thin film transistor) lcd(liquid crystal display) | |
| US6482685B1 (en) | Method for fabricating a low temperature polysilicon thin film transistor incorporating multi-layer channel passivation step | |
| KR100787805B1 (en) | Method for manufacturing pixel structure | |
| KR100837884B1 (en) | method for fabricating Liquid Crystal Display device | |
| KR100329600B1 (en) | Method of Thin film Transistor | |
| US6462793B1 (en) | Liquid crystal display device and method of fabricating the same | |
| KR100317619B1 (en) | Manufacturing Method of Thin Film Transistor | |
| KR100195253B1 (en) | Manufacturing method of polysilicon thin film transistor | |
| US8647980B2 (en) | Method of forming wiring and method of manufacturing semiconductor substrates | |
| KR0172880B1 (en) | Method of manufacturing liquid crystal display device | |
| US11307468B2 (en) | Array substrate and manufacturing method thereof | |
| KR100476055B1 (en) | a method for manufacturing of reflexible TFT LCD panel | |
| KR100687331B1 (en) | Method for manufacturing Thin Film Transistor | |
| US5523187A (en) | Method for the fabrication of liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment | ||
| FPAY | Annual fee payment | ||
| FPAY | Annual fee payment |
Payment date: 20150429 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20160428 Year of fee payment: 16 |
|
| FPAY | Annual fee payment |
Payment date: 20170413 Year of fee payment: 17 |
|
| FPAY | Annual fee payment |
Payment date: 20180416 Year of fee payment: 18 |
|
| FPAY | Annual fee payment |
Payment date: 20190417 Year of fee payment: 19 |
|
| EXPY | Expiration of term |