US6822644B1 - Method and circuit for driving capacitive load - Google Patents
Method and circuit for driving capacitive load Download PDFInfo
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- US6822644B1 US6822644B1 US09/559,633 US55963300A US6822644B1 US 6822644 B1 US6822644 B1 US 6822644B1 US 55963300 A US55963300 A US 55963300A US 6822644 B1 US6822644 B1 US 6822644B1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
- G09G3/2927—Details of initialising
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
Definitions
- An AC type plasma display panel utilizes a memory function of a dielectric layer that covers the electrodes. Namely, addressing is performed by a line scanning format for controlling charge quantity of the cell in accordance with display data, and then a sustaining voltage Vs having alternate polarity is applied to a pair of the electrodes.
- the sustaining voltage Vs satisfies the relationship (1) below.
- the application of the sustaining voltage Vs makes a cell voltage Vc (a sum of the applied voltage and the wall voltage, which is also referred to as an effective voltage) exceed the discharge starting voltage Vf only in the cell in which the wall charge exists, and causes the discharge.
- Vc a sum of the applied voltage and the wall voltage, which is also referred to as an effective voltage
- Vf the discharge starting voltage
- a step voltage whose maximum voltage is approximately 250-300 volts should be applied.
- plural bias voltage sources having different output voltages are prepared and one of them is selected to be connected to the electrode by using a switching device, so that the application of a step voltage is performed.
- the conventional circuit has a disadvantage in that plural power sources and switching devices are necessary for the number of steps of the step voltage, and so the circuit becomes large when increasing the number of steps.
- the waveform can be changed by setting the control timing of the switching device, the voltage difference between steps and the voltage transition characteristics between steps are fixed.
- the present invention provides a method of applying a step voltage to a pair of electrodes for driving a capacitive load.
- the method includes the steps of providing a current path from a power source to one of the electrodes via a current restricting resistor and a switching path of a semiconductor switching device in order, and transferring charge from the power source to the electrode intermittently by switching control of the semiconductor switching device, so as to increase charge quantity accumulated in a capacitor between the electrodes step by step.
- the voltage between the switching control terminal of the semiconductor switching device and the power source is maintained at a constant value in a period of closing the switching path, so as to make the step to step portion of the waveform of the charge voltage ramp-like shape.
- the present invention provides a method of adjusting charge by gradually decreasing wall charge of a dielectric that covers the pair of electrodes as a preparation process of addressing to control charge distribution of a screen for driving a gas discharge display device.
- the method includes the steps of providing a current path from a power source to one of the electrodes via a current restricting resistor and a switching path of a semiconductor switching device in order, and transferring charge from the power source to the electrode intermittently by switching control of the semiconductor switching device, so as to increase charge quantity accumulated in a capacitor between the electrodes step by step.
- the present invention provides a drive circuit for adjusting charge by gradually decreasing wall charge of a dielectric that covers the pair of electrodes as a preparation process of addressing to control charge distribution of a screen in a gas discharge display device.
- the drive circuit includes a first semiconductor switching device for opening and closing the current path between an output terminal connected to one of the electrodes and a bias potential line, a current restricting resistor inserted between the bias potential line and the semiconductor switching device, a second semiconductor switching device for opening and closing the current path between the output terminal and the ground potential line, and a controller for controlling the first and the second semiconductor switching devices.
- the drive circuit further includes a diode connected to the current restricting resistor in parallel and in the opposite direction, and a capacitor inserted between the terminal of the bias potential line side of the first semiconductor switching device and the ground potential line.
- the drive circuit further includes a variable voltage source for switching the potential of the switching control terminal of the semiconductor switching device.
- the controller includes a memory for memorizing pulse width modulation data used for the switching control.
- the present invention provides a display device includes a drive circuit mentioned above as the fourth aspect and an AC type plasma display panel driven by the drive circuit.
- FIG. 1 is a block diagram of a display device according to the present invention.
- FIG. 2 is a perspective view showing the inner structure of a plasma display panel according to the present invention.
- FIG. 3 shows an example of a drive sequence
- FIG. 4 shows a structure of the X common driver.
- FIG. 5 is a circuit diagram of the step voltage block.
- FIG. 6 shows waveforms of a first operational example of the step voltage block.
- FIG. 7 shows waveforms of a second operational example of the step voltage block.
- FIG. 8 shows waveforms of a third operational example of the step voltage block.
- FIG. 9 is a circuit diagram of a variation of the step voltage block.
- FIG. 10 shows operational waveforms of the variation of the step voltage block.
- FIG. 1 is a block diagram of a display device according to the present invention.
- the display device 100 includes an AC type plasma display panel 1 that is a slim color display device and a drive unit 50 for selectively lighting cells that are arranged in M columns and N rows of a screen.
- the display device 100 is used for a wall-hung TV set or a monitor of a computer system.
- the plasma display panel 1 has a three-electrode surface discharge structure in which pairs of first and second main electrodes X, Y are arranged in parallel for generating a sustain discharge (that is also referred to as a displaying discharge), and the main electrodes X, Y cross the address electrode A in each cell.
- the main electrodes X, Y extend in the row direction (the horizontal direction) of the screen, and the main electrode Y is used as a scanning electrode for selecting cells of a row in addressing.
- the address electrode A extends in the column direction (the vertical direction), and is used as a data electrode for selecting cells of a column.
- the area of the substrate surface in which the main electrodes and the address electrodes cross each other is a display area (i.e., a screen).
- the drive unit 50 includes a controller 51 , power source circuit 53 , X driver circuit 54 , Y driver circuit 56 , and address driver circuit 59 .
- the drive unit 50 is supplied with field data Df of each pixel representing the intensity level (the gradation level) of red, green and blue colors along with various synchronizing signals by external equipment such as a TV tuner or a computer.
- the field data Df are converted into subfield data Dsf for the gradation display after being stored in a frame memory 510 of the controller 51 .
- the subfield data Dsf is stored in the frame memory 510 and is transferred in series to the address driver circuit 59 along with the display.
- Each bit value of the subfield data Dsf is information indicating on and off of the cell in the subfield and, more strictly, information indicating whether or not an address discharge is necessary.
- the X driver circuit 54 includes plural X common drivers 55 , each of which corresponds to each block that is a dividend of the screen in the column direction. Each X common driver 55 controls the potential of the main electrodes X in a block.
- the Y driver circuit 56 includes a scan driver 57 and plural Y common drivers 58 .
- the scan driver 57 is potential control means for row selection in the addressing.
- the Y common driver 58 controls the potential of the main electrodes Y in a block.
- the address driver circuit 59 controls potential of total M of address electrodes (data electrodes) A in accordance with the subfield data Dsf. These driver circuits are supplied with a power by the power source circuit 53 via wiring conductors (not shown).
- FIG. 2 is a perspective view showing the inner structure of a plasma display panel according to the present invention.
- the plasma display panel 1 has a pair of main electrodes X, Y for each row, arranged on the inner surface of a glass substrate 11 of the front substrata structure 10 .
- a row is a group of cells in the horizontal direction of the screen.
- Each of the main electrodes X, Y includes a transparent conductive film 41 and a metal film (a bus conductor) 42 , which are covered with dielectric layer 17 having a thickness of approximately 30 microns of low melting point glass.
- the surface of the dielectric layer 17 is covered with a protection film 18 having a thickness of several thousands angstrom made of magnesia (MgO).
- the address electrodes A are arranged on the inner surface of the glass substrate 21 of the backside substrata structure 20 and are covered with a dielectric layer 24 having a thickness of approximately 10 microns.
- a partition 29 having a height of 150 microns and linear ribbon shape in a plan view is disposed at each portion between the address electrodes A.
- These partitions 29 define subpixels (unit areas of light emission) of the discharge space 30 in the row direction and define the gap size of the discharge space 30 .
- Three colors (red, green and blue) of fluorescent layers 28 R, 28 G and 28 B for color display cover the inner surface of the backside including the upper portion of the address electrode A and the side face of the partition 29 .
- the discharge space 30 is filled with a discharge gas containing neon as a main component and xenon, and the fluorescent layers 28 R, 28 G and 28 B are pumped locally to emit light by ultraviolet rays emitted by the xenon upon discharge.
- a pixel of the display includes three subpixels arranged in the row direction. A structure in each subpixel is the cell (display element). Since the arrangement pattern of the partition 29 is a stripe pattern, the portion of the discharge space 30 corresponding to each column is continuous in the column direction over all rows.
- FIG. 3 shows an example of a drive sequence.
- reference characters of the main electrodes X, Y are suffixed by the character (1, 2, . . . N) indicating the arrangement order of the corresponding row
- the reference characters of the address electrodes A are suffixed by the character (1-M) indicating the arrangement order of the corresponding column.
- sequential fields f (the suffix of the reference character indicates the display order) of the input image is divided into eight subframes sf 1 , sf 2 , sf 3 , sf 4 , sf 5 , sf 6 , sf 7 and sf 8 , for example.
- the fields f constituting the frame are replaced by a set of eight subframes sf 1 -sf 8 .
- each frame is divided into eight.
- the ratios of relative intensity in these subfields sf 1 -sf 8 are set to approximately 1:2:4:8:16:32:64:128 by weighting and determining the number of the sustaining discharge times of each subfield sf 1 -sf 8 .
- the intensity can be set to 256 steps for each color by the combination of on state and off state of each subfield.
- the number of colors that can be reproduced is 256 3 .
- the subfield period assigned to each subfield sf 1 -sf 8 includes a preparation period TR for making the charge distribution of the screen uniform, an addressing period TA for forming a charge distribution corresponding to display contents and a sustaining period (that is also referred to as a display period) TS for sustaining the lightened state so as to secure the intensity corresponding to the gradation level.
- the length of the preparation period TR and the addressing period TA is constant despite of the weight of the intensity, but the length of the sustaining period TS is larger for the larger weight of the intensity. Namely, the lengths of eight subfield periods corresponding to a field f are different from each other.
- a pulse Pra 1 and a pulse Pra 2 having a polarity opposite to the pulse Pra 1 are applied sequentially to all address electrodes A 1 -A M
- a pulse Prx 1 and a pulse Prx 2 having a polarity opposite to the pulse Prx 1 are applied sequentially to all of the main electrodes X 1 -X N
- a pulse Pry 1 and a pulse Pry 2 having a polarity opposite to the pulse Pry 1 are applied sequentially to all of the main electrodes Y 1 -Y N .
- the application of the pulse means biasing the electrode briefly to a potential different from the reference potential (the grand potential).
- the pulses Pra 1 , Pra 2 , Prx 1 , Prx 2 , Pry 1 and Pry 2 are step pulses having changing rate in which a micro discharge can be generated and are supplied by the drive circuit according to the present invention.
- the pulse Pra 1 and Prx 1 have the negative polarity and the pulse Pry 1 has a positive polarity.
- the pulse Pra 2 , Prx 2 and Pry 2 are applied so that the wall voltage can be adjusted to a value corresponding to the difference between the discharge starting voltage and the pulse amplitude.
- the pulses Pra 1 , Prx 1 and Pry 1 are applied so that an appropriate wall voltage having the same polarity can be generated to all cells despite on or off of the previous subfield.
- the wall charge that is necessary for sustaining is formed only in the cell to be lightened.
- All main electrodes X 1 -X N and all main electrodes Y 1 -Y N are biased to a predetermined potential Vx, while the scanning pulse Py is applied to a main electrode Y that corresponds to the selected row for each row selection period (a scanning period of a row).
- an address pulse Pa is applied only to the address electrode A corresponding to the selected cell in which the address discharge is to be generated.
- the potential of the address electrode A 1 -A M is controlled to zero or Va in accordance with the subfield data Dsf of M columns of the selected row.
- a discharge is generated between the main electrode Y and the address electrode A, which causes the surface discharge between the main electrodes. This set of sequential discharges is the address discharge.
- a sustaining pulse Ps having a predetermined polarity (the positive polarity in the illustrated example) is applied to all main electrodes Y 1 -Y N first.
- the main electrode X 1 -X N and the main electrode Y 1 -Y N are supplied with the sustaining pulse Ps alternately.
- the application of the sustaining pulse Ps causes the surface discharge in the cell having a predetermined remaining wall charge.
- the polarity of the wall voltage between the electrodes changes at every generation of the surface discharge.
- the address electrodes A 1 -A M are biased in the same polarity as the sustaining pulse Ps.
- the amplitude, the polarity and the timing of the drive waveform can be changed variously.
- one of the electrodes can be supplied with a step pulse.
- FIG. 4 shows a structure of the X common driver.
- the X common driver 55 includes a step voltage block 61 that applies a positive step pulse, a step voltage block 61 B that applies a negative step pulse, a bias circuit 60 B that pulls up the main electrode X to the potential Vx and a sustaining block 60 that applies a sustaining pulse.
- the sustaining block 60 has a power recycling circuit that saves a power necessary for charging and discharging the capacitance between the main electrodes (not shown).
- FIG. 5 is a circuit diagram of the step voltage block.
- the circuit configuration of the step voltage block 61 B is the same as the step voltage block 61 except for the difference of the polarity.
- the step voltage block 61 includes a p-channel FET 62 that opens and close the current path between the output terminal px connected to the main electrode X and a power source of the potential V 1 (bias potential line) 81 , a current restricting resistor 66 inserted between the power source 81 and the source of the FET 62 , an n-channel FET 63 that opens and closes the current path between the output terminal px and the ground potential line, gate drives 69 , 70 that control the FETs 62 , 63 , a coupling capacitor 71 , a bias resistor 68 that connects the power source 81 to the gate of the FET 62 , a diode 67 connected to the bias resistor 68 in parallel, and a gate voltage control circuit 75 that changes an output current.
- the gate drivers 69 , 70 and gate voltage control circuit 75 are supplied with a control signal (waveform data) by the controller 51 .
- Each of the FETs 62 , 63 can be made of plural elements connected in parallel for securing a current capacity. Since the output terminal px is connected to the above-mentioned sustaining block 60 , backflow preventing diodes 64 , 65 are inserted between the output terminal px and the FETs 62 and 63 , respectively.
- a diode 72 is connected in parallel with the current restricting resistor 66 and in the opposite direction to the same, a capacitor 73 is inserted between the source of the FET 62 and the ground potential line, and a capacitor 74 is inserted between the drain of the FET 62 and the ground potential line.
- FIG. 6 shows waveforms of a first operational example of the step voltage block.
- the basic operation will be explained with reference to FIG. 6 and FIG. 5 .
- the gate voltage control circuit 75 is in through (i.e., conducting) state so that the gate driver 69 is supplied with a potential Ve by the power source 82 and the output terminal px is connected to a capacitive load Cxy via the main electrode X.
- the capacitive load Cxy is a sum of the individual capacitances of all cells to be driven.
- the gate driver 69 outputs a pulse having an amplitude Ve obtained by shaping the control signal S 1 .
- the gate of the FET 62 is supplied with a control pulse having an amplitude. Ve based on the potential V 1 , so that the gate potential becomes Ve-V 1 . Since the amplitude Ve is set to a value larger than a threshold Vth between the gate and source of the FET 62 (Ve>Vth), the FET 62 is in a turned on state.
- the output (sustaining pulse) of the sustaining block 60 connected to the output terminal px along with the step voltage block 61 is a rectangular pulse having a rapid rising edge. If an impulse noise at the rising edge is added to the FET 62 , a malfunction or a break down of the element can occur since the impulse voltage may be added between the source and the gate of the FET 62 whose power source impedance (R 1 ) of source side is high.
- the diode 72 is provided for bypassing the impulse current that entered the source of the FET 62 to the power source 81 . Thus, the malfunction or the break down can be prevented.
- the capacitor 72 has a function of absorbing the impulse current that entered the source of the FET 62 and reduces the same.
- the capacitor 74 has a role of adding charge to the capacitive load Cxy to prevent the drop of the output voltage when a micro discharge that is a relatively strong discharge occurs between the main electrodes.
- FIG. 7 shows waveforms of a second operational example of the step voltage block, which indicates the operation of applying the step voltage according to the present invention.
- the controller 51 has a waveform memory that memorizes pulse width modulation data for applying the step voltage.
- the pulse width modulation data are inputted to the gate driver 69 as a control signal SI.
- the FET 62 is not always turned on in the application period, but the output (control voltage) Vsw of the gate driver 69 is controlled binary so as to repeat ON and OFF of the FET 62 , and the ON period and the OFF period are altered.
- the current Ic is maintained at a constant value as shown in FIG. 6, so the waveform of the output voltage Vrx becomes a ramp-like shape.
- the output voltage Vrx is maintained by the charge sustaining function of the capacitive load Cxy at the value when the previous ON period finishes.
- the waveform of the output voltage becomes step-like shape.
- the height and the width of the step can be controlled by setting the ON/OFF timing. According to the waveform shown in FIG. 7, the micro discharge can be generated continuously.
- FIG. 8 shows waveforms of a third operational example of the step voltage block.
- a gate voltage control circuit 75 is used for controlling the output (control voltage) Vsw of the gate driver 69 in multilevel.
- the output current Ic can be changed by setting the gate potential of the FET 62 , so that the gradient of the ramp waveform portion of the output voltage Vrx can be optimized for every step of the step waveform. If the control voltage Vsw is increased, the output current Ic is increased and the gradient becomes large. On the contrary, if the control voltage Vsw is reduced, the gradient becomes small.
- the voltage waveform can be set in detail by combining the setting of the control voltage Vsw and the setting of the above-mentioned ON and OFF timings.
- FIG. 9 is a circuit diagram of a variation of the step voltage block
- FIG. 10 shows operational waveforms of the variation of the step voltage block.
- the digital-to-analog converter 91 of the step voltage block 61 โฒ shown in FIG. 9 is a circuit specialized in the step waveform, which includes plural voltage regulators (e.g., variable resistors) 92 and plural analog switches 93 for decreasing the reference voltage Vref of the power source 85 .
- the step waveform can be obtained by combining an open state and a close state of the analog switch 93 by the signal Sv.
- the output level of the digital-to-analog converter is approximately five volts.
- a voltage amplifier circuit 95 is necessary for amplifying the output of the digital-to-analog converter up to approximately 200-300 volts.
- This voltage amplifier circuit 95 is made of many power devices, so it is inevitable that the step voltage block 61 โฒโฒ becomes expensive.
- the setting of the step height in the application of the step voltage can be performed by a simple circuit configuration according to the present invention.
- micro discharge having a uniform intensity can be generated periodically when applying the present invention to a gas discharge device.
- flexibility of setting the waveform is enhanced in driving the gas discharge display device, so as to optimize the drive.
- the voltage transition characteristics between the steps is set for each step, so that the waveform can have various shapes.
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- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Transforming Electric Information Into Light Information (AREA)
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Abstract
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Applications Claiming Priority (2)
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JP11-184610 | 1999-06-30 | ||
JP11184610A JP2001013912A (en) | 1999-06-30 | 1999-06-30 | Method and circuit for driving capacitate load |
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US09/559,633 Expired - Fee Related US6822644B1 (en) | 1999-06-30 | 2000-04-28 | Method and circuit for driving capacitive load |
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EP (1) | EP1065647A3 (en) |
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US20030098822A1 (en) * | 2001-11-24 | 2003-05-29 | Park Chung Hoo | Apparatus and method for driving plasma display panel |
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US8144144B2 (en) * | 2002-10-21 | 2012-03-27 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
US20050030260A1 (en) * | 2003-06-23 | 2005-02-10 | Jin-Sung Kim | Driving device and method of plasma display panel |
US7737921B2 (en) * | 2003-06-23 | 2010-06-15 | Samsung Sdi Co., Ltd. | Driving device and method of plasma display panel by floating a panel electrode |
US20050040770A1 (en) * | 2003-08-05 | 2005-02-24 | Kang Kyoung-Ho | Plasma display panel and driving method thereof |
US7355564B2 (en) * | 2003-08-05 | 2008-04-08 | Samsung Sdi Co., Ltd. | Plasma display panel and driving method thereof |
US20050083259A1 (en) * | 2003-10-16 | 2005-04-21 | Jin-Sung Kim | Driving device and method of plasma display panel |
US20060164336A1 (en) * | 2005-01-25 | 2006-07-27 | Jin-Ho Yang | Plasma display, driving device and method of operating the same |
Also Published As
Publication number | Publication date |
---|---|
EP1065647A2 (en) | 2001-01-03 |
KR20010006906A (en) | 2001-01-26 |
EP1065647A3 (en) | 2005-05-25 |
JP2001013912A (en) | 2001-01-19 |
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