US6455438B1 - Fabrication method for a semiconductor device - Google Patents
Fabrication method for a semiconductor device Download PDFInfo
- Publication number
- US6455438B1 US6455438B1 US09/662,855 US66285500A US6455438B1 US 6455438 B1 US6455438 B1 US 6455438B1 US 66285500 A US66285500 A US 66285500A US 6455438 B1 US6455438 B1 US 6455438B1
- Authority
- US
- United States
- Prior art keywords
- resist film
- opening
- openings
- film
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
Links
- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 238000000137 annealing Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 description 20
- 239000000463 material Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005549 size reduction Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Definitions
- the present invention relates to a fabrication method for a semiconductor device, and in particular to a technique for forming an opening in a resist film and then annealing the resist film to make the diameter of the formed opening smaller.
- an opening such as a contact hole is formed in an insulation film or the like formed on a semiconductor substrate in the following manner.
- the insulation film such as a silicon oxide film is formed on the entire surface of the semiconductor substrate.
- a resist film is formed on the insulation film and is then exposed and developed, so as to form the opening in the resist film.
- the resist film having the opening thus formed is then subjected to an annealing process, thus making the diameter of the opening smaller.
- the insulation film is etched using the resist film as a mask.
- the diameter of the opening formed in the resist film is made smaller by annealing the resist film as described above, the amount of reduction in the diameter varies depending on the position of the opening. This makes it hard to form openings having a uniform shape for a film that is to be etched.
- a fabrication method for a semiconductor method includes: forming a film to be etched on a semiconductor substrate; forming a resist film on the film to be etched; exposing the resist film to form a first pattern group and a second pattern group therein, the first pattern group including a plurality of first patterns having a first size, the second pattern group arranged outside of the first pattern group, including a plurality of second patterns larger than the first patterns; developing the resist film to form in the resist film, openings corresponding to the first patterns and the second patterns; and annealing the resist film to make the openings smaller.
- the first pattern group is formed by exposure using a first mask
- the second pattern group is formed by exposure using a second mask different from the first mask
- the first patterns are arranged at a substantially constant interval.
- the amount of exposure for forming the second pattern group is larger than that for forming the first pattern group.
- an opening of the first mask has a smaller diameter than that of an opening of the second mask.
- the diameter of each of the openings corresponding to the first patterns after the annealing is substantially the same as the diameter of each of the openings corresponding to the second patterns after the annealing.
- a fabrication method for a semiconductor device includes: forming a film to be etched on a semiconductor substrate; forming a first resist film on the film to be etched; forming a first opening and a second opening in the resist film, the second opening being located away from the first opening by a first distance; annealing the first resist film to make the first and second openings smaller; forming in the film to be etched a third opening and a fourth opening respectively corresponding to the first opening and the second opening that have been made smaller; removing the first resist film after the third opening and the fourth opening are formed in the film to be etched; forming a second resist film on the film to be etched; forming a fifth opening in a region of the second resist film corresponding to a position between the third and fourth openings; annealing the second resist film to make the fifth opening smaller; and forming in the film to be etched a sixth opening corresponding to the fifth opening.
- the formation of the first and second openings in the first resist film and the formation of the fifth opening in the second resist film are performed by exposure and development using a single mask.
- the distance between the first opening and the second opening is twice the diameter of the first opening or more.
- a fabrication method for a semiconductor device includes: forming a film to be etched on a semiconductor substrate; forming a first resist film on the film to be etched; forming a plurality of first openings in the first resist film; annealing the first resist film and then removing a part of the film to be etched that is exposed through the first openings; removing the first resist film and then forming a second resist film on the film to be etched including an area in which the film to be etched has been removed; forming a plurality of second openings in regions of the second film respectively corresponding to regions between adjacent two of the first openings; and annealing the second resist film and then removing a part of the film to be etched that is exposed through the second openings.
- FIGS. 1A, 1 B and 1 C are plan views illustrating fabrication processes of a fabrication method according to a first embodiment of the present invention
- FIG. 2A is a plan view used for explanation of a second embodiment of the present invention, while FIG. 2B is a cross-sectional view taken along a line A-A′ in FIG. 2A;
- FIG. 3 is a plan view illustrating the second embodiment of the present invention.
- FIGS. 4A, 4 B and 4 C are cross-sectional views showing processes of a fabrication method according to the second embodiment of the present invention.
- FIGS. 5A, 5 B and 5 C are cross-sectional views showing processes of the fabrication method according to the second embodiment of the present invention.
- FIG. 6 is a plan view showing a modified example of the second embodiment of the present invention.
- FIGS. 1A, 1 B and 1 C The first embodiment of the present invention is described with reference to FIGS. 1A, 1 B and 1 C.
- a resist film I is exposed so as to form a first pattern group 3 including a plurality of first patterns 2 , as shown in FIG. 1 A.
- the resist film 1 is formed with a thickness of about 0.65 ⁇ m. All of the first patterns 2 that are arranged in a matrix have the same shape of a square with sides of 0.26 ⁇ m, for example.
- the resist film 1 is formed on a film to be etched (not shown) that is formed on a semiconductor substrate (not shown).
- an insulation film such as a silicon oxide film deposited by a CVD method, is formed as the film to be etched.
- a second pattern group 4 is formed outside of the first pattern group 3 that includes the first patterns 2 arranged in a matrix, by exposing the resist film 1 , as shown in FIG. 1 B.
- the second pattern group 4 includes second patterns 5 each having a shape obtained by enlarging the first pattern 2 in one direction and third patterns 6 each having a shape obtained by enlarging the first pattern 2 in two directions.
- the shape of the second pattern 5 is obtained by enlarging that of the first pattern 2 by 0.02 ⁇ m in the direction opposite to the side on which the first patterns 2 are formed with respect to the position of the second pattern 5 , thus having a size of 0.26 ⁇ m ⁇ 0.28 ⁇ m.
- the shape of the third pattern 6 is obtained by enlarging that of the first pattern 2 by 0.02 ⁇ m in the directions opposite to the side of the first pattern 2 with respect to the position of the second pattern 5 , thus having a size of 0.28 ⁇ m ⁇ 0.28 ⁇ m.
- the second pattern group 4 is formed by exposure, using a different mask from that used for the first pattern group 3 .
- the resist film 1 having the openings formed therein is then subjected to an annealing process for one minute at a temperature of 135° C. As a result, reduced-size openings 7 are obtained, as shown in FIG. 1 C.
- the resist material flows into the openings formed in the resist film 1 so that the diameter of each opening is reduced.
- the flow of the resist material into the openings is limited on the side on which the openings corresponding to the first patterns 2 are formed.
- the side opposite to the first pattern group 3 there is a sufficient amount of the resist material because no opening is formed on that side.
- the amount of size reduction is greater on the side opposite to the first patterns 2 than that on the side on which the first patterns 2 are formed.
- the reduced-size openings 7 can have substantially the same shape as that of the openings 8 after the size reduction.
- the diameter of each opening after size reduction is approximately 0.1 ⁇ m.
- the first pattern group 3 and the second pattern group 4 are formed in different shapes by exposure using different masks.
- this exposure it is typical to use for the first pattern group 3 a mask having a shape different from that of the mask for the second pattern group 4 .
- the amount of exposure may be varied between the first pattern group 3 and the second pattern group 4 , while using a mask having the same size of mask patterns, both for the first pattern group 3 and the second pattern group 4 .
- the amount of exposure can be adjusted in the case where it is difficult to form openings in the mask corresponding to the second patterns 5 , so as to have a sufficient size.
- the first pattern group 3 and the second pattern group 4 are formed using separate masks.
- the first pattern group 3 and the second pattern group 4 can be formed using the single mask. In this case, a single exposure process forms all of the patterns.
- FIG. 2A shows a state where, after the resist film is exposed and developed to form predetermined openings, the openings are made smaller by annealing the resist film.
- FIG. 2B is a cross-sectional view taken along a line A-A′ in FIG. 2 A.
- an insulation film 22 such as a silicon oxide film deposited by a CVD method, is formed on a semiconductor substrate 21 .
- resist material is applied on the insulation film 22 by, for example, spin-coating to about 0.65 ⁇ m thickness, so as to form a resist film 24 .
- the resist film 24 is exposed and developed by a known photolithography method or the like, thus openings 25 are formed in the resist film 24 .
- the resist film 24 is subjected to an annealing process. This process softens the resist film 24 , so that a resist film 26 having a shape expanded into the openings 25 is formed. That is, the shape of each opening 25 is made smaller than that before the annealing process.
- the resist material expands, and the height thereof becomes lower due to the annealing process.
- the shape of the resist film 24 shown with a broken line changes into the shape of the resist film 26 shown with solid line.
- the resist film 26 has a shape in which the middle portion expands more than the upper and lower portions, as shown in FIG. 2 B. Therefore, in a case where the insulation film 22 is etched by a plasma method or the like, it is likely that openings to be formed in the insulation film 22 are connected to each other. This is significant when the distance between adjacent openings before the annealing process is twice the size of the opening before the annealing process or less.
- FIGS. 3, 4 A- 4 C and 5 A- 5 C illustrate a fabrication method of a semiconductor device according to the second embodiment of the present invention, that can suppress deformation of the resist film caused by the annealing process shown in FIGS. 2A and 2B.
- the fabrication method is described in detail below, referring to FIGS. 3, 4 A- 4 C and 5 A- 5 C.
- the second embodiment has a feature where the openings are formed by repeating formation processes.
- the openings are formed by repeating the formation processes twice.
- FIG. 3 shows positions of openings to be formed in a resist film 31 .
- the openings 32 shown by a solid line are formed by a first opening-formation processes, while the openings 33 shown by a broken line are formed by a second opening-formation processes.
- FIGS. 4A-4C and 5 A- 5 C are cross-sectional views taken along a line A-A′ in FIG. 3 .
- FIGS. 4A, 4 B and 4 C show the first opening-formation processes; and
- FIGS. 5A, 5 B and 5 C show the second opening-formation processes.
- an insulation film 42 is formed on a semiconductor substrate 41 .
- the insulation film 42 is a silicon oxide film deposited by a CVD method, for example.
- a resist film 43 on which openings 44 are formed by known exposure and development techniques.
- the openings 44 correspond to the openings 32 shown by the solid line in FIG. 3 .
- a mask corresponding to the openings 44 are used.
- the resist film 43 having the openings 44 formed therein is then subjected to the annealing process for one minute, at a temperature of 135° C. As a result, the resist material expands into the openings 44 , and thus reduced-size openings 45 are formed, as shown in FIG. 4 B.
- the aforementioned annealing process makes the size of the openings smaller, the amount of deformation of the resist film 43 can be suppressed. This is because the arrangement of the openings 44 are not concentrated, that is, the openings 44 are arranged in a staggered manner in which every other opening appears aligned.
- the insulation film 42 is etched using the resist film 43 as a mask, as shown in FIG. 4 C. At this time, the openings 45 in the resist film 43 have been made smaller by the annealing process of the resist film 43 .
- the insulation film 42 is etched by, for example, a plasma CVD method.
- the resist material for the resist film 51 is applied within the openings that have been formed in the insulation film 42 using the resist film 43 .
- the resist film 51 having the openings 52 formed therein is then subjected to the annealing process for one minute, at a temperature of 135° C. This makes the resist material expand into the openings 52 , and thus reduced-size openings 53 are obtained, as shown in FIG. 5 B.
- the openings are made smaller by the annealing process, the amount of deformation of the resist film 51 can be suppressed because the arrangement of the openings 53 is not concentrated.
- the insulation film 42 is etched using the resist film 51 as a mask.
- the openings 53 in the resist film 51 have already been made smaller by the annealing process of the resist film 51 .
- the insulation film 42 is etched using a plasma CVD method, for example.
- the ratio of the size of the opening after development to the distance between adjacent openings after development is 12
- the amount of deformation of the resist material caused by the annealing process is large.
- the deformation of the resist film caused by the annealing process can be suppressed by forming the consecutive openings by the first and second opening-formation processes. In this way, every other opening is formed in each opening-formation process, as described in the present embodiment.
- openings 62 shown by solid line, formed by the first exposure and development and other openings 63 , shown by broken line, formed by the second exposure and development may be arranged in straight dines so that the lines of the openings 62 and the lines of the openings 63 are alternately arranged, as shown in FIG. 6 .
- the processes of the fabrication method are the same as those in the fabrication method shown in FIGS. 4 A- 4 AC and 5 A- 5 C, and therefore the cross-sectional views in the respective processes are the same as the corresponding ones shown in FIGS. 4A-4C and 5 A- 5 C.
- the detailed description of the respective steps is omitted here.
- the exposure for forming the respective openings can be performed by using a single mask.
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000068776A JP3581628B2 (en) | 2000-03-13 | 2000-03-13 | Method for manufacturing semiconductor device |
JP2000-068776 | 2000-03-13 |
Publications (1)
Publication Number | Publication Date |
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US6455438B1 true US6455438B1 (en) | 2002-09-24 |
Family
ID=18587781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/662,855 Expired - Lifetime US6455438B1 (en) | 2000-03-13 | 2000-09-15 | Fabrication method for a semiconductor device |
Country Status (2)
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US (1) | US6455438B1 (en) |
JP (1) | JP3581628B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090316125A1 (en) * | 2008-06-24 | 2009-12-24 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
US20100129736A1 (en) * | 2008-06-17 | 2010-05-27 | Kasprowicz Bryan S | Photomask Having A Reduced Field Size And Method Of Using The Same |
US20110012237A1 (en) * | 2008-01-16 | 2011-01-20 | Christophe Pierrat | Spacer double patterning for lithography operations |
US20110086511A1 (en) * | 2009-06-17 | 2011-04-14 | Kasprowicz Bryan S | Photomask having a reduced field size and method of using the same |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20040007117A (en) * | 2002-07-16 | 2004-01-24 | 주식회사 하이닉스반도체 | Method for forming contact hole pattern of semiconductor device |
SG118239A1 (en) * | 2003-04-24 | 2006-01-27 | Asml Netherlands Bv | Lithographic processing method and device manufactured thereby |
JP4480424B2 (en) * | 2004-03-08 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | Pattern formation method |
US7465525B2 (en) | 2005-05-10 | 2008-12-16 | Lam Research Corporation | Reticle alignment and overlay for multiple reticle process |
JP5918637B2 (en) * | 2012-06-20 | 2016-05-18 | ラピスセミコンダクタ株式会社 | Hot plate temperature correction method, hot plate drive device, and substrate heating device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5776836A (en) * | 1996-02-29 | 1998-07-07 | Micron Technology, Inc. | Self aligned method to define features smaller than the resolution limit of a photolithography system |
-
2000
- 2000-03-13 JP JP2000068776A patent/JP3581628B2/en not_active Expired - Fee Related
- 2000-09-15 US US09/662,855 patent/US6455438B1/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5776836A (en) * | 1996-02-29 | 1998-07-07 | Micron Technology, Inc. | Self aligned method to define features smaller than the resolution limit of a photolithography system |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101910940B (en) * | 2008-01-16 | 2013-06-05 | 益华公司 | Spacer double patterning for lithography operations |
US8278156B2 (en) | 2008-01-16 | 2012-10-02 | Cadence Design Systems, Inc. | Spacer double patterning for lithography operations |
US20110012237A1 (en) * | 2008-01-16 | 2011-01-20 | Christophe Pierrat | Spacer double patterning for lithography operations |
US20110018146A1 (en) * | 2008-01-16 | 2011-01-27 | Christophe Pierrat | Spacer double patterning for lithography operations |
US7927928B2 (en) * | 2008-01-16 | 2011-04-19 | Cadence Design Systems, Inc. | Spacer double patterning for lithography operations |
TWI452607B (en) * | 2008-01-16 | 2014-09-11 | Cadence Design Systems Inc | Spacer double patterning for lithography operations |
US9005848B2 (en) | 2008-06-17 | 2015-04-14 | Photronics, Inc. | Photomask having a reduced field size and method of using the same |
US20100129736A1 (en) * | 2008-06-17 | 2010-05-27 | Kasprowicz Bryan S | Photomask Having A Reduced Field Size And Method Of Using The Same |
US8416394B2 (en) | 2008-06-24 | 2013-04-09 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
US20090316125A1 (en) * | 2008-06-24 | 2009-12-24 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
US8786828B2 (en) | 2008-06-24 | 2014-07-22 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
US7982856B2 (en) | 2008-06-24 | 2011-07-19 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
US9005849B2 (en) | 2009-06-17 | 2015-04-14 | Photronics, Inc. | Photomask having a reduced field size and method of using the same |
US20110086511A1 (en) * | 2009-06-17 | 2011-04-14 | Kasprowicz Bryan S | Photomask having a reduced field size and method of using the same |
Also Published As
Publication number | Publication date |
---|---|
JP3581628B2 (en) | 2004-10-27 |
JP2001257155A (en) | 2001-09-21 |
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