US6380634B1 - Conductor wires and semiconductor device using them - Google Patents
Conductor wires and semiconductor device using them Download PDFInfo
- Publication number
- US6380634B1 US6380634B1 US09/361,502 US36150299A US6380634B1 US 6380634 B1 US6380634 B1 US 6380634B1 US 36150299 A US36150299 A US 36150299A US 6380634 B1 US6380634 B1 US 6380634B1
- Authority
- US
- United States
- Prior art keywords
- semiconductor chip
- wire
- wires
- conductor
- bending point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 107
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000005452 bending Methods 0.000 claims abstract description 60
- 230000000630 rising effect Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000005022 packaging material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4801—Structure
- H01L2224/48011—Length
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85203—Thermocompression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- This invention pertains to a type of conductor wires for making electric connection of a semiconductor chip to external conductors.
- this invention provides an excellent type of conductor wires that can reduce the thickness of the package and can avoid problems of short-circuits among the wires.
- Wire bonding is the most common method for connecting a semiconductor chip to external conductors, such as a pattern or lead frame on an insulating substrate.
- the semiconductor chip is connected to the external conductors by fine wires of gold (Au) or aluminum (Al) fed from a tool known as a capillary tool.
- Au gold
- Al aluminum
- the wires fed from the capillary tool have one end bonded to the electrode pads of a semiconductor chip, followed by looping, that is, forming a loop, and then have the other end bonded to the external conductors.
- the aforementioned wire looping plays an important role in absorbing the influence of contraction of the wires under pressure and heat during the molding operation.
- the amount of rise of the wire loops from the surface of the semiconductor chip directly affects the thickness of the semiconductor device. It is necessary to have sufficiently thick packaging material on the surface of the semiconductor chip to completely cover and shield the aforementioned wires.
- the miniaturization trend of electronic and communications equipment there is a requirement for even smaller and thinner semiconductor devices. Consequently, it is important to further reduce the thickness of the packaging material on tile semiconductor chip.
- a bending point usually called the “bend” (point P in the figure) is formed midway along wire W, as shown in FIG. 7, so as to increase the resistance to deformation.
- a bending point usually called the “bend” (point P in the figure) is formed midway along wire W, as shown in FIG. 7, so as to increase the resistance to deformation.
- the heights of adjacent wire loops are changed alternately in bonding. Even when adjacent wires move near each other in the plane due to the movement of wires during manufacturing, it is still possible to ensure a sufficient gap between the wires in the height direction, and it is thus possible to minimize the danger of short-circuits.
- the thickness of the packaging material on the semiconductor chip has to be increased. This is a disadvantage.
- the purpose of this invention is to provide a type of conductor wires appropriate for realizing a thin semiconductor device.
- Another purpose of this invention is to provide a type of conductor wires that can minimize the problem of short-circuiting between wires while the thickness of the semiconductor device is reduced.
- This invention pertains to a type of conductor wires for electrically connecting the semiconductor chip to external conductors.
- Each of the conductor wires in this invention has a first end portion bonded to the electrode pad of the semiconductor chip, a second end portion bonded to the external conductor, and a bending point which is positioned between the aforementioned first and second end portions and is bent almost in the direction opposite to the direction that the conductor wire rises at the aforementioned first end portion.
- the aforementioned bending point is usually called the “bend.” It refers to the site on the wire intentionally bent during manufacturing. As the bending point is bent almost in the direction opposite to the rising direction of the conductor wire, it is possible to reduce the amount of rise of the conductor wire from the principal surface of the semiconductor chip, so that the semiconductor device can be made even thinner.
- the aforementioned bending point be positioned on the side opposite to the rising side of the conductor wire with respect to the position of a straight line connecting the aforementioned first end portion and the aforementioned second end portion, and that the bending point position be shifted toward the aforementioned first end portion.
- plural said bending points may be formed on each conductor wire.
- This invention also provides a type of semiconductor device having the aforementioned conductor wires.
- the semiconductor device of this invention has plural first conductor wires and plural second conductor wires set close among the aforementioned first conductor wires.
- Each said first conductor wire has a bending point bent in the rising direction of the conductor wire.
- Each said second conductor wire has a bending point bent in the direction almost opposite to the rising direction. In this way, a sufficient gap is formed between the conductor wires having bending points in different directions, and the possibility of short-circuits is reduced.
- FIG. 1 is an enlarged view of the main portion of the semiconductor device using the conductor wires of this invention.
- FIG. 2 is a diagram illustrating an example in which this invention is adopted in a semiconductor device using a zigzag-shaped bonding configuration.
- FIG. 3 is a diagram illustrating the bonding procedure for the conductor wires of this invention.
- FIG. 4 is a diagram illustrating another embodiment of this invention having plural bending points.
- FIG. 5 is a diagram comparing the conventional structure with conductor wires in an embodiment of this invention.
- FIG. 6 is a plane view illustrating the shape of the zigzag bonding configuration.
- FIG. 7 is a diagram illustrating the shape of conventional conductor wires.
- FIG. 8 is a diagram illustrating the shape of conventional conductor wires in a zigzag-shaped bonding confirmation.
- 1 is a semiconductor chip
- 2 is an electrode pad
- 3 a die pad
- 4 an inner lead
- 5 a conductive wire 5 a and b end portions
- A the bending point.
- FIG. 1 is a diagram illustrating the enlarged main portion of the semiconductor device using the conductor wires of this invention.
- the semiconductor device shown in FIG. 1 is TQFP (Thin Quad Flat Package).
- TQFP Thin Quad Flat Package
- semiconductor chip ( 1 ) is attached on die pad ( 3 ), and inner leads ( 4 ) of the lead frame are set around semiconductor chip ( 1 ) at a distance apart from it.
- Electrode pads ( 2 ) set around the principal surface of semiconductor chip ( 1 ) and inner leads ( 4 ) of the lead frame are electrically connected to each other by conductor wires ( 5 ).
- conductor wire ( 5 ) has downward bending point A 1 . Bending point A 1 is shifted in position from the midpoint of the total length of conductor wire ( 5 ) to end portion ( 5 a ) towards electrode pad ( 2 ). Conductor wire ( 5 ) also has bending point A 2 bent a little upward and shifted toward end portion (5 b ). Conductor wire ( 5 ), after rising a little from end portion ( 5 a ), extends steeply downward to reach bending point A 1 . At bending point A 1 , conductor wire ( 5 ) is bent through a large angle. From bending point A 2 , the conductor wire is gently bent downward to reach end portion ( 5 b ) at inner lead ( 4 ).
- FIG. 1 shows straight line L that connects two end portions ( 5 a ) and ( 5 b ) of conductor wire ( 5 ).
- Bending point A 1 is positioned below said straight line L. If the height position of bending point A 1 with respect to straight line L is lowered, the height from the surface of the semiconductor chip to the maximum rise of the conductor wire (position of point P on the wire) becomes smaller. However, if the position of bending point A 1 is too low, the stress applied to wire's end portion ( 5 a ) becomes larger and may lead to a poor joint at electrode pad ( 2 ). In consideration of this problem, it is necessary to adjust the position of bending point A 1 . As the height position of bending point A 1 can be controlled to a certain degree by its opening angle ⁇ , one may adjust said opening angle ⁇ when conductor wires ( 5 ) are installed.
- FIG. 2 is a diagram illustrating another embodiment of this invention.
- semiconductor chip ( 1 ) has electrode pads ( 2 a ) and ( 2 b ) set in the same zigzag configuration as shown in FIG. 6 .
- two types of conductor wires. ( 5 ) and ( 6 ), with respect to their shape, are shown.
- Conductor wires ( 5 ) have the same shape as shown in FIG. 1, with end portion ( 5 a ) bonded to the row of electrode pads ( 2 a ) on the outer side.
- Other conductor wires ( 6 ) are conventional lead-out wires, with end portion ( 6 a ) bonded to electrode pad ( 2 b ) on the inner side.
- each conductor wire ( 6 ) after leading out vertically from electrode pad ( 2 b ), it is bent almost at a right angle so that it extends horizontally. Then, at the middle portion it deviates towards inner lead ( 4 ), that is, at bending point B, it is bent slightly, and it then reaches inner lead ( 4 ).
- Conductor wires ( 5 ) and ( 6 ) are led out from zigzag-configured electrode pads ( 2 a ) and ( 2 b ) alternately. Consequently, no conductor wires of the same shape are set adjacent to each other. In this case, bending point A 1 of conductor wire ( 5 ) faces downward, while bending point B of conductor wire ( 6 ) faces upward. Consequently, in middle region M between these two conductor wires, the conductor wires are separated sufficiently from each other in the height direction. For middle region M between the conductor wires, deformation during injection of the molding resin is large, and positional error at the time of wire bonding also appears to be maximum here.
- the possibility of contact between wires in said middle region M can be minimized.
- the two conductor wires are set relatively near each other in the height direction in the regions near the two end portions. However, in the regions near the wire end portions, deformation during injection of the molding resin and error in position during wire bonding are small. Consequently, there is little possibility for the two conductor wires to make contact with each other.
- said conductor wire ( 6 ) has an upward bending point B. However, even when there is no such bending point, for the combination of a wire without such a bending point and said conductor wire ( 5 ) having the aforementioned downward bending point, sufficient clearance can still be ensured between the two wires.
- FIG. 3 is a diagram illustrating the bonding procedure for conductor wires ( 5 ) in FIGS. 1 and 2.
- this procedure is a basic bonding operation not different from the conventional method, the movement path of the capillary tool nevertheless has certain characteristic features in this case, in order to realize the special shape of said conductor wires ( 5 ).
- a ball is formed on the tip of each wire.
- capillary tool ( 10 ) By means of ultrasonic waves and hot pressure adhesion from capillary tool ( 10 ), the tip of the wire is bonded to electrode pad ( 2 ) of the semiconductor chip.
- capillary tool ( 10 ) is further pulled [straight] upward (step (A)).
- step (B) pull-up of capillary tool ( 10 ) is stopped.
- step (C) After the capillary tool is moved sideway (step (B)), it is further pulled upward (step (C)).
- capillary tool ( 10 ) is moved to the left side (step (D)), and a sufficient bend is applied to bending point A 1 . Then, the capillary tool is pulled upward (step (E)). Finally, while the wire is pulled out, the capillary tool is driven to move to perform bonding on inner lead ( 4 ) (step (F)).
- FIG. 4 is a diagram illustrating another embodiment of the conductor wires in this invention.
- conductor wire ( 7 ) has plural downward bending points C.
- wire ( 7 ) has downward bending points C 1 -C 3 formed at three sites so that it is divided into four portions. Formation of plural downward bending points on each conductor wire has the advantage that this can increase the resistance of the conductor wire to deformation, and that it enables setting of the conductor wire such that its entire length is at an average low height. If this embodiment is adopted for one of the two types of wires set alternately as shown in FIG. 2, it is possible to avoid the problem of short-circuits between adjacent wires.
- samples of conductor wires of the conventional structure and in an embodiment of this invention were prepared, and they were used to compare the height position with respect to the semiconductor chip plane.
- Both wires were prepared from A 1 wires having length of 4 mm and diameter of 25 ⁇ m. Measurement of all of the samples was performed to derive height D of the wire at bending point A with respect to the height of the principal surface of the semiconductor chip, taken as a reference. The results are listed in the following table.
- the height of the wire at bending point A has an average value as small as 186.4 ⁇ m.
- This invention may be adopted on any type of semiconductor device using conductor wires to electrically connect the semiconductor chip to external conductors.
- the external conductors for bonding with the conductor wires may be inner leads of a lead frame, a conductor pattern on an insulating substrate, or other conductor parts.
- this invention may be applied for conductor wires bonded to the pattern on a printed-circuit board when the bare chip is assembled directly on a printed board.
- the conductor wires of this invention may be realized in TQFP, BGA (Ball Grid Array), CSP (Chip Size Package), and other semiconductor devices as long as conductor wires are used.
- the amount of rise of conductor wires from the principal surface of a semiconductor chip can be reduced. As a result, it is possible to realize a thin semiconductor device.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The purpose of this invention is to provide a type of conductor wires which are appropriate for making a thin semiconductor device and can minimize problems of short-circuits between wires. This invention pertains to a type of conductor wires for electrically connecting a semiconductor chip to external conductors. According to this invention, each of conductor wires (5) has first end portion (5 a) bonded to electrode pad (2) of semiconductor chip (1), second end portion (5 b) bonded to external conductor (4), and bending point (A1) which is positioned between the aforementioned first and second end portions and is bent almost in the direction opposite to the direction that the conductor wire rises at the aforementioned first end portion. As the bending point is bent almost in the direction opposite to the rising direction of the conductor wire, the amount of rise of the conductor wire from the principal surface of the semiconductor chip can be reduced, and the thickness of the semiconductor device can be reduced. Also, by setting said conductor wires (5), and wires (6) of the conventional structure alternately, it is possible to ensure sufficient clearance between wires, so that it is possible to reduce the possibility of short-circuits among the conductor wires.
Description
This invention pertains to a type of conductor wires for making electric connection of a semiconductor chip to external conductors. In particular, this invention provides an excellent type of conductor wires that can reduce the thickness of the package and can avoid problems of short-circuits among the wires.
Wire bonding is the most common method for connecting a semiconductor chip to external conductors, such as a pattern or lead frame on an insulating substrate. In the wire bonding method, the semiconductor chip is connected to the external conductors by fine wires of gold (Au) or aluminum (Al) fed from a tool known as a capillary tool. In the manufacturing process, the wires fed from the capillary tool have one end bonded to the electrode pads of a semiconductor chip, followed by looping, that is, forming a loop, and then have the other end bonded to the external conductors.
The aforementioned wire looping plays an important role in absorbing the influence of contraction of the wires under pressure and heat during the molding operation. On the other hand, however, the amount of rise of the wire loops from the surface of the semiconductor chip directly affects the thickness of the semiconductor device. It is necessary to have sufficiently thick packaging material on the surface of the semiconductor chip to completely cover and shield the aforementioned wires. On the other hand, with the miniaturization trend of electronic and communications equipment, there is a requirement for even smaller and thinner semiconductor devices. Consequently, it is important to further reduce the thickness of the packaging material on tile semiconductor chip.
On the other hand, with progress in realizing higher speeds and more functions for semiconductor devices, the number of connecting terminals of semiconductor devices is on the rise. An increase in the number of the connecting terminals means an increase in the number of the wires inside the device. As a result, along with the aforementioned demand for smaller device sizes, the danger of short-circuits between adjacent wires becomes higher. That is, as the distance between adjacent wires becomes smaller, spread of the wire configuration during manufacturing and deformation of the wires during injection molding lead to short-circuits of the wires. When electrode pads (2) are set in a zigzag pattern on semiconductor chip (1), as shown in FIG. 6, it is possible to increase the number of connecting terminals per unit area. As the distance between wires W is further reduced, the aforementioned problem becomes exacerbated.
As a method for solving the aforementioned problems, a bending point usually called the “bend” (point P in the figure) is formed midway along wire W, as shown in FIG. 7, so as to increase the resistance to deformation. However, even with such a bending point, it is still impossible to eliminate deformation of the wires, and there is still a danger of short-circuits, depending on the configuration of the wires.
As another method to reduce the danger of wire short-circuits, as shown in FIG. 8, the heights of adjacent wire loops are changed alternately in bonding. Even when adjacent wires move near each other in the plane due to the movement of wires during manufacturing, it is still possible to ensure a sufficient gap between the wires in the height direction, and it is thus possible to minimize the danger of short-circuits. However, in order to ensure a sufficient gap in the height direction, the thickness of the packaging material on the semiconductor chip has to be increased. This is a disadvantage.
The purpose of this invention is to provide a type of conductor wires appropriate for realizing a thin semiconductor device.
Another purpose of this invention is to provide a type of conductor wires that can minimize the problem of short-circuiting between wires while the thickness of the semiconductor device is reduced.
This invention pertains to a type of conductor wires for electrically connecting the semiconductor chip to external conductors. Each of the conductor wires in this invention has a first end portion bonded to the electrode pad of the semiconductor chip, a second end portion bonded to the external conductor, and a bending point which is positioned between the aforementioned first and second end portions and is bent almost in the direction opposite to the direction that the conductor wire rises at the aforementioned first end portion. The aforementioned bending point is usually called the “bend.” It refers to the site on the wire intentionally bent during manufacturing. As the bending point is bent almost in the direction opposite to the rising direction of the conductor wire, it is possible to reduce the amount of rise of the conductor wire from the principal surface of the semiconductor chip, so that the semiconductor device can be made even thinner.
According to this invention, in order to reduce the amount of rise of the conductor wire as much as possible, it is preferred that the aforementioned bending point be positioned on the side opposite to the rising side of the conductor wire with respect to the position of a straight line connecting the aforementioned first end portion and the aforementioned second end portion, and that the bending point position be shifted toward the aforementioned first end portion.
Also, in order to further increase the resistance of the conductor wires to deformation, plural said bending points may be formed on each conductor wire.
This invention also provides a type of semiconductor device having the aforementioned conductor wires. The semiconductor device of this invention has plural first conductor wires and plural second conductor wires set close among the aforementioned first conductor wires. Each said first conductor wire has a bending point bent in the rising direction of the conductor wire. Each said second conductor wire has a bending point bent in the direction almost opposite to the rising direction. In this way, a sufficient gap is formed between the conductor wires having bending points in different directions, and the possibility of short-circuits is reduced.
FIG. 1 is an enlarged view of the main portion of the semiconductor device using the conductor wires of this invention.
FIG. 2 is a diagram illustrating an example in which this invention is adopted in a semiconductor device using a zigzag-shaped bonding configuration.
FIG. 3 is a diagram illustrating the bonding procedure for the conductor wires of this invention.
FIG. 4 is a diagram illustrating another embodiment of this invention having plural bending points.
FIG. 5 is a diagram comparing the conventional structure with conductor wires in an embodiment of this invention.
FIG. 6 is a plane view illustrating the shape of the zigzag bonding configuration.
FIG. 7 is a diagram illustrating the shape of conventional conductor wires.
FIG. 8 is a diagram illustrating the shape of conventional conductor wires in a zigzag-shaped bonding confirmation.
In the figures, 1 is a semiconductor chip, 2 is an electrode pad, 3 a die pad, 4 an inner lead, 5 a conductive wire, 5 a and b end portions, and A the bending point.
In the following, the embodiment of this invention will be explained in more detail with reference to figures. FIG. 1 is a diagram illustrating the enlarged main portion of the semiconductor device using the conductor wires of this invention. The semiconductor device shown in FIG. 1 is TQFP (Thin Quad Flat Package). In TQFP, semiconductor chip (1) is attached on die pad (3), and inner leads (4) of the lead frame are set around semiconductor chip (1) at a distance apart from it. Electrode pads (2) set around the principal surface of semiconductor chip (1) and inner leads (4) of the lead frame are electrically connected to each other by conductor wires (5). No further explanation will be made on the general structure of TQFP, as it is well known to specialists.
As shown in the figure, conductor wire (5) has downward bending point A1. Bending point A1 is shifted in position from the midpoint of the total length of conductor wire (5) to end portion (5 a) towards electrode pad (2). Conductor wire (5) also has bending point A2 bent a little upward and shifted toward end portion (5 b). Conductor wire (5), after rising a little from end portion (5 a), extends steeply downward to reach bending point A1. At bending point A1, conductor wire (5) is bent through a large angle. From bending point A2, the conductor wire is gently bent downward to reach end portion (5 b) at inner lead (4).
FIG. 1 shows straight line L that connects two end portions (5 a) and (5 b) of conductor wire (5). Bending point A1 is positioned below said straight line L. If the height position of bending point A1 with respect to straight line L is lowered, the height from the surface of the semiconductor chip to the maximum rise of the conductor wire (position of point P on the wire) becomes smaller. However, if the position of bending point A1 is too low, the stress applied to wire's end portion (5 a) becomes larger and may lead to a poor joint at electrode pad (2). In consideration of this problem, it is necessary to adjust the position of bending point A1. As the height position of bending point A1 can be controlled to a certain degree by its opening angle ø, one may adjust said opening angle ø when conductor wires (5) are installed.
In the aforementioned semiconductor device, all of conductor wires (5) led out from electrode pads (2) have the shape shown in FIG. 1. Although not shown in the figure, semiconductor chip (1) and conductor wires (5) are sealed by a molding resin that forms the outer shape of the package.
FIG. 2 is a diagram illustrating another embodiment of this invention. In this figure, semiconductor chip (1) has electrode pads (2 a) and (2 b) set in the same zigzag configuration as shown in FIG. 6. In the figure, two types of conductor wires. (5) and (6), with respect to their shape, are shown. Conductor wires (5) have the same shape as shown in FIG. 1, with end portion (5 a) bonded to the row of electrode pads (2 a) on the outer side. Other conductor wires (6) are conventional lead-out wires, with end portion (6 a) bonded to electrode pad (2 b) on the inner side. That is, for each conductor wire (6), after leading out vertically from electrode pad (2 b), it is bent almost at a right angle so that it extends horizontally. Then, at the middle portion it deviates towards inner lead (4), that is, at bending point B, it is bent slightly, and it then reaches inner lead (4).
Conductor wires (5) and (6) are led out from zigzag-configured electrode pads (2 a) and (2 b) alternately. Consequently, no conductor wires of the same shape are set adjacent to each other. In this case, bending point A1 of conductor wire (5) faces downward, while bending point B of conductor wire (6) faces upward. Consequently, in middle region M between these two conductor wires, the conductor wires are separated sufficiently from each other in the height direction. For middle region M between the conductor wires, deformation during injection of the molding resin is large, and positional error at the time of wire bonding also appears to be maximum here. Depending on the relative position relationship between the aforementioned two conductor wires, the possibility of contact between wires in said middle region M can be minimized. The two conductor wires are set relatively near each other in the height direction in the regions near the two end portions. However, in the regions near the wire end portions, deformation during injection of the molding resin and error in position during wire bonding are small. Consequently, there is little possibility for the two conductor wires to make contact with each other. Also, said conductor wire (6) has an upward bending point B. However, even when there is no such bending point, for the combination of a wire without such a bending point and said conductor wire (5) having the aforementioned downward bending point, sufficient clearance can still be ensured between the two wires.
FIG. 3 is a diagram illustrating the bonding procedure for conductor wires (5) in FIGS. 1 and 2. Although this procedure is a basic bonding operation not different from the conventional method, the movement path of the capillary tool nevertheless has certain characteristic features in this case, in order to realize the special shape of said conductor wires (5).
At first, a ball is formed on the tip of each wire. By means of ultrasonic waves and hot pressure adhesion from capillary tool (10), the tip of the wire is bonded to electrode pad (2) of the semiconductor chip. After the wire is pulled up obliquely to create the amount of rise of the conductor wire from the chip, capillary tool (10) is further pulled [straight] upward (step (A)). At the position where the bending point is formed a point A1 in the figure), pull-up of capillary tool (10) is stopped. After the capillary tool is moved sideway (step (B)), it is further pulled upward (step (C)).
Then, at the position where bending point A2 is formed in the direction opposite to said bending point A 1, capillary tool (10) is moved to the left side (step (D)), and a sufficient bend is applied to bending point A1. Then, the capillary tool is pulled upward (step (E)). Finally, while the wire is pulled out, the capillary tool is driven to move to perform bonding on inner lead (4) (step (F)).
FIG. 4 is a diagram illustrating another embodiment of the conductor wires in this invention. In this embodiment, conductor wire (7) has plural downward bending points C. As shown in the figure, wire (7) has downward bending points C1-C3 formed at three sites so that it is divided into four portions. Formation of plural downward bending points on each conductor wire has the advantage that this can increase the resistance of the conductor wire to deformation, and that it enables setting of the conductor wire such that its entire length is at an average low height. If this embodiment is adopted for one of the two types of wires set alternately as shown in FIG. 2, it is possible to avoid the problem of short-circuits between adjacent wires.
As shown in FIG. 5, samples of conductor wires of the conventional structure and in an embodiment of this invention were prepared, and they were used to compare the height position with respect to the semiconductor chip plane. During formation of the samples, efforts were made to stretch the two wires to have as low a height as possible. Both wires were prepared from A1 wires having length of 4 mm and diameter of 25 μm. Measurement of all of the samples was performed to derive height D of the wire at bending point A with respect to the height of the principal surface of the semiconductor chip, taken as a reference. The results are listed in the following table.
TABLE I | ||
Height of loop | Conventional example (μm) | Embodiment (μm) |
Minimum | 141 | −47 |
Maximum | 145 | −42 |
Average | 142.2 | −44.2 |
Standard deviation | 1.60 | 1.72 |
The results indicated that in this embodiment, the height of the wire at bending point A has an average value as small as 186.4 μm.
In the above, the embodiments of this invention have been explained with reference to figures. However, it is clear that the application range of this invention is not limited to the items defined in the aforementioned embodiments. This invention may be adopted on any type of semiconductor device using conductor wires to electrically connect the semiconductor chip to external conductors. The external conductors for bonding with the conductor wires may be inner leads of a lead frame, a conductor pattern on an insulating substrate, or other conductor parts. Also, this invention may be applied for conductor wires bonded to the pattern on a printed-circuit board when the bare chip is assembled directly on a printed board. The conductor wires of this invention may be realized in TQFP, BGA (Ball Grid Array), CSP (Chip Size Package), and other semiconductor devices as long as conductor wires are used.
According to this invention, the amount of rise of conductor wires from the principal surface of a semiconductor chip can be reduced. As a result, it is possible to realize a thin semiconductor device.
Also, according to this invention, it is possible to realize a relatively large distance between adjacent conductor wires, and it is possible to minimize problems related to short-circuits between wires.
Claims (16)
1. Conductor wiring for electrically connecting a semiconductor chip to an external conductor, said seminconductor chip having a bottom mounted on a base, and an electrode pad or bond pad on a top thereof facing in a first direction, said base having said external conductor on a surface thereof facing in said first direction; said wiring comprising:
a first bonding wire having a first end bonded to said electrode pad on said top of said semiconductor chip, said wire having a second end bonded to said external conductor; and
a bending point formed in said wire between said first and second ends, said bending point being at a level between said top of said semiconductor chip and said bottom thereof, whereby height of said wire above said semiconductor chip is reduced.
2. Conductor wiring of claim 1 wherein said bending point is bent in a direction towards said bottom of said semiconductor chip.
3. Conductor wiring of claim 1 wherein said bending point is closer to said first end than to said second end.
4. Conductor wiring of claim 1 wherein there are plural bending points in said wire, at least one of said plural bending points being at a level between said top of said semiconductor chip and said bottom thereof.
5. Conductor wiring of claim 1 further comprising:
a plurality of electrode pads on said semiconductor chip;
a plurality of external conductors;
a plurality of bonding wires, at least one first bonding wire and at least one second bonding wire not having a bending point formed at a level between said top and said bottom of said semiconductor chip.
6. Conductor wiring of claim 5 further comprising a plurality of first bonding wires and a plurality of second bonding wires, wherein said first bonding wires are interleaved in between a pair of second bonding wires.
7. Conductor wiring of claim 5 wherein said second bonding wire has a bending point above a level of said top of said semiconductor chip.
8. Conductor wiring of claim 6 wherein said plurality of second bonding wires have a bending point above a level of said top of said semiconductor chip.
9. Semiconductor device comprising:
a semiconductor chip having a top side and a bottom side, said top side having a plurality of electrode pads or bond pads thereon facing in a first direction, said semiconductor chip being mounted on a base;
a plurality of external conductors on said base and facing in said first direction;
a plurality of bonding wires electrically connecting each one of said plurality of electrode pads to a corresponding external conductor, at least one of said bonding wires being a first bonding wire having a bending point formed in said wire between a first end of said wire bonded to one of said electrode pads and a second end of said wire bonded to one of said external conductors, said bending point being at a level between said top side and said bottom side of said semiconductor chip, whereby height of said wire above said semiconductor chip is reduced; and a body enclosing said semiconductor chip and said bonding wires.
10. Semiconductor device of claim 9 wherein said bending point is bent in a direction towards said bottom side of said semiconductor chip.
11. Semiconductor device of claim 9 wherein said bending point is closer to said first end than to said second end.
12. Semiconductor device of claim 9 wherein there are plural bending points in said wire, at least one of said plural bending points being at a level between said top side and said bottom side of said semiconductor chip.
13. Semiconductor device of claim 9 wherein said plurality of bonding wires includes at least one second bonding wire not having a bending point formed at a level between said top side and said bottom side of said semiconductor chip.
14. Semiconductor device of claim 13 further comprising a plurality of first bonding wires and a plurality of second bonding wires wherein said first bonding wires are interleaved in between a pair of second bonding wires.
15. Semiconductor device of claim 13 wherein said second bonding wire has a bending point above a level of said top side of said semiconductor chip.
16. Semiconductor device of claim 14 wherein said plurality of second bonding wires have a bending point above a level of said top side of said semiconductor chip.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10-211056 | 1998-07-27 | ||
JP21105698A JP3741184B2 (en) | 1998-07-27 | 1998-07-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US6380634B1 true US6380634B1 (en) | 2002-04-30 |
Family
ID=16599672
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/361,502 Expired - Lifetime US6380634B1 (en) | 1998-07-27 | 1999-07-23 | Conductor wires and semiconductor device using them |
Country Status (2)
Country | Link |
---|---|
US (1) | US6380634B1 (en) |
JP (1) | JP3741184B2 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050029679A1 (en) * | 2001-08-27 | 2005-02-10 | Renesas Technology Corp. | Semiconductor device and wire bonding apparatus |
US20060266804A1 (en) * | 2005-05-17 | 2006-11-30 | Wang Chin S | Chip package and wire bonding process thereof |
US20090014894A1 (en) * | 2007-07-13 | 2009-01-15 | Kabushiki Kaisha Toshiba | Stacked semiconductor device and semiconductor memory device |
US20100148369A1 (en) * | 2008-10-21 | 2010-06-17 | Kabushiki Kaisha Shinkawa | Wire bonding method and semiconductor device |
US20100176500A1 (en) * | 2009-01-15 | 2010-07-15 | Hishioka Maiko | Semiconductor device |
CN102244058A (en) * | 2010-05-13 | 2011-11-16 | 群丰科技股份有限公司 | Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method |
US20120175665A1 (en) * | 2011-01-07 | 2012-07-12 | Samsung Led Co., Ltd. | Light-emitting device package and method of manufacturing the same |
US8513819B2 (en) | 2011-09-09 | 2013-08-20 | Carsem (M) Sdn. Bhd. | Low loop wire bonding |
US8525352B2 (en) | 2011-04-11 | 2013-09-03 | Carsem (M) Sdn.Bhd. | Short and low loop wire bonding |
US20170263568A1 (en) * | 2016-03-10 | 2017-09-14 | Amkor Technology, Inc. | Semiconductor device having conductive wire with increased attachment angle and method |
US10804238B2 (en) * | 2017-02-22 | 2020-10-13 | Murata Manufacturing Co., Ltd. | Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same |
US11342276B2 (en) | 2019-05-24 | 2022-05-24 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and method of manufacturing semiconductor device |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5332211B2 (en) * | 2007-03-07 | 2013-11-06 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
JP5917817B2 (en) * | 2011-03-25 | 2016-05-18 | シチズン電子株式会社 | Wire bonding structure |
JP6447580B2 (en) * | 2016-06-15 | 2019-01-09 | 日亜化学工業株式会社 | Light emitting device |
JP6809522B2 (en) * | 2018-11-29 | 2021-01-06 | 日亜化学工業株式会社 | Light emitting device |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5455167A (en) * | 1977-10-12 | 1979-05-02 | Toshiba Corp | Semiconductor device |
JPS56153754A (en) * | 1980-04-30 | 1981-11-27 | Toshiba Corp | Power transistor |
JPS58192688A (en) * | 1982-04-30 | 1983-11-10 | Chiyouonpa Kogyo Kk | Regulation of wire loop shape in wire bonding device |
US4928871A (en) * | 1988-02-23 | 1990-05-29 | Emhart Deutschland Gmbh | Apparatus and method of controlled feed of a bonding wire to the "wedge" of a bonding head |
US5156323A (en) * | 1991-02-27 | 1992-10-20 | Kabushiki Kaisha Shinkawa | Wire bonding method |
US5205463A (en) * | 1992-06-05 | 1993-04-27 | Kulicke And Soffa Investments, Inc. | Method of making constant clearance flat link fine wire interconnections |
US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
US5623163A (en) * | 1993-09-20 | 1997-04-22 | Nec Corporation | Leadframe for semiconductor devices |
US5717252A (en) * | 1994-07-25 | 1998-02-10 | Mitsui High-Tec, Inc. | Solder-ball connected semiconductor device with a recessed chip mounting area |
US5842628A (en) * | 1995-04-10 | 1998-12-01 | Fujitsu Limited | Wire bonding method, semiconductor device, capillary for wire bonding and ball bump forming method |
US5869905A (en) * | 1996-01-15 | 1999-02-09 | Kabushiki Kaisha Toshiba | Molded packaging for semiconductor device and method of manufacturing the same |
US5884398A (en) * | 1993-11-16 | 1999-03-23 | Form Factor, Inc. | Mounting spring elements on semiconductor devices |
US5917235A (en) * | 1996-08-20 | 1999-06-29 | Nec Corporation | Semiconductor device having LOC structure, a semiconductor device lead frame, TAB leads, and an insulating TAB tape |
US5961029A (en) * | 1997-01-13 | 1999-10-05 | Kabushiki Kaisha Shinkawa | Wire bonding method |
US5989995A (en) * | 1996-12-27 | 1999-11-23 | Kabushiki Kaisha Shinkawa | Semiconductor device and wire bonding method therefor |
US6010057A (en) * | 1996-03-02 | 2000-01-04 | Esec Sa | Method for making a wire connections of predetermined shape |
US6031281A (en) * | 1997-11-21 | 2000-02-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device having dummy bonding wires |
US6068180A (en) * | 1996-12-18 | 2000-05-30 | Texas Instruments Incorporated | System, apparatus, and method for connecting a semiconductor chip to a three-dimensional leadframe |
US6079610A (en) * | 1996-10-07 | 2000-06-27 | Denso Corporation | Wire bonding method |
-
1998
- 1998-07-27 JP JP21105698A patent/JP3741184B2/en not_active Expired - Lifetime
-
1999
- 1999-07-23 US US09/361,502 patent/US6380634B1/en not_active Expired - Lifetime
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5455167A (en) * | 1977-10-12 | 1979-05-02 | Toshiba Corp | Semiconductor device |
JPS56153754A (en) * | 1980-04-30 | 1981-11-27 | Toshiba Corp | Power transistor |
JPS58192688A (en) * | 1982-04-30 | 1983-11-10 | Chiyouonpa Kogyo Kk | Regulation of wire loop shape in wire bonding device |
US4928871A (en) * | 1988-02-23 | 1990-05-29 | Emhart Deutschland Gmbh | Apparatus and method of controlled feed of a bonding wire to the "wedge" of a bonding head |
US5156323A (en) * | 1991-02-27 | 1992-10-20 | Kabushiki Kaisha Shinkawa | Wire bonding method |
US5205463A (en) * | 1992-06-05 | 1993-04-27 | Kulicke And Soffa Investments, Inc. | Method of making constant clearance flat link fine wire interconnections |
US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
US5623163A (en) * | 1993-09-20 | 1997-04-22 | Nec Corporation | Leadframe for semiconductor devices |
US5884398A (en) * | 1993-11-16 | 1999-03-23 | Form Factor, Inc. | Mounting spring elements on semiconductor devices |
US5717252A (en) * | 1994-07-25 | 1998-02-10 | Mitsui High-Tec, Inc. | Solder-ball connected semiconductor device with a recessed chip mounting area |
US5842628A (en) * | 1995-04-10 | 1998-12-01 | Fujitsu Limited | Wire bonding method, semiconductor device, capillary for wire bonding and ball bump forming method |
US5869905A (en) * | 1996-01-15 | 1999-02-09 | Kabushiki Kaisha Toshiba | Molded packaging for semiconductor device and method of manufacturing the same |
US6010057A (en) * | 1996-03-02 | 2000-01-04 | Esec Sa | Method for making a wire connections of predetermined shape |
US5917235A (en) * | 1996-08-20 | 1999-06-29 | Nec Corporation | Semiconductor device having LOC structure, a semiconductor device lead frame, TAB leads, and an insulating TAB tape |
US6079610A (en) * | 1996-10-07 | 2000-06-27 | Denso Corporation | Wire bonding method |
US6068180A (en) * | 1996-12-18 | 2000-05-30 | Texas Instruments Incorporated | System, apparatus, and method for connecting a semiconductor chip to a three-dimensional leadframe |
US5989995A (en) * | 1996-12-27 | 1999-11-23 | Kabushiki Kaisha Shinkawa | Semiconductor device and wire bonding method therefor |
US5961029A (en) * | 1997-01-13 | 1999-10-05 | Kabushiki Kaisha Shinkawa | Wire bonding method |
US6031281A (en) * | 1997-11-21 | 2000-02-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device having dummy bonding wires |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050029679A1 (en) * | 2001-08-27 | 2005-02-10 | Renesas Technology Corp. | Semiconductor device and wire bonding apparatus |
US20060266804A1 (en) * | 2005-05-17 | 2006-11-30 | Wang Chin S | Chip package and wire bonding process thereof |
US7968993B2 (en) | 2007-07-13 | 2011-06-28 | Kabushiki Kaisha Toshiba | Stacked semiconductor device and semiconductor memory device |
US20090014894A1 (en) * | 2007-07-13 | 2009-01-15 | Kabushiki Kaisha Toshiba | Stacked semiconductor device and semiconductor memory device |
US20110079904A1 (en) * | 2008-10-21 | 2011-04-07 | Kabushiki Kaisha Shinkawa | Semiconductor device |
US7851347B2 (en) | 2008-10-21 | 2010-12-14 | Kabushiki Kaisha Shinkawa | Wire bonding method and semiconductor device |
US8232656B2 (en) | 2008-10-21 | 2012-07-31 | Kabushiki Kaisha Shinkawa | Semiconductor device |
US20100148369A1 (en) * | 2008-10-21 | 2010-06-17 | Kabushiki Kaisha Shinkawa | Wire bonding method and semiconductor device |
US20100176500A1 (en) * | 2009-01-15 | 2010-07-15 | Hishioka Maiko | Semiconductor device |
US8278768B2 (en) * | 2009-01-15 | 2012-10-02 | Panasonic Corporation | Semiconductor device including wires connecting electrodes to an inner lead |
CN102244058A (en) * | 2010-05-13 | 2011-11-16 | 群丰科技股份有限公司 | Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method |
US20120175665A1 (en) * | 2011-01-07 | 2012-07-12 | Samsung Led Co., Ltd. | Light-emitting device package and method of manufacturing the same |
US8829691B2 (en) * | 2011-01-07 | 2014-09-09 | Samsung Electronics Co., Ltd. | Light-emitting device package and method of manufacturing the same |
US8946913B2 (en) | 2011-04-11 | 2015-02-03 | Carsem (M) Sdn. Bhd. | Short and low loop wire bonding |
US8525352B2 (en) | 2011-04-11 | 2013-09-03 | Carsem (M) Sdn.Bhd. | Short and low loop wire bonding |
US8513819B2 (en) | 2011-09-09 | 2013-08-20 | Carsem (M) Sdn. Bhd. | Low loop wire bonding |
US8941249B2 (en) | 2011-09-09 | 2015-01-27 | Carsem (M) Sdn, Bhd. | Low loop wire bonding |
US20170263568A1 (en) * | 2016-03-10 | 2017-09-14 | Amkor Technology, Inc. | Semiconductor device having conductive wire with increased attachment angle and method |
US10141269B2 (en) * | 2016-03-10 | 2018-11-27 | Amkor Technology, Inc. | Semiconductor device having conductive wire with increased attachment angle and method |
US10943871B2 (en) | 2016-03-10 | 2021-03-09 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device having conductive wire with increased attachment angle and method |
US20210143105A1 (en) * | 2016-03-10 | 2021-05-13 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device having conductive wire with increased attachment angle and method |
US11804447B2 (en) * | 2016-03-10 | 2023-10-31 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device having conductive wire with increased attachment angle and method |
US10804238B2 (en) * | 2017-02-22 | 2020-10-13 | Murata Manufacturing Co., Ltd. | Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same |
US11417625B2 (en) * | 2017-02-22 | 2022-08-16 | Murata Manufacturing Co., Ltd. | Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same |
US11342276B2 (en) | 2019-05-24 | 2022-05-24 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP3741184B2 (en) | 2006-02-01 |
JP2000049185A (en) | 2000-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6380634B1 (en) | Conductor wires and semiconductor device using them | |
US6080264A (en) | Combination of semiconductor interconnect | |
USRE35496E (en) | Semiconductor device and method of producing the same | |
KR100372153B1 (en) | Multi-layer lead frame | |
US5172851A (en) | Method of forming a bump electrode and manufacturing a resin-encapsulated semiconductor device | |
US6372625B1 (en) | Semiconductor device having bonding wire spaced from semiconductor chip | |
US5235211A (en) | Semiconductor package having wraparound metallization | |
US6838767B2 (en) | Semiconductor device | |
US5708304A (en) | Semiconductor device | |
KR19990029932A (en) | Method and apparatus for wire bond package for integrated circuits | |
US4916506A (en) | Integrated-circuit lead-frame package with low-resistance ground-lead and heat-sink means | |
US5569956A (en) | Interposer connecting leadframe and integrated circuit | |
US5751057A (en) | Lead on chip lead frame design without jumpover wiring | |
US6107676A (en) | Leadframe and a method of manufacturing a semiconductor device by use of it | |
KR20010006920A (en) | Semiconductor device and method for manufacturing same | |
US20090039509A1 (en) | Semiconductor device and method of manufacturing the same | |
US5704593A (en) | Film carrier tape for semiconductor package and semiconductor device employing the same | |
EP0210371A1 (en) | Semiconductor device having a plurality of leads | |
US6268644B1 (en) | Semiconductor device | |
JPH06302638A (en) | Semiconductor device | |
KR100390466B1 (en) | multi chip module semiconductor package | |
KR100350084B1 (en) | Method for wire bonding in semiconductor package | |
KR930004255B1 (en) | Resin sealed semiconductor device | |
JPH0256942A (en) | Semiconductor device | |
JPH0754841B2 (en) | Insulator-sealed circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:UMEHARA, NORITO;TEXAS INSTRUMENTS JAPAN, LTD.;REEL/FRAME:010273/0419 Effective date: 19990903 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |