US6372408B1 - Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles - Google Patents

Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles Download PDF

Info

Publication number
US6372408B1
US6372408B1 US09/598,374 US59837400A US6372408B1 US 6372408 B1 US6372408 B1 US 6372408B1 US 59837400 A US59837400 A US 59837400A US 6372408 B1 US6372408 B1 US 6372408B1
Authority
US
United States
Prior art keywords
puddle
semiconductor wafer
development
photoresist
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/598,374
Other languages
English (en)
Inventor
Zhijian Lu
Alan Thomas
Alois Gutmann
Kuang Jung Chen
Margaret C. Lawson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Priority to US09/598,374 priority Critical patent/US6372408B1/en
Assigned to INFINEON TECHNOLOGIES NORTH AMERICA CORP. reassignment INFINEON TECHNOLOGIES NORTH AMERICA CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GUTMANN, ALOIS, LU, ZHIJIAN
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, KUANG JUNG, LAWSON, MARGARET C., THOMAS, ALAN
Priority to DE60142833T priority patent/DE60142833D1/de
Priority to EP01948563A priority patent/EP1292864B1/fr
Priority to PCT/US2001/019815 priority patent/WO2001099161A2/fr
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Publication of US6372408B1 publication Critical patent/US6372408B1/en
Application granted granted Critical
Assigned to QIMONDA AG reassignment QIMONDA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: QIMONDA AG
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/3021—Imagewise removal using liquid means from a wafer supported on a rotating chuck

Definitions

  • This invention relates to semiconductor fabrication lithography, lithographic resist, and the development of same, and to a method for reducing the incidence of undesired post-development defects, denoted as “Blob Defects”, which may remain on a surface of a semiconductor wafer being processed after the development of the resist.
  • DUV deep ultraviolet
  • DUV photoresist materials have been identified, and are in use around the world, which demonstrate most, but not all of these important characteristics.
  • One of the required characteristics which has not been adequately demonstrated is the ability to achieve a low density of photolithographic related defects.
  • most of the DUV photoresist materials which are in common use exhibit a class of post-development defects which are defined as “Blob Defects”, in which fragments, pieces, or particles of the original components of the photoresist material, which should have been removed, remain in and around small openings in the photoresist after the photoresist has been exposed and developed, potentially blocking or partially blocking such openings.
  • Modem photoresist materials are typically developed using a technique known as Puddle Development.
  • Puddle Development a technique known as Puddle Development.
  • the use of this technique is well known in the field of semiconductor lithography.
  • This prior art method comprises the following steps. A semiconductor wafer which has been prepared with photoresist material and which has been exposed to the desired pattern of light is first given a post exposure bake and then cooled to near ambient room temperature. The photoresist is then developed as follows. The semiconductor wafer is placed on a spinner head and rotated at a high speed while a small amount of liquid, either developer solution or deionized water, is dispensed onto the surface of the semiconductor wafer to pre-wet the surface of the photoresist.
  • liquid either developer solution or deionized water
  • the high speed of rotation generates sufficient centrifugal force to cause the liquid to be thrown off of the periphery of the semiconductor wafer as it is dispensed onto the central portion of the wafer. No liquid remains on the surface of the semiconductor wafer.
  • the speed of rotation of the semiconductor wafer is then reduced to a lower value and a quantity of developer solution is dispensed onto the surface of the semiconductor wafer.
  • the lower speed of rotation is such that centrifugal force spreads the developer solution out to the periphery of the semiconductor wafer, but the centrifugal force is insufficient to overcome the surface tension of the developer solution, and the developer solution is not thrown from the surface of the semiconductor wafer but remains as a pool, or puddle, on the surface.
  • the puddle of developer solution is allowed to remain on the surface of the semiconductor wafer for a time sufficient to allow complete development of the exposed photoresist material.
  • the speed of rotation is then increased to a higher value at which centrifugal force will cause the developer solution to be thrown from the surface of the semiconductor wafer.
  • the semiconductor wafer is then rinsed and dried, completing the development of the photoresist.
  • the present inventive method of developing photoresist employs the use of at least one Puddle Development cycle and at least one Puddle Rinse cycle.
  • Blob Defects particles of the components of the photoresist, denoted as “Blob Defects”, can remain in and around the openings created in the photoresist.
  • the photoresist material is composed of a mixture of various components, including a base polymer and photosensitive elements.
  • the Blob Defects appear to be an aggregation of hydrophobic materials having low solubility in the photoresist developer solution. The mechanisms and dynamics by which these Blob Defects are formed and adhere to the structures being processed are not completely understood.
  • the present invention is directed to a method of developing an exposed layer of photoresist material on a semiconductor wafer to reduce the incidence of Blob Defects.
  • the method comprises the steps of developing the layer of photoresist first using a Puddle Development cycle, and upon completion of the Puddle Development cycle, subjecting the semiconductor wafer to a Puddle Rinse cycle.
  • the semiconductor wafer may be subjected to multiple additional Puddle Rinse cycles.
  • the present invention is directed to a method of developing an exposed layer of photoresist material on a semiconductor wafer to reduce the incidence of Blob Defects.
  • the method comprises the steps of subjecting the semiconductor wafer to a sequence of Puddle cycles which are chosen from a group consisting of a Puddle Development cycle and a Puddle Rinse cycle, with at least one of the chosen cycles being a Puddle Development cycle.
  • the present invention is directed to a method of developing an exposed layer of x-ray sensitive x-ray resist material on a semiconductor wafer to reduce the incidence of Blob Defects.
  • the method comprises the steps of developing the layer of x-ray resist material first using a Puddle Development cycle, and upon completion of the Puddle Development cycle, subjecting the semiconductor wafer to a Puddle Rinse cycle.
  • the present invention is directed to a method of developing an exposed layer of electron beam sensitive e-beam resist material on a semiconductor wafer to reduce the incidence of Blob Defects.
  • the method comprises the steps of developing the layer of e-beam resist first using a Puddle Development cycle, and upon completion of the Puddle Development cycle, subjecting the semiconductor wafer to a Puddle Rinse cycle.
  • the present invention is directed to a method of developing an exposed layer of ion beam sensitive resist material on a semiconductor wafer to reduce the incidence of Blob Defects.
  • the method comprises the steps of developing the layer of ion beam sensitive resist first using a Puddle Development cycle, and upon completion of the Puddle Development cycle, subjecting the semiconductor wafer to a Puddle Rinse cycle.
  • Table 1 illustrates the effect of multiple Puddle Development and Rinse cycles on the number of Blob Defects remaining on the surface of a semiconductor wafer after the completion of the exposure and development of the photoresist material.
  • this method of reducing the number of Blob Defects remaining on the semiconductor wafer may be combined with other methods of achieving such reductions.
  • the method of using multiple Puddle Development and Puddle Rinse cycles may be combined with the use of multiple patterned and non-patterned exposures, as described in the above identified related application being filed concurrently with this application.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
US09/598,374 2000-06-21 2000-06-21 Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles Expired - Lifetime US6372408B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US09/598,374 US6372408B1 (en) 2000-06-21 2000-06-21 Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles
DE60142833T DE60142833D1 (de) 2000-06-21 2001-06-21 Verfahren zur verringerung von entwicklungsdefekten in und um öffnungen in photolack mittels mehrfacher entwickler/spülzyklen
EP01948563A EP1292864B1 (fr) 2000-06-21 2001-06-21 Procede de reduction des defauts apres developpement dans et autour des orifices formes dans le photoresist au moyen de plusieurs cycles de developpement et rin age
PCT/US2001/019815 WO2001099161A2 (fr) 2000-06-21 2001-06-21 Procede de reduction des defauts apres developpement dans et autour des orifices formes dans le photoresist au moyen de plusieurs cycles de developpement et rinçage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/598,374 US6372408B1 (en) 2000-06-21 2000-06-21 Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles

Publications (1)

Publication Number Publication Date
US6372408B1 true US6372408B1 (en) 2002-04-16

Family

ID=24395299

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/598,374 Expired - Lifetime US6372408B1 (en) 2000-06-21 2000-06-21 Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles

Country Status (4)

Country Link
US (1) US6372408B1 (fr)
EP (1) EP1292864B1 (fr)
DE (1) DE60142833D1 (fr)
WO (1) WO2001099161A2 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759351B2 (en) * 2000-01-11 2004-07-06 International Business Machines Corporation Method for eliminating development related defects in photoresist masks
US20040175938A1 (en) * 2002-06-23 2004-09-09 John Grunwald Method for metalizing wafers
US20050142880A1 (en) * 2003-12-27 2005-06-30 Park Tae W. Polymer removal method for use in manufacturing semiconductor devices
US20070099429A1 (en) * 2005-10-28 2007-05-03 Stefan Brandl Post exposure resist bake
US20070166640A1 (en) * 2006-01-19 2007-07-19 Yayi Wei Defect reduction in immersion lithography
US7470503B1 (en) * 2005-04-29 2008-12-30 Infineon Technologies Ag Method for reducing lithography pattern defects
US9012133B2 (en) 2011-08-30 2015-04-21 International Business Machines Corporation Removal of alkaline crystal defects in lithographic patterning
US11022891B2 (en) 2017-02-23 2021-06-01 International Business Machines Corporation Photoresist bridging defect removal by reverse tone weak developer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2383849A (en) * 2002-01-03 2003-07-09 Zarlink Semiconductor Ltd Resist development

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292605A (en) 1990-05-18 1994-03-08 Xinix, Inc. Method for control of photoresist develop processes
US5759749A (en) * 1995-02-28 1998-06-02 Pioneer Electronic Corporation Developing method and developing apparatus for optical record medium
US6238848B1 (en) * 1999-04-02 2001-05-29 Tokyo Electron Limited Developing method and developing apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342738A (en) * 1991-06-04 1994-08-30 Sony Corporation Resist film developing method and an apparatus for carrying out the same
EP0887706A1 (fr) * 1997-06-25 1998-12-30 Wako Pure Chemical Industries Ltd Composition pour photoréserve contenant un agent réticulant spécifique
US5985497A (en) * 1998-02-03 1999-11-16 Advanced Micro Devices, Inc. Method for reducing defects in a semiconductor lithographic process
JP3362781B2 (ja) * 2000-02-03 2003-01-07 日本電気株式会社 現像処理方法および装置、現像制御装置、情報記憶媒体

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292605A (en) 1990-05-18 1994-03-08 Xinix, Inc. Method for control of photoresist develop processes
US5759749A (en) * 1995-02-28 1998-06-02 Pioneer Electronic Corporation Developing method and developing apparatus for optical record medium
US6238848B1 (en) * 1999-04-02 2001-05-29 Tokyo Electron Limited Developing method and developing apparatus

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759351B2 (en) * 2000-01-11 2004-07-06 International Business Machines Corporation Method for eliminating development related defects in photoresist masks
US20040175938A1 (en) * 2002-06-23 2004-09-09 John Grunwald Method for metalizing wafers
US20050142880A1 (en) * 2003-12-27 2005-06-30 Park Tae W. Polymer removal method for use in manufacturing semiconductor devices
US7470503B1 (en) * 2005-04-29 2008-12-30 Infineon Technologies Ag Method for reducing lithography pattern defects
US20070099429A1 (en) * 2005-10-28 2007-05-03 Stefan Brandl Post exposure resist bake
US7396482B2 (en) 2005-10-28 2008-07-08 Infineon Technologies Ag Post exposure resist bake
US20070166640A1 (en) * 2006-01-19 2007-07-19 Yayi Wei Defect reduction in immersion lithography
US9012133B2 (en) 2011-08-30 2015-04-21 International Business Machines Corporation Removal of alkaline crystal defects in lithographic patterning
US11022891B2 (en) 2017-02-23 2021-06-01 International Business Machines Corporation Photoresist bridging defect removal by reverse tone weak developer
US11022890B2 (en) 2017-02-23 2021-06-01 International Business Machines Corporation Photoresist bridging defect removal by reverse tone weak developer

Also Published As

Publication number Publication date
WO2001099161A2 (fr) 2001-12-27
EP1292864A2 (fr) 2003-03-19
DE60142833D1 (de) 2010-09-30
EP1292864B1 (fr) 2010-08-18
WO2001099161A3 (fr) 2002-10-10

Similar Documents

Publication Publication Date Title
US9012132B2 (en) Coating material and method for photolithography
US6713236B2 (en) Lithography method for preventing lithographic exposure of peripheral region of semiconductor wafer
US7195863B2 (en) Development defect preventing process and material
US6372408B1 (en) Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles
US6420101B1 (en) Method of reducing post-development defects in and around openings formed in photoresist by use of non-patterned exposure
JP2000331928A (ja) リソグラフ方法
US6599683B1 (en) Photoresist developer with reduced resist toppling and method of using same
US5885756A (en) Methods of patterning a semiconductor wafer having an active region and a peripheral region, and patterned wafers formed thereby
US4816380A (en) Water soluble contrast enhancement layer method of forming resist image on semiconductor chip
KR0160921B1 (ko) 레지스트 패턴의 형성방법
US20020187434A1 (en) Process for device fabrication in which the size of lithographically produced features is subsequently reduced
JPH07335519A (ja) パタン形成方法
US6649525B1 (en) Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process
JP3861851B2 (ja) レジストパターン形成方法および半導体装置の製造方法
JP3055512B2 (ja) 化学増幅ポジ型レジスト
JPH06110214A (ja) レジストパターンの形成方法
JP2524993B2 (ja) レジストパタ−ンの形成方法
JPH0290170A (ja) パターン形成方法
US6270949B1 (en) Single component developer for copolymer resists
US6281130B1 (en) Method for developing ultra-thin resist films
JP3036500B2 (ja) フォトレジストパターン形成方法及び半導体基板
JPS62226148A (ja) パタ−ン形成方法
US6759179B1 (en) Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process
JPS61241745A (ja) ネガ型フオトレジスト組成物及びレジストパタ−ン形成方法
JPH11297607A (ja) パターン形成方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP., CALIFOR

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LU, ZHIJIAN;GUTMANN, ALOIS;REEL/FRAME:011286/0321;SIGNING DATES FROM 20001109 TO 20001113

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:THOMAS, ALAN;CHEN, KUANG JUNG;LAWSON, MARGARET C.;REEL/FRAME:011286/0412

Effective date: 20001109

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES NORTH AMERICA CORP.;REEL/FRAME:012670/0044

Effective date: 20020211

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: QIMONDA AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023853/0401

Effective date: 20060425

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001

Effective date: 20141009