US6037648A - Semiconductor structure including a conductive fuse and process for fabrication thereof - Google Patents
Semiconductor structure including a conductive fuse and process for fabrication thereof Download PDFInfo
- Publication number
- US6037648A US6037648A US09/105,647 US10564798A US6037648A US 6037648 A US6037648 A US 6037648A US 10564798 A US10564798 A US 10564798A US 6037648 A US6037648 A US 6037648A
- Authority
- US
- United States
- Prior art keywords
- layer
- semiconductor structure
- conductive
- etch stop
- fuse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- E—FIXED CONSTRUCTIONS
- E01—CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
- E01F—ADDITIONAL WORK, SUCH AS EQUIPPING ROADS OR THE CONSTRUCTION OF PLATFORMS, HELICOPTER LANDING STAGES, SIGNS, SNOW FENCES, OR THE LIKE
- E01F9/00—Arrangement of road signs or traffic signals; Arrangements for enforcing caution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- E—FIXED CONSTRUCTIONS
- E01—CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
- E01H—STREET CLEANING; CLEANING OF PERMANENT WAYS; CLEANING BEACHES; DISPERSING OR PREVENTING FOG IN GENERAL CLEANING STREET OR RAILWAY FURNITURE OR TUNNEL WALLS
- E01H1/00—Removing undesirable matter from roads or like surfaces, with or without moistening of the surface
- E01H1/02—Brushing apparatus, e.g. with auxiliary instruments for mechanically loosening dirt
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention is concerned with a semiconductor structure that includes a conductive fuse, and more particularly relates to providing a conductive fuse having a self-aligned isolation cap thereon.
- the present invention relates to a fabrication process for achieving the desired structure.
- the fabrication process of the present invention makes it possible to provide a well controlled relatively thin dielectric layer over the fuse which is self-aligned to the fuse.
- DRAM dynamic random access memory
- SRAM static random access memory
- fuses Such can provide for redundancy for the purpose of preventing reduction of yield of the semiconductor devices which may be caused by random defects generated in the manufacturing process.
- the redundant circuit portion is provided as a spare circuit portion having the same function as a specific circuit portion so that the specific circuit portion which has a defect caused during manufacturing may be replaced with the redundant circuit in order to maintain the function of the entire semiconductor.
- fuse links provide for voltage options, packaging pin out options, or any other option desired by the manufacturer to be employed prior to the final processing. This helps increase yield and makes it easier to use one basic design for several different end products.
- the thickness of the insulating layer over the fuse tends to have very large variation.
- the large variation in the final insulation thickness is due to variations in the deposition of isolation between a first and a second conductive level, variations in deposition of the next-to-last insulation layers, non-uniformities during chemical-mechanical polishing and variations in the reactive ion etching to achieve the final thickness.
- the thickness variation occurs because of the cumulative variations of each of the process steps even when each individual step can be reasonably controlled.
- the variation in thickness limits the fuse pitch to that which corresponds to the largest isolation layer generated by the processing.
- the present invention relates to improving the control of the thickness of the insulating layer above a fuse structure. Moreover, the present invention makes possible a fuse structure having a relatively thin self-aligned dielectric layer.
- the invention is concerned with a semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a fuse located at this conductive level.
- the fuse comprises a self-aligned dielectric etch stop layer thereon.
- An insulation structure is provided located above the conductive level, but not above the fuse. Electrical connection is provided through the insulation structure to selected locations of the conductive level. A further insulation structure is provided above the electrical connection.
- the invention encompasses a process for fabricating the above disclosed semiconductor structure. More particularly, the process of the invention comprises providing a semiconductor substrate having a conductive level thereon. A layer of a first dielectric etch stop material is blanket deposited. The layer of the dielectric etch stop material and the conductive level are patterned, preferably by reactive ion etching, thereby creating structures including (i) a fuse structure capped with self-aligned dielectric etch stop material thereon and (ii) conductive lines, and gaps between the structures.
- the process of the invention is preferably continued by depositing a second dielectric material, different from the etch stop material, over the structures and in the gaps.
- a third dielectric material is deposited over the second dielectric material.
- the third dielectric material, second dielectric material and first dielectric material are patterned, preferably by reactive ion etching, to create vias through the third dielectric material, second dielectric material and first dielectric material, thereby exposing selected portions of the conductive level.
- the vias are filled with electrically conductive material to provide electrical interconnection to the selected portions of the conductive level.
- a further insulating layer is provided over the entire structure, and then via is created through the insulating structure down to the etch stop layer on the fuse.
- FIGS. 1-5 illustrate the semiconductor structure of the present invention during various stages of preparation.
- the semiconductor structure of the invention preferably comprises a semiconductor substrate 10; an electrically conductive material at a level 1 on the substrate; a conductive fuse 21 located at the conductive level 1 wherein the fuse comprises a conductive segment of the level 1 conductive material with self-aligned dielectric etch stop layer 2 thereon; insulation structure 3 (optionally including additional insulating layer 13) located above the conductive level 1 and in between conductive lines 22 of the conductive level 1, but not above the fuse 21; and electrical interconnection 4 through the insulation structure 3 (and 13 if present) to selected locations of the conductive level 1.
- the structure of the invention preferably further comprises a further insulating structure shown as layers 5-7 over the electrical interconnection 4.
- a semiconductor substrate structure 10 is provided with an electrically conductive layer 1 (also referred to as level 1).
- the conductive layer 1 is preferably formed from a conductive material selected from the group consisting of aluminum, copper, aluminum copper alloys, and doped polysilicon having metallic-type conductivity.
- the electrically conductive level 1 may be a wiring level or gate conductor level and may be formed by any technique normally used to form those conductive levels.
- Layer 1 is preferably about 50 to 1000 nanometers thick, more preferably about 200 to 500 nanometers thick.
- a layer 2 of a dielectric etch stop material is blanket deposited on top of layer 1.
- the layer 2 is preferably a silicon nitride and/or silicon oxynitride.
- the silicon nitride and/or silicon oxynitride can be provided by chemical vapor deposition (CVD) or other known technique.
- the maximum thickness of layer 2 is preferably about 450 nanometers.
- Layer 2 is more preferably about 25 to 200 nanometers thick, more preferably about 50 to 100 nanometers thick, a typical example being about 50 nanometers.
- a silicon dioxide layer (not shown) can also be present as a component of layer 2 above the silicon nitride and/or silicon oxynitride layer.
- the dielectric etch stop material layer 2 and the conductive layer 1 are patterned, preferably by reactive ion etching (RIE).
- RIE reactive ion etching
- the substrate is electrically biased in a chamber that has a plasma of gases made up of a reactive component (e.g. fluorinated hydrocarbon) and an inert gas.
- a reactive component e.g. fluorinated hydrocarbon
- the plasma reacts with the layers to produce volatile reaction products that get pumped away from the chamber.
- wet chemical etching may be used as an alternative to reactive ion etching.
- the etching conditions may be altered to conditions more suitable for reactive ion etching of metals where the patterned etch stop material acts as a hard mask patterning the conductive features.
- the patterning step results in the creation of one or more fuses 21 capped with self-aligned dielectric etch stop material.
- the patterning also typically results in the formation of other conductive features such as conductive lines 22 and gaps 20 located between the conductive lines 22.
- the fuses 21 capped by the self-aligned dielectric material are formed prior to providing the next level dielectric material and while there is essentially no material between the conductive lines 21.
- a second dielectric material 3 different from the etch stop material, is deposited in the gaps 20 and over the remaining dielectric etch stop material.
- the second dielectric material 3 is a relatively dense silicon dioxide material provided by using high density plasma enhanced chemical vapor deposition or other technique.
- the thickness of layer 3 above layer 2 is about 40 to 400 nanometers, more preferably about 50 to 200 nanometers.
- a third dielectric layer 13 such as silicon oxide from chemical vapor deposition of tetraethylorthosilicate (TEOS) or a silane may be provided.
- TEOS tetraethylorthosilicate
- layer 13 is about 50 to 1000 nanometers thick, and more preferably about 200 to 400 nanometers thick. In some instances, it may be possible to omit the deposition of silane-derived or TEOS derived silicon oxide if oxide layer 3 is of sufficient thickness.
- the uppermost dielectric layer 3 (or 13 if present) is then preferably planarized using chemical mechanical polishing or other appropriate technique.
- the combined thickness of layers 2, 3 and 13 is preferably about 350 to 1200 nanometers.
- the dielectric layers 3 and 13 are then patterned to provide vias 14 to selected conductive lines 22 and/or other features remaining from conductive layer 1. This patterning can be carried out by reactive ion etching or other suitable technique. A resulting structure is shown in FIG. 3.
- a conductive material such as aluminum, tungsten, titanium, tantalum, or heavily doped polysilicon, is then provided in the vias to provide electrical connection to the underlying conductive feature (e.g. a line 22).
- a portion of conductive material is also provided above the isolation layer 13 and is patterned, using reactive ion etching or other known technique, thereby resulting in the electrical interconnection structure 4.
- a dielectric layer 5 such as silicon dioxide obtained from depositing TEOS.
- This layer 5 is preferably about 100 to 1000 nanometers thick and more preferably about 200 to 600 nanometers thick.
- Another layer 6 of silicon nitride may then be provided by chemical vapor deposition above the TEOS-derived layer 5.
- This layer 6 is preferably about 100 to 1000 nanometers thick, more preferably about 200 to 600 nanometers thick.
- a layer 7 of, for example, photosensitive polyimide is then deposited over layer 6.
- Layer 7 may be deposited by spraying or spin coating and is preferably about 2 to 10 micrometers thick.
- layer 7 is patterned by known lithographic techniques and acts as an etch mask for selectively etching the various dielectric layers above the fuse 21 dielectric etch stop. More particularly, the selective etching is preferably achieved by reactive ion etching.
- nitride layer 6 and oxide layer 5 may be etched using a fluorinated hydrocarbon (e.g., C 4 F 8 ) at about 5 to 15 sccm (typically about 8 sccm) and an inert gas (e.g., argon) at about 50 to 100 sccm (typically about 100 sccm).
- a fluorinated hydrocarbon e.g., C 4 F 8
- an inert gas e.g., argon
- the flow rate of the fluorinated hydrocarbon and inert gas may be adjusted, to about 5 to 15 sccm (typically about 8 sccm) and about 10 to 25 sccm typically about 15 sccm), respectively, in order to etch the underlying silicon oxide layers 3 and 13 while removing at most only very small amounts of underlying nitride-containing etch stop material layer 2 which is the cap for the fuse 21.
- the process of the invention advantageously produces fuses having a controlled thickness insulting layer which provides the design and performance advantages mentioned above.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Civil Engineering (AREA)
- Structural Engineering (AREA)
- Architecture (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (9)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/105,647 US6037648A (en) | 1998-06-26 | 1998-06-26 | Semiconductor structure including a conductive fuse and process for fabrication thereof |
TW088107991A TW415077B (en) | 1998-06-26 | 1999-05-17 | Semiconductor structure including a conductive fuse and process for fabrication thereof |
EP99304728A EP0981161B1 (en) | 1998-06-26 | 1999-06-17 | Process of fabricating a semiconductor structure including a conductive fuse |
DE69939300T DE69939300D1 (en) | 1998-06-26 | 1999-06-17 | Method for producing a semiconductor structure with a conductive fuse |
JP11174401A JP2000058655A (en) | 1998-06-26 | 1999-06-21 | Semiconductor structure containing conductive fuse and its manufacture |
KR1019990023659A KR100350545B1 (en) | 1998-06-26 | 1999-06-23 | Semiconductor structure including a conductive fuse and process for fabrication thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/105,647 US6037648A (en) | 1998-06-26 | 1998-06-26 | Semiconductor structure including a conductive fuse and process for fabrication thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US6037648A true US6037648A (en) | 2000-03-14 |
Family
ID=22307017
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/105,647 Expired - Lifetime US6037648A (en) | 1998-06-26 | 1998-06-26 | Semiconductor structure including a conductive fuse and process for fabrication thereof |
Country Status (6)
Country | Link |
---|---|
US (1) | US6037648A (en) |
EP (1) | EP0981161B1 (en) |
JP (1) | JP2000058655A (en) |
KR (1) | KR100350545B1 (en) |
DE (1) | DE69939300D1 (en) |
TW (1) | TW415077B (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6180503B1 (en) * | 1999-07-29 | 2001-01-30 | Vanguard International Semiconductor Corporation | Passivation layer etching process for memory arrays with fusible links |
US6495901B2 (en) | 2001-01-30 | 2002-12-17 | Infineon Technologies Ag | Multi-level fuse structure |
US6566171B1 (en) * | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
US6573125B2 (en) * | 2001-07-04 | 2003-06-03 | Samsung Electronics Co., Ltd. | Method of opening repair fuse of semiconductor device |
US20040053487A1 (en) * | 2002-09-17 | 2004-03-18 | Taiwan Semiconductor Manufacturing Company | Metal fuse for semiconductor devices |
US20060289899A1 (en) * | 2005-06-22 | 2006-12-28 | Samsung Electronics Co., Ltd. | Semiconductor devices having fuses and methods of forming the same |
US20090026575A1 (en) * | 2006-02-07 | 2009-01-29 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20090302418A1 (en) * | 2008-06-10 | 2009-12-10 | Samsung Electronics Co., Ltd. | Fuse structure of a semiconductor device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121074A (en) * | 1998-11-05 | 2000-09-19 | Siemens Aktiengesellschaft | Fuse layout for improved fuse blow process window |
US20090045484A1 (en) | 2007-08-16 | 2009-02-19 | International Business Machines Corporation | Methods and systems involving electrically reprogrammable fuses |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5444012A (en) * | 1993-07-20 | 1995-08-22 | Hitachi, Ltd. | Method for manufacturing semiconductor integrated circuit device having a fuse element |
US5550399A (en) * | 1994-11-03 | 1996-08-27 | Kabushiki Kaisha Toshiba | Integrated circuit with windowed fuse element and contact pad |
US5578517A (en) * | 1994-10-24 | 1996-11-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of forming a highly transparent silicon rich nitride protective layer for a fuse window |
US5723358A (en) * | 1996-04-29 | 1998-03-03 | Vlsi Technology, Inc. | Method of manufacturing amorphous silicon antifuse structures |
US5789794A (en) * | 1994-12-29 | 1998-08-04 | Siemens Aktiengesellschaft | Fuse structure for an integrated circuit element |
US5872390A (en) * | 1995-08-28 | 1999-02-16 | International Business Machines Corporation | Fuse window with controlled fuse oxide thickness |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59200453A (en) * | 1983-04-27 | 1984-11-13 | Hitachi Ltd | Manufacture of semiconductor device |
JPS6065545A (en) * | 1983-09-21 | 1985-04-15 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device and the same device |
JPS6289338A (en) * | 1985-10-16 | 1987-04-23 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JPS6480038A (en) * | 1987-09-19 | 1989-03-24 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
US5300456A (en) * | 1993-06-17 | 1994-04-05 | Texas Instruments Incorporated | Metal-to-metal antifuse structure |
-
1998
- 1998-06-26 US US09/105,647 patent/US6037648A/en not_active Expired - Lifetime
-
1999
- 1999-05-17 TW TW088107991A patent/TW415077B/en not_active IP Right Cessation
- 1999-06-17 EP EP99304728A patent/EP0981161B1/en not_active Expired - Lifetime
- 1999-06-17 DE DE69939300T patent/DE69939300D1/en not_active Expired - Lifetime
- 1999-06-21 JP JP11174401A patent/JP2000058655A/en active Pending
- 1999-06-23 KR KR1019990023659A patent/KR100350545B1/en not_active IP Right Cessation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5444012A (en) * | 1993-07-20 | 1995-08-22 | Hitachi, Ltd. | Method for manufacturing semiconductor integrated circuit device having a fuse element |
US5578517A (en) * | 1994-10-24 | 1996-11-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of forming a highly transparent silicon rich nitride protective layer for a fuse window |
US5550399A (en) * | 1994-11-03 | 1996-08-27 | Kabushiki Kaisha Toshiba | Integrated circuit with windowed fuse element and contact pad |
US5789794A (en) * | 1994-12-29 | 1998-08-04 | Siemens Aktiengesellschaft | Fuse structure for an integrated circuit element |
US5872390A (en) * | 1995-08-28 | 1999-02-16 | International Business Machines Corporation | Fuse window with controlled fuse oxide thickness |
US5723358A (en) * | 1996-04-29 | 1998-03-03 | Vlsi Technology, Inc. | Method of manufacturing amorphous silicon antifuse structures |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6180503B1 (en) * | 1999-07-29 | 2001-01-30 | Vanguard International Semiconductor Corporation | Passivation layer etching process for memory arrays with fusible links |
US6495901B2 (en) | 2001-01-30 | 2002-12-17 | Infineon Technologies Ag | Multi-level fuse structure |
US6806551B2 (en) | 2001-06-12 | 2004-10-19 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
US6566171B1 (en) * | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
US6573125B2 (en) * | 2001-07-04 | 2003-06-03 | Samsung Electronics Co., Ltd. | Method of opening repair fuse of semiconductor device |
US6753210B2 (en) | 2002-09-17 | 2004-06-22 | Taiwan Semiconductor Manufacturing Company | Metal fuse for semiconductor devices |
US20040053487A1 (en) * | 2002-09-17 | 2004-03-18 | Taiwan Semiconductor Manufacturing Company | Metal fuse for semiconductor devices |
US20040219720A1 (en) * | 2002-09-17 | 2004-11-04 | Jeng Shin-Puu | Metal fuse for semiconductor devices |
US7205588B2 (en) | 2002-09-17 | 2007-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal fuse for semiconductor devices |
US20060289899A1 (en) * | 2005-06-22 | 2006-12-28 | Samsung Electronics Co., Ltd. | Semiconductor devices having fuses and methods of forming the same |
US7510914B2 (en) | 2005-06-22 | 2009-03-31 | Samsung Electronics Co., Ltd. | Semiconductor devices having fuses and methods of forming the same |
US20090184391A1 (en) * | 2005-06-22 | 2009-07-23 | Hyun-Chul Yoon | Semiconductor devices having fuses and methods of forming the same |
US20090026575A1 (en) * | 2006-02-07 | 2009-01-29 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20090302418A1 (en) * | 2008-06-10 | 2009-12-10 | Samsung Electronics Co., Ltd. | Fuse structure of a semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2000058655A (en) | 2000-02-25 |
DE69939300D1 (en) | 2008-09-25 |
TW415077B (en) | 2000-12-11 |
EP0981161B1 (en) | 2008-08-13 |
EP0981161A3 (en) | 2002-06-12 |
KR100350545B1 (en) | 2002-08-28 |
EP0981161A2 (en) | 2000-02-23 |
KR20000006375A (en) | 2000-01-25 |
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