US5912841A - Repair fuse circuit performing complete latch operation using flash memory cell - Google Patents
Repair fuse circuit performing complete latch operation using flash memory cell Download PDFInfo
- Publication number
- US5912841A US5912841A US08/997,063 US99706397A US5912841A US 5912841 A US5912841 A US 5912841A US 99706397 A US99706397 A US 99706397A US 5912841 A US5912841 A US 5912841A
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- coupled
- fuse circuit
- repair fuse
- flash memory
- inverting
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The present invention provides a repair fuse circuit capable of performing stable latch operation. The present invention improves the reliability of the repair fuse circuit using flash memory cells, by performing the initialization of the cross-coupled latch circuit at a high voltage level. The repair fuse circuit of a cross-coupled latch structure includes a voltage increasing element for temporally increasing voltage level of the cross-coupled latch circuit and a controller for controlling the voltage increasing element. As a result, the repair fuse circuit is initialized in a high logic state.
Description
1. Field of the Invention
The present invention relates to a repair fuse circuit and, more particularly, to a repair fuse circuit improving a latch operation using flash memory cells, by initializing a cross-coupled latch circuit in a predetermined high voltage level.
2. Description of the Related Arts
In general, a repair fuse circuit using flash memory cells has used a cross-coupled latch circuit in which the latch operation is naturally carried out by applied power voltage.
Referring now to FIG. 1A, the conventional repair fuse circuit includes two p-channel MOS transistors MP1 and MP2, two flash memory cells FC1 and FC2, n-channel MOS transistor MN1 and an inverter INT1. It should be noted that the flash memory cell FC2 consists of two flash memory cells connected in parallel.
The source of each of the p-channel MOS transistors MP1 and MP2 is commonly coupled to a power supply Vcc and the drain of p-channel MOS transistor MP1 is coupled to the drain of the flash memory cell FC1. Further, the drain of p-channel MOS transistor MP2 is coupled to the drain of the flash memory cell FC2. Accordingly, voltage from the power supply Vcc is applied to each drain of the two flash memory cells FC1 and FC2 via the p-channel MOS transistors MP1 and MP2.
In case where the flash memory cells are erased by the ultraviolet rays and the repair operation is not carried out, the amount of current flowing away through the flash memory cell FC2 may be twice as much as that through the flash memory cell FC1 because the flash memory cell FC2 consists of two memories which are connected in parallel and the flash memory FC1 consists of only one memory cell.
Accordingly, the drain of the flash memory cell FC2 is in a ground voltage level because the current flowing through the flash memory cell FC2 is passed through the n-channel MOS transistor MN1 and the drain of the flash memory cell FC1 is in a voltage level of Vcc. At this time, as shown in FIG. 1B, the gate of the n-channel transistor MN1 receives a fuse read signal FUSEREAD, As shown in FIG. 1B, at a node N2, the drain of the p-channel MOS transistor MP2, the drain of the flash memory cell FC2, the gates of the p-channel MOS transistor MP1 and the flash memory cell FC1 are connected is in a high voltage level and, at a node N1, the drain of the p-channel MOS transistor MP1, the drain of the flash memory cell FC1, the gates of the p-channel MOS transistor MP2 and the flash memory cell FC2 are connected is in a low voltage level. As a result, the output from the inverter INT1 is a fuse output signal of 0 V.
In case where the repair is carried out by programming the flash memory cell FC2, since no current flows through the flash memory cell FC2, the drain of the flash memory cell FC2 is in a high voltage level of Vcc and the drain of the flash memory cell FC1 is in a low voltage level of 0 V.
When a latch operation for the initialization may be erroneously performed in a low voltage level, the repair may be not performed. However, in this case, it appears as if the repair has been performed. That is, typically, the repair circuit is initialized in a low voltage level, but the latch operation may be erroneously performed. Although the power supply Vcc is going from low to high, this latch operation may be not corrected because the repair fuse circuit uses a cross-coupled structure.
An object of the present invention is to provide a repair fuse circuit capable of performing stable latch operation, by initializing it in a predetermined high voltage.
Another object of the present invention is to provide a repair fuse circuit of a cross-coupled latch structure used in a flash memory device.
In accordance with an aspect to the present invention, there is provided a repair fuse circuit of a cross-coupled latch circuit, wherein the repair fuse circuit has a first flash memory cell which is coupled to a first current providing means at a first node and at least two second flash memory cells which are coupled, in parallel, to a second current providing means at second node and wherein the first and second current providing means are coupled to a power supply, the repair fuse circuit comprising: a first means for precharging the first and second nodes; and a second means for generating a control signal to control the first means in order that the first means temporally precharges the first and second nodes, whereby the repair fuse circuit is initialized in a high logic state.
In accordance with another aspect to the present invention, there is provided a repair fuse circuit of a cross-coupled latch circuit, wherein the repair fuse circuit has a first flash memory cell which is coupled to a first current providing means at a first node and at least two second flash memory cells which are coupled, in parallel, to a second current providing means at second node and wherein the first and second current providing means are coupled to a power supply, the repair fuse circuit comprising: an enable delay means for increasing a voltage level in the first and second nodes, by cutting off a current path of the cross-coupled latch circuit.
In accordance with further another aspect to the present invention, there is provided a repair fuse circuit of a cross-coupled latch circuit in a flash memory device, wherein the repair fuse circuit has a flash memory cell coupled to a first current providing means at a first node and at least two flash memory cells which are coupled, in parallel, to a second current providing means at second node and wherein the first and second current providing means are coupled to a power supply, the repair fuse circuit comprising: a voltage increasing means for temporally increasing voltage level at the first and second nodes; and a control means for controlling the voltage increasing means, whereby the repair fuse circuit is initialized in a high logic state.
Other objects and aspects of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings in which:
FIG. 1A is a block diagram illustrating a conventional repair fuse circuit;
FIG. 1B is a timing diagram illustrating the conventional repair fuse circuit of FIG. 1A;
FIG. 2A is a block diagram illustrating a repair fuse circuit in accordance with an embodiment of the present invention;
FIG. 2B is a timing diagram illustrating the repair fuse circuit of FIG. 2A;
FIG. 3A is a block diagram illustrating a control signal generator used in the repair fuse circuit of FIG. 2A;
FIG. 3B is a timing diagram illustrating the control signal generator of FIG. 3A;
FIG. 4A is a block diagram illustrating a repair fuse circuit in accordance with another embodiment of the present invention; and
FIG. 4B is a timing diagram illustrating the repair fuse circuit of FIG. 4A.
Hereinafter, the present invention will be described below referring the accompanying drawings.
First, to prevent an output error from being generated by a low voltage level, the present invention increases an initialization voltage up to a predetermined voltage level when the initialization of the repair fuse circuit is required. That is, the repair fuse circuit according to the present invention is initialized at a relatively high voltage level. Although an erroneous latch operation has been caused by a low voltage level, the repair fuse circuit according to the present invention can performs a stable latch operation with the increase of the initialization voltage level.
First, the elements shown in FIG. 2A which are the same as those in FIG. lA has the same reference numerals. Referring to FIG. 2A, a repair fuse circuit 200 in accordance with an embodiment of the present invention includes the same cross-coupled latch circuit as that shown in FIG. lA. In addition, the repair fuse circuit 200 includes p-channel MOS transistors MP3 and MP4 which are respectively connected to the nodes N1 and N2. In other words, the p-channel MOS transistor MP3 has a source connected to a power supply Vcc and a drain connected to the node N1 (to which the drain of the flash memory cell FC1 is connected). Also, the p-channel MOS transistor MP4 has a source connected to a power supply Vcc and a drain connected to the node N2 (to which the drain of the flash memory cell FC2 is connected). A control signal CTR1 generated by a control signal generator is applied to the gates of the p-channel MOS transistors MP3 and MP4.
FIG. 3A is a block diagram illustrating the control signal generator providing the control signal CTR1 for the gates of the p-channel MOS transistors MP3 and MP4. The control signal generator includes a Vcc detector 20 and a pulse generator 22. Also, the pulse generator 22 includes four inverters INT3 to INT6, which are connected in series, a NAND gate NAND1 which receives the output signals from the inverters INT3 and INT6, and two inverters INT7 and INT8, which are connected in series. The inverter INT7 is connected to the output terminal of the NAND gate NAND1. Also, the pulse generator 22 includes n-channel MOS transistors MN21 and MN22 for capacitive coupling. That is, the source and drain of the n-channel MOS transistors MN21 and MN22 are coupled to the ground voltage level and the gates thereof are respectively connected to the output terminals of the inverters INT4 and INT5.
The Vcc detector 20 receiving the voltage Vcc provides to the inverter INT3 of the pulse generator 22 an output signal SIGNAL1 whose voltage is approximately 70% of the voltage Vcc. The pulse generator 22 receiving the output signal SIGNAL1 generates the control signal CTR1. As shown in FIG. 3B, the control signal CTR1 has been in a low logic state for a short time since the output signal SIGNAL1 went from a high logic state to a low logic state.
Referring again to FIG. 2A, if the control signal CTR1 is applied to the gates of the p-channel MOS transistors MP3 and MP4, the repair fuse circuit 200 is initialized again. In this initialization operation in which the flash memory cell is not programmed, the node N2 is in a high logic state when the control signal CTR1 in a low logic state is applied to the gate of the p-channel MOS transistors MP4. Also, the node N1 is in a high logic state and an output signal FUSEOUT of the repair fuse circuit 200 is continuously maintained in a low logic state. As a result, since the repair fuse circuit 200 is initialized at a high voltage which is 70% of the voltage Vcc, there is no probability of erroneous latch operation due to a low voltage level.
FIG. 4A is a block diagram illustrating a repair fuse circuit in accordance with another embodiment of the present invention and FIG. 4B is a timing diagram illustrating the repair fuse circuit of FIG. 4A.
Referring to FIGS. 4A and 4B, a control signal CTR2 for enabling the cross-coupled latch circuit is produced by the output signal SIGNAL1 from the Vcc detector 20. That is, the control signal CTR2 is generated by inverting the output signal SIGNAL1 from the Vcc detector 20 via an inverter INT2. Since the output signal SIGNAL1 is generated at 70% of the voltage Vcc, the initialization operation is carried out at a high voltage level, securing the stable latch operation.
As apparent from the above description, the present invention improves the reliability of the repair fuse circuit using flash memory cells, by performing the initialization of cross-coupled latch circuit in a high voltage level.
Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (13)
1. A repair fuse circuit of a cross-coupled latch circuit, comprising:
a first flash memory cell coupled to a first current providing means at a first node;
at least two second flash memory cells coupled, in parallel, to a second current providing means at a second node, wherein the first and second current providing means are coupled to a power supply;
a first means for precharging the first and second nodes; and
a second means for generating a control signal to control the first means in order that the first means temporally precharges the first and second nodes,
whereby the repair fuse circuit is initialized in a high logic state.
2. The repair fuse circuit in accordance with claim 1, wherein the first means for precharging the first and second nodes comprises a first pull-up transistor coupled to the first node and a second pull-up transistor coupled to the second node.
3. The repair fuse circuit in accordance with claim 1, wherein the second means for generating a control signal comprises:
a voltage detecting means for detecting whether the power supply increases up to a selected voltage level; and
a pulse generating means for receiving an output from the voltage detecting means and generating the control signal.
4. The repair fuse circuit in accordance with claim 3, wherein the pulse generating means comprises:
a plurality of first inverting means coupled in series to the voltage detecting means;
at least one capacitive coupling means coupled in parallel to the first inverting means;
an NAND logic means for NANDing outputs from two inverting means of a plurality of the first inverting mean; and
a plurality of second inverting means coupled in series the NAND logic means.
5. The repair fuse circuit in accordance with claim 4, wherein the capacitive coupling means is an n-channel MOS transistor having a gate connected to the output terminal of the first inverting means and source and drain connected to a ground voltage level.
6. A repair fuse circuit of a cross-coupled latch circuit, comprising:
a first flash memory cell coupled to a first current providing means at a first node;
at least two second flash memory cells which are coupled, in parallel, to a second current providing means at a second node, wherein the first and second current providing means are coupled to a power supply;
enable delay means for increasing a voltage level in the first and second nodes, by cutting off a current path of the cross-coupled latch circuit.
7. The repair fuse circuit in accordance with claim 6, wherein the enable delay means comprises:
a voltage detecting means for detecting whether the power supply increases up to a selected voltage level;
an inverting means for inverting an output from the voltage detecting means for providing an enable signal for the cross-coupled latch circuit.
8. A repair fuse circuit of a cross-coupled latch circuit in a flash memory device, comprising:
a flash memory cell coupled to a first current providing means at a first node;
at least two flash memory cells which are coupled, in parallel, to a second current providing means at a second node, wherein the first and second current providing means are coupled to a power supply;
a voltage increasing means for temporally increasing voltage level at the first and second nodes; and
a control means for controlling the voltage increasing means,
whereby the repair fuse circuit is initialized in a high logic state.
9. The repair fuse circuit in accordance with claim 8, wherein the voltage increasing means comprises a first pull-up transistor coupled to the first node and a second pull-up transistor coupled to the second node.
10. The repair fuse circuit in accordance with claim 8, wherein the control means comprises:
a voltage detecting means for detecting whether the power supply increases up to a selected voltage level; and
an enable delay means for increasing a voltage level in the first and second nodes, by cutting off a current path of the cross-coupled latch circuit.
11. The repair fuse circuit in accordance with claim 8, wherein the control means comprises:
a voltage detecting means for detecting whether an applied power supply increases up to a selected voltage level; and
a pulse generating means for receiving an output from the voltage detecting means and generating the control signal.
12. The repair fuse circuit in accordance with claim 11, wherein the pulse generating means comprises:
a plurality of first inverting means coupled in series to the voltage detecting means;
at least one capacitive coupling means coupled in parallel to the first inverting means;
an NAND logic means for NANDing outputs from two inverting means of a plurality of the first inverting mean; and
a plurality of second inverting means coupled in series the NAND logic means.
13. The repair fuse circuit in accordance with claim 12, wherein the capacitive coupling means is an n-channel MOS transistor having a gate connected to the output terminal of the first inverting means and source and drain connected to a ground voltage level.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR96-71406 | 1996-12-24 | ||
| KR1019960071406A KR100233283B1 (en) | 1996-12-24 | 1996-12-24 | Repair fuse initialzing circuit using a flash memory cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US5912841A true US5912841A (en) | 1999-06-15 |
Family
ID=19490685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/997,063 Expired - Lifetime US5912841A (en) | 1996-12-24 | 1997-12-23 | Repair fuse circuit performing complete latch operation using flash memory cell |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5912841A (en) |
| JP (1) | JPH10334691A (en) |
| KR (1) | KR100233283B1 (en) |
| CN (2) | CN1159724C (en) |
| GB (1) | GB2320825B (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6026037A (en) * | 1999-02-01 | 2000-02-15 | Utron Technology Inc. | Repair circuit of memory cell array |
| US6529407B2 (en) | 2000-06-14 | 2003-03-04 | Hitachi, Ltd. | Semiconductor device with improved latch arrangement |
| US6654272B2 (en) | 2001-02-27 | 2003-11-25 | Micron Technology, Inc. | Flash cell fuse circuit |
| US20040037131A1 (en) * | 2001-02-27 | 2004-02-26 | Micron Technology, Inc. | Flash cell fuse circuit |
| US20050007854A1 (en) * | 2003-07-07 | 2005-01-13 | Imondi Giuliano Gennaro | No-precharge FAMOS cell and latch circuit in a memory device |
| US20050047253A1 (en) * | 2003-08-26 | 2005-03-03 | Puri Mukesh K. | Sharing fuse blocks between memories in hard-bisr |
| US20050052201A1 (en) * | 2003-09-05 | 2005-03-10 | Impinj, Inc. A Delaware Corporation | High-voltage switches in single-well CMOS processes |
| US20050219931A1 (en) * | 2004-03-30 | 2005-10-06 | Impinj, Inc., A Delaware Corporation | Rewriteable electronic fuses |
| US20050219932A1 (en) * | 2004-03-30 | 2005-10-06 | Impinj, Inc., A Delaware Corporation | Rewriteable electronic fuses |
| US20050237840A1 (en) * | 2004-03-30 | 2005-10-27 | Impinj, Inc., A Delaware Corporation | Rewriteable electronic fuses |
| US20060062198A1 (en) * | 2004-09-17 | 2006-03-23 | Shoei-Lai Chen | Network wireless telephone system for MSN platform and method for applying the same |
| US20060284997A1 (en) * | 2005-06-10 | 2006-12-21 | Lee Dong U | Line driving circuit of semiconductor device |
| US20070263456A1 (en) * | 2005-03-17 | 2007-11-15 | Impinj, Inc. | Inverter non-volatile memory cell and array system |
| US20080136602A1 (en) * | 2005-03-31 | 2008-06-12 | Impinj, Inc. | Rfid tag with redundant non-volatile memory cell |
| US20080175050A1 (en) * | 2004-05-05 | 2008-07-24 | Alberto Pesavento | Pfet nonvolatile memory |
| US20080205150A1 (en) * | 2004-04-21 | 2008-08-28 | Impinj, Inc. | Hybrid non-volatile memory |
| US7796450B1 (en) | 2007-04-24 | 2010-09-14 | Virage Logic Corporation | Radio frequency (RFID) tag including configurable single bit/dual bits memory |
| US8122307B1 (en) | 2006-08-15 | 2012-02-21 | Synopsys, Inc. | One time programmable memory test structures and methods |
| US8139411B1 (en) | 2008-05-22 | 2012-03-20 | Synopsys, Inc. | pFET nonvolatile memory |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100485184B1 (en) * | 1997-12-12 | 2005-07-29 | 주식회사 하이닉스반도체 | Cross-Latch Circuit Using Flash Memory Cells |
| KR100451421B1 (en) * | 1997-12-29 | 2004-12-17 | 주식회사 하이닉스반도체 | Power supply voltage regulation circuit, especially including constant voltage source and voltage divider |
| KR100630977B1 (en) * | 2000-02-18 | 2006-10-04 | 매그나칩 반도체 유한회사 | Power on reset circuit |
| JP5160164B2 (en) * | 2007-08-06 | 2013-03-13 | ルネサスエレクトロニクス株式会社 | Fuse circuit |
| CN106248582B (en) | 2011-01-21 | 2020-10-20 | 拉布拉多诊断有限责任公司 | System and method for maximizing sample usage |
| KR101890820B1 (en) * | 2012-04-30 | 2018-08-22 | 에스케이하이닉스 주식회사 | Semiconductor integrated circuit having array e-fuse and driving method thereof |
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- 1996-12-24 KR KR1019960071406A patent/KR100233283B1/en not_active IP Right Cessation
-
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- 1997-12-24 JP JP9366431A patent/JPH10334691A/en active Pending
- 1997-12-24 GB GB9727403A patent/GB2320825B/en not_active Expired - Fee Related
- 1997-12-24 CN CNB971208298A patent/CN1159724C/en not_active Expired - Fee Related
- 1997-12-24 CN CNA031587593A patent/CN1505049A/en active Pending
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Cited By (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6026037A (en) * | 1999-02-01 | 2000-02-15 | Utron Technology Inc. | Repair circuit of memory cell array |
| US6724657B2 (en) | 2000-06-14 | 2004-04-20 | Renesas Technology Corp. | Semiconductor device with improved latch arrangement |
| US6529407B2 (en) | 2000-06-14 | 2003-03-04 | Hitachi, Ltd. | Semiconductor device with improved latch arrangement |
| US20030067822A1 (en) * | 2000-06-14 | 2003-04-10 | Shoji Shukuri | Semiconductor device with improved latch arrangement |
| US6845029B2 (en) | 2001-02-27 | 2005-01-18 | Micron Technology, Inc. | Flash cell fuse circuit |
| US7277311B2 (en) | 2001-02-27 | 2007-10-02 | Micron Technology, Inc. | Flash cell fuse circuit |
| US20040037131A1 (en) * | 2001-02-27 | 2004-02-26 | Micron Technology, Inc. | Flash cell fuse circuit |
| US7002828B2 (en) | 2001-02-27 | 2006-02-21 | Micron Technology, Inc. | Flash cell fuse circuit |
| US20060083061A1 (en) * | 2001-02-27 | 2006-04-20 | Goiovanni Santin | Flash cell fuse circuit |
| US20040052121A1 (en) * | 2001-02-27 | 2004-03-18 | Micron Technology, Inc. | Flash cell fuse circuit |
| US6654272B2 (en) | 2001-02-27 | 2003-11-25 | Micron Technology, Inc. | Flash cell fuse circuit |
| US7154800B2 (en) | 2003-07-07 | 2006-12-26 | Micron Technology, Inc. | No-precharge FAMOS cell and latch circuit in a memory device |
| US7263022B2 (en) | 2003-07-07 | 2007-08-28 | Micron Technology, Inc. | No-precharge FAMOS cell and latch circuit in a memory device |
| US6967889B2 (en) * | 2003-07-07 | 2005-11-22 | Micron Technology, Inc. | No-precharge FAMOS cell and latch circuit in a memory device |
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Also Published As
| Publication number | Publication date |
|---|---|
| GB2320825B (en) | 2000-12-13 |
| CN1192567A (en) | 1998-09-09 |
| JPH10334691A (en) | 1998-12-18 |
| KR19980052418A (en) | 1998-09-25 |
| CN1159724C (en) | 2004-07-28 |
| GB9727403D0 (en) | 1998-02-25 |
| GB2320825A (en) | 1998-07-01 |
| KR100233283B1 (en) | 1999-12-01 |
| CN1505049A (en) | 2004-06-16 |
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