KR100451421B1 - Power supply voltage regulation circuit, especially including constant voltage source and voltage divider - Google Patents

Abstract

PURPOSE: A power supply voltage regulation circuit is provided to prevent operation error of a memory device and thus to improve reliability and yield of the device. CONSTITUTION: The power supply voltage regulation circuit includes a constant voltage source(11) generating a constant voltage according to a power supply voltage and a pulse signal being output from a circuit detecting a level of the power supply voltage. The power supply voltage regulation circuit also includes a voltage divider(12) to divide a voltage being output from the constant voltage source. According to the constant voltage source, the first PMOS transistor(P11) is connected between the power supply voltage and the second node. The second PMOS transistor(P12) is connected between the power supply voltage and the first node(K11). The first NMOS transistor(N13) is connected between the second node(K12) and a ground. The second NMOS transistor has a drain connected to the first node and a gate connected to the second node. A resistor is connected between a source of the second NMOS transistor and the ground. A capacitor is connected between the first node and the second node. And an inverter(14) receives the pulse signal. And the third PMOS transistor(P13) is connected between the first node and the second node in parallel with the capacitor.

Description

Supply Voltage Regulation Circuit

The present invention relates to a power supply voltage regulation circuit, and more particularly, to a power supply voltage regulation circuit for generating a constant voltage in accordance with a constant voltage supplied from a constant voltage source.

In general, a memory device using a CMOS structure uses a voltage of about 10 percent (%) of the power supply voltage (Vcc) as an operating voltage of the power supply voltage. That is, when the power supply voltage is 5V, 4.5V to 5.5V are used as the operating voltage of the power supply voltage. In this case, the difference between the power supply voltage in the low state and the power supply voltage in the high state becomes 1V. In a memory device using CMOS, a power supply voltage (Vcc) regulation circuit is used to compensate for the voltage difference.

1 is a circuit diagram of a conventional power supply voltage regulation circuit.

When a power supply voltage is applied to the memory device, the voltage of the first node K1 of the constant voltage source 1 is slightly lower than the voltage obtained by subtracting the threshold voltage of the first or second PMOS transistor P1 or P2 from the power supply voltage Vcc. The voltage Vcc- (Vtp + α) is maintained. In addition, the voltage of the second node K2 is slightly higher than the threshold voltage of the first or second NMOS transistor N1 or N2 by the first and second PMOS transistors P1 and P2 and the capacitor C1. Vtn + α). That is, the voltages of the first and second nodes K1 and K2 are turned off by the first and second PMOS transistors P1 and P2 and the first and second NMOS transistors N1 and N2. It maintains constant voltage so that it is not off).

Meanwhile, the voltage of the first node K1 is supplied to the input of the third PMOS transistor P3 of the voltage divider 2. In this case, the third PMOS transistor P3 is weakly turned on. When the third PMOS transistor P3 is turned on, the PMOS transistors D1 to D4 of the diode chain 3 and the power supply voltage Vcc are input to the ground terminal Vss through the third NMOS transistor N3. A current pass is formed. At this time, the output voltage Vreg of the power supply voltage regulation circuit maintains a voltage stabilized above a certain voltage by the PMOS transistors D1 to D4 of the diode chain 3.

For example, assuming that a threshold voltage of each of the PMOS transistors D1 to D4 of the diode chain 3 is about 1 V, since four PMOS transistors are connected to the diode chain 3, the output voltage Vreg Maintains a 4V voltage. Therefore, even if the power supply voltage is increased above the 4V voltage, the output voltage Vreg can always maintain the 4V voltage.

However, even when the power supply voltage is applied, the first and second nodes K1 and K2 may remain floating and thus may not be maintained at a desired voltage level. That is, the first and second PMOS transistors P1 and P2 and the first and second NMOS transistors N1 and N2 are both turned off to maintain the voltage of Vcc-Vtp + α at the first node K1. In addition, the voltage of Vtn-α is maintained at the second node K2, so that the third PMOS transistor P3 which inputs the first node K1 is turned off. When the third PMOS transistor P3 is turned off, the current path is blocked so that the diode chain 3 is floated, the output Vreg node is also floated, and the output voltage Vreg is low. As a result, the entire memory device malfunctions, thereby degrading reliability and yield of the device.

Therefore, the present invention can prevent the malfunction of the memory device by initializing the power supply voltage regulation circuit to a stable voltage above a certain voltage by using the output voltage of the circuit capable of detecting a voltage of about 70 percent of the power supply voltage. The purpose is to provide a supply voltage regulation circuit that can improve the reliability and yield of the device.

The power supply voltage regulation circuit according to the present invention for achieving the above object is a constant voltage source for generating a constant voltage in accordance with the power supply voltage and the pulse signal output from the circuit for detecting the level of the power supply voltage, and is output from the constant voltage source And a voltage divider for distributing voltage. The constant voltage source according to the first embodiment of the present invention is connected between a power supply voltage and a second node, a first PMOS transistor having a gate terminal connected to the first node, and between the power supply voltage and the first node. A second PMOS transistor having a gate terminal connected to the first node, a first NMOS transistor connected between the second node and ground and a gate terminal connected to the second node, and a drain terminal connected to the first node And a second NMOS transistor having a gate terminal connected to the second node, a resistor connected between a source terminal and ground of the second NMOS transistor, a capacitor connected between the first and second nodes, and the pulse signal. A third PMOS transistor connected in parallel with the capacitor between the input inverter and the first and second nodes and having a gate terminal connected to the output terminal of the inverter; And a first PMOS transistor connected between a power supply voltage and a second node, a gate terminal of which is connected to the first node, and the power supply. A second PMOS transistor connected between a voltage and the first node and having a gate terminal connected to the first node, a first NMOS transistor connected between the second node and ground and having a gate terminal connected to the second node; A second NMOS transistor having a drain terminal connected to the first node and a gate terminal connected to the second node, a resistor connected between a source terminal and ground of the second NMOS transistor, and between the first and second nodes; A connected capacitor, an inverter receiving the pulse signal, a power supply voltage and a second node, and a gate terminal connected to an output terminal of the inverter And a third PMOS transistor. The constant voltage source according to the third embodiment of the present invention is connected between a power supply voltage and a second node, a first PMOS transistor having a gate terminal connected to the first node, and between the power supply voltage and the first node. A second PMOS transistor having a gate terminal connected to the first node, a first NMOS transistor connected between the second node and ground and a gate terminal connected to the second node, and a drain terminal connected to the first node And a second NMOS transistor having a gate terminal connected to the second node, a resistor connected between a source terminal and ground of the second NMOS transistor, a capacitor connected between the first and second nodes, and the pulse signal. And a third NMOS transistor connected between the input inverter and the first node and the ground, and the gate terminal of which is connected to the output terminal of the inverter. The constant voltage source according to the fourth embodiment of the present invention includes a first PMOS transistor connected between a power supply voltage and a second node and a gate terminal connected to the first node, and the power supply voltage and the first voltage source. A second PMOS transistor connected between one node and a gate terminal connected to the first node, a first NMOS transistor connected between the second node and ground and a gate terminal connected to the second node, and the first node A second NMOS transistor having a drain terminal connected thereto and a gate terminal connected to the second node, a resistor connected between a source terminal of the second NMOS transistor and a ground, and a first connected between the first and second nodes. And a second capacitor connected between the capacitor and the first node and the pulse signal input terminal. In addition, the constant voltage source according to the fifth embodiment of the present invention is connected between a power supply voltage and a second node and a first PMOS transistor having a gate terminal connected to the first node, and between the power supply voltage and the first node. A second PMOS transistor having a gate terminal connected to the first node, a first NMOS transistor connected between the second node and ground and a gate terminal connected to the second node, and a drain terminal connected to the first node And a second NMOS transistor having a gate terminal connected to the second node, a resistor connected between a source terminal and ground of the second NMOS transistor, a first capacitor connected between the first and second nodes, and the pulse. And a second capacitor connected between the inverter receiving the signal and the output terminal of the second node and the inverter.

1 is a conventional power supply voltage regulation circuit diagram.

2 to 6 are power supply voltage regulation circuit diagrams of the present invention according to each embodiment.

<Description of the symbols for the main parts of the drawings>

P11 and P12: first and second PMOS transistors

N13 and N14: first and second NMOS transistors

P13: third PMOS transistor P14: fourth PMOS transistor

P24: fifth PMOS transistor N24: fourth NMOS transistor

C21, C22: capacitor

11: constant voltage source 12: voltage divider

13: diode chain 14: inverter

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a power supply voltage regulation circuit diagram according to a first embodiment of the present invention.

When a power supply voltage is applied, the first and second PMOS transistors P11 and P12 and the first and second NMOS transistors N11 and N12 of the constant voltage source 11 may be used for normal operation of the power supply voltage regulation circuit. ) Are all turned on. That is, all four transistors are initially turned on. To this end, in the present invention, the fourth PMOS transistor P14 that inputs a pulse signal (hereinafter referred to as LVcc voltage) output from a circuit for detecting a power supply voltage level of about 70 percent (%) through the inverter 14. Is connected between the first and second nodes K11 and K12 of the constant voltage source 11. That is, the fourth PMOS transistor P14 is turned on according to the LVcc voltage supplied through the inverter 14 to connect the first node k11 and the second node K12 of the constant voltage source 11. . At this time, the capacitor C11 is shorted by the fourth PMOS transistor P14. Therefore, when a power supply voltage is applied, the first node K11 and the second node K12 are maintained at the same level. That is, while the LVcc voltage is kept high, the first and second PMOS transistors P11 and P12 and the first and second NMOS transistors N11 and N12 are turned on. In addition, the third PMOS transistor P13 of the voltage divider 12 that receives the first node K11 is turned on. Accordingly, a current path is formed to the ground terminal Vss through the PMOS transistors D11 to D14 of the diode chain 13 and the third NMOS transistor N13 which receives the power supply voltage Vcc. At this time, the output voltage Vreg of the power supply voltage regulation circuit is initialized to a voltage stabilized above a certain voltage by the PMOS transistors D11 to D14 of the diode chain 13.

3 is a circuit diagram illustrating a power supply voltage regulation according to a second embodiment of the present invention.

In the power supply voltage regulation circuit of FIG. 2, the power supply terminal Vcc and the second PMOS transistor P24 that inputs an LVcc voltage through the inverter 14 instead of the fourth PMOS transistor P14 is input. The connection is made between the nodes K12. This is because when the fifth PMOS transistor P24 is turned on according to the LVcc voltage, the second node K12 becomes high and the first node K11 via the capacitor C11 becomes low. . That is, the fifth PMOS transistor P24 maintains the voltage of the second node K12 at the power supply voltage Vcc while the LVcc voltage is maintained at a high state, so that the first and second PMOS transistors P11 and P12 and both of the first and second NMOS transistors N11 and N12 are turned on. In addition, the third PMOS transistor P13 of the voltage divider 12 that receives the first node K11 is turned on. Accordingly, a current path is formed to the ground terminal Vss through the PMOS transistors D11 to D14 of the diode chain 13 and the third NMOS transistor N13 which receives the power supply voltage Vcc. At this time, the output voltage Vreg of the power supply voltage regulation circuit is initialized to a voltage stabilized above a certain voltage by the PMOS transistors D11 to D14 of the diode chain 13.

4 is a circuit diagram illustrating a power supply voltage regulation according to a third embodiment of the present invention.

In the power supply voltage regulation circuit of FIG. 3, a fourth NMOS transistor N24 that inputs an LVcc voltage through the inverter 14 instead of the fourth PMOS transistor P14 is connected to a first node of the constant voltage source 11. A connection is made between K11 and the ground terminal Vss. This is because when the fourth NMOS transistor N24 is turned on according to the LVcc voltage, the first node K11 goes low, and the second node K12 via the capacitor C11 goes high. . That is, the fourth NMOS transistor N24 maintains the voltage of the first node K11 at the ground voltage Vss while the LVcc voltage maintains the high state such that the first and second PMOS transistors P11 and P12 and both of the first and second NMOS transistors N11 and N12 are turned on. In addition, the third PMOS transistor P13 of the voltage divider 12 that receives the first node K11 is turned on. Accordingly, a current path is formed to the ground terminal Vss through the PMOS transistors D11 to D14 of the diode chain 13 and the third NMOS transistor N13 which receives the power supply voltage Vcc. At this time, the output voltage Vreg of the power supply voltage regulation circuit is initialized to a voltage stabilized above a certain voltage by the PMOS transistors D11 to D14 of the diode chain 13.

5 is a circuit diagram illustrating a power supply voltage regulation according to a fourth embodiment of the present invention.

In the power supply voltage regulation circuit of FIG. 2, instead of the fourth PMOS transistor P14, a capacitor C21 that inputs the LVcc voltage is connected to the first node K11 of the constant voltage source 11. This is because when the LVcc voltage becomes low by negative pumping by the LVcc voltage, the first node K11 is coupled to the low state and the first via the capacitor C11. The two nodes K12 go high. That is, the capacitor C21 maintains the voltage of the first node K11 in the low state of the ground voltage Vss while the LVcc voltage maintains the low state, so that the first and second PMOS transistors P11 and P12 is turned on, and then both the first and second NMOS transistors N11 and N12 are turned on. In addition, the third PMOS transistor P13 of the voltage divider 12 that receives the first node K11 is turned on. Accordingly, a current path is formed to the ground terminal Vss through the PMOS transistors D11 to D14 of the diode chain 13 and the third NMOS transistor N13 which receives the power supply voltage Vcc. At this time, the output voltage Vreg of the power supply voltage regulation circuit is initialized to a voltage stabilized above a certain voltage by the PMOS transistors D11 to D14 of the diode chain 13.

6 is a circuit diagram illustrating a power supply voltage regulation according to a fifth embodiment of the present invention.

In the power supply voltage regulation circuit of FIG. 2, a capacitor C22 that inputs an LVcc voltage through the inverter 12 instead of the fourth PMOS transistor P14 is connected to the first node K11 of the constant voltage source 11. You will be connected to This is because when the LVcc voltage becomes low due to negative pumping by the LVcc voltage, the second node K12 is coupled to the high state and the second via the capacitor C11. The node K12 goes high. That is, the capacitor C22 holds the first and second PMOS transistors P11 and P12 by keeping the voltage of the second node K12 at the power supply voltage Vcc while the LVcc voltage is kept low. After that, the first and second NMOS transistors N11 and N12 are turned on. In addition, the third PMOS transistor P13 of the voltage divider 12 that receives the first node K11 is turned on. Accordingly, a current path is formed to the ground terminal Vss through the PMOS transistors D11 to D14 of the diode chain 13 and the third NMOS transistor N13 which receives the power supply voltage Vcc. At this time, the output voltage Vreg of the power supply voltage regulation circuit is initialized to a voltage stabilized above a certain voltage by the PMOS transistors D11 to D14 of the diode chain 13.

As described above, according to the present invention, the output node of the regulation circuit is prevented from floating by using a pulse signal output from a circuit capable of detecting a power supply voltage level of about 70 percent, thereby preventing malfunction of the entire memory device. This can be an excellent effect that can improve the reliability and yield of the device.

Claims (6)

A constant voltage source generating a constant voltage according to a power supply voltage and a pulse signal output from a circuit for detecting the level of the power supply voltage; And a voltage divider for distributing the voltage output from the constant voltage source. The semiconductor device of claim 1, wherein the constant voltage source comprises: a first PMOS transistor connected between a power supply voltage and a second node, the gate terminal of which is connected to the first node; A second PMOS transistor connected between the power supply voltage and the first node and having a gate terminal connected to the first node; A first NMOS transistor connected between the second node and ground and whose gate terminal is connected to the second node; A second NMOS transistor having a drain terminal connected to the first node and a gate terminal connected to the second node; A resistor connected between the source terminal of the second NMOS transistor and ground; A capacitor connected between the first and second nodes, An inverter receiving the pulse signal; And a third PMOS transistor connected in parallel with the capacitor between the first and second nodes and having a gate terminal connected to an output terminal of the inverter. The semiconductor device of claim 1, wherein the constant voltage source comprises: a first PMOS transistor connected between a power supply voltage and a second node, the gate terminal of which is connected to the first node; A second PMOS transistor connected between the power supply voltage and the first node and having a gate terminal connected to the first node; A first NMOS transistor connected between the second node and ground and whose gate terminal is connected to the second node; A second NMOS transistor having a drain terminal connected to the first node and a gate terminal connected to the second node; A resistor connected between the source terminal of the second NMOS transistor and ground; A capacitor connected between the first and second nodes, An inverter receiving the pulse signal; And a third PMOS transistor connected between the power supply voltage and the second node and having a gate terminal connected to the output terminal of the inverter. The semiconductor device of claim 1, wherein the constant voltage source comprises: a first PMOS transistor connected between a power supply voltage and a second node, the gate terminal of which is connected to the first node; A second PMOS transistor connected between the power supply voltage and the first node and having a gate terminal connected to the first node; A first NMOS transistor connected between the second node and ground and whose gate terminal is connected to the second node; A second NMOS transistor having a drain terminal connected to the first node and a gate terminal connected to the second node; A resistor connected between the source terminal of the second NMOS transistor and ground; A capacitor connected between the first and second nodes, An inverter receiving the pulse signal; And a third NMOS transistor connected between the first node and ground and whose gate terminal is connected to an output terminal of the inverter. The semiconductor device of claim 1, wherein the constant voltage source comprises: a first PMOS transistor connected between a power supply voltage and a second node, the gate terminal of which is connected to the first node; A second PMOS transistor connected between the power supply voltage and the first node and having a gate terminal connected to the first node; A first NMOS transistor connected between the second node and ground and whose gate terminal is connected to the second node; A second NMOS transistor having a drain terminal connected to the first node and a gate terminal connected to the second node; A resistor connected between the source terminal of the second NMOS transistor and ground; A first capacitor connected between the first and second nodes, And a second capacitor connected between the first node and the pulse signal input terminal. The semiconductor device of claim 1, wherein the constant voltage source comprises: a first PMOS transistor connected between a power supply voltage and a second node, the gate terminal of which is connected to the first node; A second PMOS transistor connected between the power supply voltage and the first node and having a gate terminal connected to the first node; A first NMOS transistor connected between the second node and ground and whose gate terminal is connected to the second node; A second NMOS transistor having a drain terminal connected to the first node and a gate terminal connected to the second node; A resistor connected between the source terminal of the second NMOS transistor and ground; A first capacitor connected between the first and second nodes, An inverter receiving the pulse signal; And a second capacitor connected between the second node and an output terminal of the inverter.

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