US5882950A - Fabrication method for horizontal direction semiconductor PN junction array - Google Patents

Fabrication method for horizontal direction semiconductor PN junction array Download PDF

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US5882950A
US5882950A US08/773,185 US77318596A US5882950A US 5882950 A US5882950 A US 5882950A US 77318596 A US77318596 A US 77318596A US 5882950 A US5882950 A US 5882950A
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epitaxial layer
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Suk-Ki Min
Seong-Il Kim
Eun Kyu Kim
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Korea Advanced Institute of Science and Technology KAIST
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/042—Doping, graded, for tapered etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/056—Gallium arsenide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/168—V-Grooves
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/912—Displacing pn junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/915—Amphoteric doping

Definitions

  • the present invention relates to a fabrication method for a semiconductor memory device, and in particular, to an improved fabrication method of a level semiconductor PN junction array which allows a significant increase of growth in the horizontal direction so that a PN junction array structure can formed by introduction or doping of a CCl 4 or CBr 4 gas when a GaAs or AlGaAs epitaxial layer is grown on a GaAs substrate having a V-shaped or U-shaped recess by metalorganic chemical vapor deposition (hereinafter, called MOCVD).
  • MOCVD metalorganic chemical vapor deposition
  • a three dimensional epitaxial layer can be desirably embodied by putting a test piece in a reaction tube one time without going through a complicated fabrication process for a semiconductor device.
  • the improved fabrication method for a horizontal direction PN junction array is characterized in that a P type GaAs or P type AlGaAs is grown only in the V-shaped or U-shaped recess by introducing (or doping) a small amount of a CCl 4 or CBr 4 gas when a GaAs or AlGaAs epitaxial layer is grown on a GaAs substrate having a V-shaped or U-shaped type recess formed thereon.
  • the method according the present invention is applied to increase the efficiency of photoelectro devices such as a photodetector or is used for a solar cell or fabricating a low threshold current laser diode or an optical wave guide.
  • FIGS. 1A through 1C are schematic views showing a construction of a horizontal direction PN junction array according to the present invention, wherein FIG. 1A is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on a semi-insulated GaAs substrate, FIG. 1B is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on an N type GaAs substrate, and FIG. 1C is a view showing the construction in which a P type GaAs or P type AlGaAs array is implanted in the N type GaAs substrate;
  • FIGS. 2A and 2B are cross-sectional views showing an epitaxial layer in a construction of the horizontal direction PN junction array fabricated by introducing CBr 4 in the growth of a GaAs epitaxial layer on an array of a V-shaped recess according to the present invention, wherein FIG. 2A is a photograph of the epitaxial layer viewed through a scanning electronic microscope (hereinafter, called SEM) and FIG. 2B is a schematic view of FIG. 2A; and
  • SEM scanning electronic microscope
  • FIGS. 3A and 3B are SEM photographs of a cross-sectional epitaxial layer according to the present invention and the conventional art , wherein FIG. 3A is the SEM photograph of the cross-sectional GaAs epitaxial layer grown on the structure of the V-shaped recess array by introducing CCl 4 gas at 0.03 cc/min according to the present invention, and FIG. 3B is the SEM photograph of the cross-sectional epitaxial layer grown according to the conventional art to be compared with FIG. 3A.
  • a CCl 4 or CBr 4 gas is introduced by a MOCVD method for the growth of a GaAs epitaxial layer.
  • hydrogen having a high degree of purity is used as a carrier gas and total introduced amount of the gas is 5 liters per minute.
  • trimethylgallium (TMG) and trimethylaluminium (TMA) are used as a material for an organometal of group I and an arsine gas (AsH 3 ) as a material for an organometal of group V.
  • FIGS. 1A through 1C are schematic views showing constructions of a level semiconductor PN junction array according to the present invention, wherein FIG. 1A is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on a semi-insulated GaAs substrate, FIG. 1B is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on an N type GaAs substrate, and FIG. 1C is a view showing a construction in which a P type GaAs or P type AlGaAs array is implanted in the N type GaAs substrate.
  • the horizontal growth rate can be controlled by adjusting the introducing rate or changing the growth temperature of the CCl 4 or CBr 4 gas.
  • FIGS. 2A and 2B are cross-sectional view showing an epitaxial layer in a construction of the horizontal direction PN junction array fabricated by the introduction of CBr 4 in the growth of a GaAs epitaxial layer on an array of a V-shaped recess, wherein FIG. 2A is an SEM photograph of the epitaxial layer and FIG. 2B is a schematic view of FIG. 2A.
  • an N type GaAs is used as a substrate and a P type GaAs as a newly grown epitaxial layer filling the V-shaped recess.
  • a black line in FIG. 2A is an AlGaAs layer (marker layer) grown for effectively observing the growth of the GaAs epitaxial layer.
  • the intervals between the PN junction arrays can be controlled by the mask used in etching the substrate before the growth of the epitaxial layer, and the shape or height of the P type GaAs filling the V-shaped recess can be adjusted by changing the growth conditions of the MOCVD method, as described above.
  • FIG. 3A is an SEM photograph of the cross-sectional GaAs epitaxial layer grown on the construction of the V-shaped recess array by introducing CCl 4 gas at 0.03 cc/min by the MOCVD method, and the black line in FIG. 3A indicates an AlGaAs layer (marker layer) grown for effectively observing the growth of the GaAs epitaxial layer, and a complete planarization is realized from the first layer of the V-shaped recess.
  • FIG. 3B is the SEM photograph of the cross-sectional epitaxial layer grown without the introduction of a CCl 4 gas to be compared with FIG. 3A, according to the conventional art, wherein a planarization is not achieved at all even after several layers are grown and remains the V-shaped recess.
  • a P type GaAs or P type AlGaAs is formed only in the V-shaped or U-shaped recess by introducing (or doping) a CCl 4 or CBr 4 gas, resulting in the formation of the horizontal direction PN junction array. Accordingly, a PN junction portion exists on the surface and consequently an incident light reaches the PN junction portion without any loss. Therefore, the method according to the present invention is applied to increasing the efficiency of such a photoelectro device as a photodetector or a solar cell or fabricating a low threshold current laser diode or an optical wave guide.

Abstract

A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl4 or CBr4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl4 or CBr4 .

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor memory device, and in particular, to an improved fabrication method of a level semiconductor PN junction array which allows a significant increase of growth in the horizontal direction so that a PN junction array structure can formed by introduction or doping of a CCl4 or CBr4 gas when a GaAs or AlGaAs epitaxial layer is grown on a GaAs substrate having a V-shaped or U-shaped recess by metalorganic chemical vapor deposition (hereinafter, called MOCVD).
2. Description of the Prior Art
Recently, studies on the fabrication of photoelectro devices on the basis of a chemical composition semiconductor are being conducted, and such photoelectro devices fabrication requires a complicated process.
If a selective epitaxy technology which has been recently studied as one of the MOCVD methods is employed, a three dimensional epitaxial layer can be desirably embodied by putting a test piece in a reaction tube one time without going through a complicated fabrication process for a semiconductor device. As a result, since the complicated construction of a semiconductor device is formed during the growth of a epitaxial layer without being exposed to air during the process, a default and damage on junction boundary surfaces as well as undesired oxidation of the surface of the epitaxial layer can be effectively prevented.
However, in fabricating a photoelectro device for a chemical composition semiconductor according to the conventional art in which the epitaxial layer is formed by the MOCVD method, a horizontal direction PN junction cannot be realized, and therefore, in semiconductor devices using light, the PN junction exists within the semiconductor device, and the light is absorbed into the epitaxial layer before it reaches a PN junction layer, resulting in a large optical loss.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved fabrication method for a horizontal direction PN junction array which is carried out by forming a V-shaped or U-shaped recess on a substrate by using a non-planar growth which is one of the selective epitaxial growth mechanisms and performing an epitaxial layer growth thereon.
To achieve the above object, the improved fabrication method for a horizontal direction PN junction array is characterized in that a P type GaAs or P type AlGaAs is grown only in the V-shaped or U-shaped recess by introducing (or doping) a small amount of a CCl4 or CBr4 gas when a GaAs or AlGaAs epitaxial layer is grown on a GaAs substrate having a V-shaped or U-shaped type recess formed thereon.
When the horizontal direction PN junction array according to the present invention is fabricated using the above-described method, a PN junction portion exists on the surface and consequently an incident light reaches the PN junction portion without any loss. Therefore, the method according the present invention is applied to increase the efficiency of photoelectro devices such as a photodetector or is used for a solar cell or fabricating a low threshold current laser diode or an optical wave guide.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, wherein:
FIGS. 1A through 1C are schematic views showing a construction of a horizontal direction PN junction array according to the present invention, wherein FIG. 1A is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on a semi-insulated GaAs substrate, FIG. 1B is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on an N type GaAs substrate, and FIG. 1C is a view showing the construction in which a P type GaAs or P type AlGaAs array is implanted in the N type GaAs substrate;
FIGS. 2A and 2B are cross-sectional views showing an epitaxial layer in a construction of the horizontal direction PN junction array fabricated by introducing CBr4 in the growth of a GaAs epitaxial layer on an array of a V-shaped recess according to the present invention, wherein FIG. 2A is a photograph of the epitaxial layer viewed through a scanning electronic microscope (hereinafter, called SEM) and FIG. 2B is a schematic view of FIG. 2A; and
FIGS. 3A and 3B are SEM photographs of a cross-sectional epitaxial layer according to the present invention and the conventional art , wherein FIG. 3A is the SEM photograph of the cross-sectional GaAs epitaxial layer grown on the structure of the V-shaped recess array by introducing CCl4 gas at 0.03 cc/min according to the present invention, and FIG. 3B is the SEM photograph of the cross-sectional epitaxial layer grown according to the conventional art to be compared with FIG. 3A.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The fabrication method for a horizontal direction semiconductor PN junction array according to the present invention will now be described in detail referring to the accompanying drawings.
First, after a test piece on which an N type GaAs epitaxial layer having a thickness of 2˜3 μm is grown or an N type GaAs substrate is formed on a semi-insulated GaAs substrate in the 100! direction, only a portion to be etched is exposed by photolithography, using a photoresist and a photomask, and then a wet etching is performed in the direction of 001! at a predetermined rate using H2 SO4 : H2 O2 : H2 O to form a V-shaped or U-shaped recess. Here, if the width of an etched portion is adjusted, the intervals between the horizontal direction PN junction arrays can be also controlled. Then, on a test piece having the V-shaped or U-shaped recess formed thereon, a CCl4 or CBr4 gas is introduced by a MOCVD method for the growth of a GaAs epitaxial layer. During the growth by the MOCVD method, hydrogen having a high degree of purity is used as a carrier gas and total introduced amount of the gas is 5 liters per minute. In addition, trimethylgallium (TMG) and trimethylaluminium (TMA) are used as a material for an organometal of group I and an arsine gas (AsH3) as a material for an organometal of group V.
FIGS. 1A through 1C are schematic views showing constructions of a level semiconductor PN junction array according to the present invention, wherein FIG. 1A is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on a semi-insulated GaAs substrate, FIG. 1B is a view showing a construction of a P-GaAs/N-GaAs or P-AlGaAs/N-GaAs PN junction array formed on an N type GaAs substrate, and FIG. 1C is a view showing a construction in which a P type GaAs or P type AlGaAs array is implanted in the N type GaAs substrate.
As described above, when the CCl4 or CBr4 gas is introduced (or doped) in growing the epitaxial layer by the MOCVD method on the GaAs substrate having the V-shaped or U-shaped recess formed thereon, a horizontal growth rate is remarkably increased, and since the carbon (C) introduced here serves as a P type dopant, the resultant becomes a P type GaAs or P type AlGaAs, resulting in the construction of the horizontal direction PN junction array. Here, the horizontal growth rate can be controlled by adjusting the introducing rate or changing the growth temperature of the CCl4 or CBr4 gas.
FIGS. 2A and 2B are cross-sectional view showing an epitaxial layer in a construction of the horizontal direction PN junction array fabricated by the introduction of CBr4 in the growth of a GaAs epitaxial layer on an array of a V-shaped recess, wherein FIG. 2A is an SEM photograph of the epitaxial layer and FIG. 2B is a schematic view of FIG. 2A. Here, an N type GaAs is used as a substrate and a P type GaAs as a newly grown epitaxial layer filling the V-shaped recess. A black line in FIG. 2A is an AlGaAs layer (marker layer) grown for effectively observing the growth of the GaAs epitaxial layer. Meanwhile, the intervals between the PN junction arrays can be controlled by the mask used in etching the substrate before the growth of the epitaxial layer, and the shape or height of the P type GaAs filling the V-shaped recess can be adjusted by changing the growth conditions of the MOCVD method, as described above.
FIG. 3A is an SEM photograph of the cross-sectional GaAs epitaxial layer grown on the construction of the V-shaped recess array by introducing CCl4 gas at 0.03 cc/min by the MOCVD method, and the black line in FIG. 3A indicates an AlGaAs layer (marker layer) grown for effectively observing the growth of the GaAs epitaxial layer, and a complete planarization is realized from the first layer of the V-shaped recess. FIG. 3B is the SEM photograph of the cross-sectional epitaxial layer grown without the introduction of a CCl4 gas to be compared with FIG. 3A, according to the conventional art, wherein a planarization is not achieved at all even after several layers are grown and remains the V-shaped recess.
As described above in detail, when a GaAs or AlGaAs epitaxial layer is grown using an N type GaAs substrate having a V-shaped or U-shaped recess, a P type GaAs or P type AlGaAs is formed only in the V-shaped or U-shaped recess by introducing (or doping) a CCl4 or CBr4 gas, resulting in the formation of the horizontal direction PN junction array. Accordingly, a PN junction portion exists on the surface and consequently an incident light reaches the PN junction portion without any loss. Therefore, the method according to the present invention is applied to increasing the efficiency of such a photoelectro device as a photodetector or a solar cell or fabricating a low threshold current laser diode or an optical wave guide.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.

Claims (8)

What is claimed is:
1. A fabrication method for a horizontal direction PN junction array, comprising:
forming a recess on an N type GaAs substrate by non-planar growth;
growing a P type epitaxial layer on the N type GaAs substrate by metalorganic chemical vapor deposition to form a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AIGaAs/N-GaAs by introducing a gas of CCl4 or CBr4.
2. The method of claim 1, wherein the recess on the N type GaAs substrate is formed as a V-shaped or U-shaped pattern.
3. The method of claim 2, wherein the recess on the N type GaAs substrate is formed as a V-shaped or U-shaped pattern by a photolithography using a photomask, and etched by wet etching to form the V-shaped or U-shaped recess.
4. The method of claim 3, wherein the wet etching is carried out using H2 SO4 :H2 O2 :H2 O.
5. The method of claim 1, wherein a P type GaAs or a P type AlGaAs epitaxial layer is formed only in the recess of the N type GaAs substrate.
6. The method of claim 2, wherein a P type GaAs or a P type AlGaAs epitaxial layer is formed only in the recess of the N type GaAs substrate.
7. The method of claim 1 wherein the GaAs substrate is in the (100) direction.
8. The method of claim 3 wherein the etching is performed in the (001) direction.
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KR101133412B1 (en) 2009-07-24 2012-04-09 한양대학교 산학협력단 Light Emitting Diode formed on Substrate having Trench

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