US5774706A - High speed PCI bus utilizing TTL compatible signaling - Google Patents

High speed PCI bus utilizing TTL compatible signaling Download PDF

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Publication number
US5774706A
US5774706A US08/766,914 US76691496A US5774706A US 5774706 A US5774706 A US 5774706A US 76691496 A US76691496 A US 76691496A US 5774706 A US5774706 A US 5774706A
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mhz
bus
processing system
data processing
pci
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Expired - Fee Related
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US08/766,914
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English (en)
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Danny M. Neal
Richard A. Kelley
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International Business Machines Corp
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International Business Machines Corp
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Priority to US08/766,914 priority Critical patent/US5774706A/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEAL, DANNY M., KELLEY, RICHARD A.
Priority to KR1019970047945A priority patent/KR100249337B1/ko
Priority to CN97122536A priority patent/CN1097780C/zh
Priority to JP9329943A priority patent/JPH10214142A/ja
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Definitions

  • the present invention relates in general to PCI local bus architectures and in particular to PCI local bus architectures which support high speed operations. Still more particularly, the present invention relates to a PCI local bus architecture which supports high speed operations utilizing the 5 V signalling environment and the 5 V PCI connector in a manner which is backward compatible with current architecture definitions.
  • PCI local bus a high performance 32-bit or 64-bit bus with multiplexed address and data lines.
  • the mechanical, electrical, and operational standards for the PCI local bus may be found in PCI Local Bus Specification, Revision 2.1 (hereinafter "the current PCI specification"), available from the PCI Special Interest Group in Portland, Oregon and incorporated herein by reference.
  • PCI local bus specification provides a processor-independent interface to add-in boards, also commonly referred to as expansion cards or adapters. Because of AC switching characteristic limitations, a PCI bus is typically configured to include six loads on the motherboard and two expansion slots or two loads on the motherboard and four expansion slots. Other configurations are possible, depending on the physical layout, loaded impedance of the motherboard, and other factors.
  • PCI add-in boards use an edge connector and are mounted in female connectors on the motherboard.
  • the female connectors or slots on the motherboard reflect the signaling environment of the PCI bus.
  • two types of PCI female connectors are defined: one for the 5 V signaling environment and one for the 3.3 V signaling environment.
  • Three varieties are specified for PCI add-in boards: a 5 V board which plugs into only the 5 V female connector, a universal board which plugs into both 5 V and 3.3 V female connectors, and a 3.3 V board which plugs into only the 3.3 V female connector.
  • a connector keying system prevents boards from being inserted into an inappropriate slot or female connector, as illustrated in FIG. 4.
  • Keyways 400-403 must be provided on the adapter board edge connectors at appropriate locations to accept keys 404, 405 in the female connectors or slots. Therefore the edge connector on a 5 V board 410 may only be inserted into a 5 V slot 420, and the edge connector on a 3.3 V board 430 may only be inserted into a 3.3 V slot 440.
  • the edge connector on a universal board 450 may be inserted into either 5 V slot 420 or 3.3 V slot 440.
  • the universal board is powered by a connection-dependent rail and includes components which operate in both the 5 V and 3.3 V signaling environments.
  • All three board types may be connected to both 5 V and 3.3 V power supplies.
  • the distinction between board type lies in the signaling protocol.
  • the 5 V board 410 is designed to operate only in the 5 V signaling environment, while the 3.3 V board operates only in the 3.3 V signaling environment.
  • the distinction between board types is commercially motivated, allowing vendors transition from the 5 V signaling environment to the 3.3 V signaling environment while sparing them the expense and burden of implementing 3.3 V components which are tolerant of 5 V signaling.
  • the PCI local bus specification provides an architecture definition for high speed operation (up to 66 MHz), which requires use of the 3.3 V female connector.
  • a 66 MHz adapter may utilize either the 3.3 V board or the universal board, but may not use the 5 V board since high speed operation is not defined for the 5 V signaling environment.
  • a ground pin or conductor on the bus (M66EN - side B, pin 49) is utilized to indicate support for 66 MHz capability.
  • Systems and adapters which support 66 MHz operation do not ground this ground pin. If all adapters installed on a PCI local bus do not ground the specified ground pin, the bus operates at the higher frequency--up to 66 MHz--supported by the system PCI clock.
  • the 5 V signaling environment is TTL compatible, while support for 3.3 V signalling is required for CMOS compliant devices.
  • CMOS compliant devices As data processing systems move from 5 V signaling to 3.3 V signaling for environmental or component density reasons, the majority of adapters will continue to utilize the 5 V type boards for some time. Therefore it would be desirable to support high speed PCI operations (33 MHz-50 MHz) utilizing the 5 V signaling environment and the 5 V PCI female connectors. It would also be desirable to provide such support in a backward compatible fashion with current 33 MHz and 66 MHz architecture definitions.
  • a PCI local bus in a data processing system is operated at 50 MHz using 5 V connectors for add-in boards and a 5 V signaling environment with an appropriate timing budget. Only the 5 V add-in boards may be used for 50 MHz adapters installed in the bus.
  • the bus is backward compatible with existing 33 MHz PCI specifications and operates at 33 MHz if a 33 MHz adapter is installed, and will operate at 50 MHz if only 50 MHz adapters and/or 66 MHz adapters which utilize the universal boards are installed.
  • FIG. 1 depicts a block diagram of a data processing system in which a preferred embodiment of the present invention may be implemented.
  • FIG. 2 is a block diagram of a PCI bridge and expansion slots in accordance with a preferred embodiment of the present invention.
  • FIG. 3 depicts a table of timing budgets for PCI bus operation at various bus speeds.
  • FIG. 4 is a pictorial representation of the connector keying system for PCI boards and slots.
  • Data processing system 100 utilizes the PCI local bus architecture.
  • Processor 102, cache 104, and system memory 106 are connected to the PCI local bus 108 through PCI bridge 110.
  • PCI bridge 110 may have an integrated memory controller. Additional connections to PCI local bus 108 may be through direct component interconnection or through add-in boards.
  • network adapter 112 SCSI adapter 114, and expansion bus interface 116 are connected to PCI local bus 108 by direct component connection, while sound card 118, motion video card 120 and graphics adapter 122 are connected to PCI local bus 108 by add-in boards inserted in expansion slots.
  • Typical PCI local bus implementations will support three or four PCI expansion slots or add-in connectors. The example depicted includes four loads on the motherboard and three expansion slots.
  • FIG. 1 may vary.
  • other peripheral devices such as optical disk drives and the like also may be utilized in addition to or in place of the hardware depicted.
  • the example depicted is not meant to imply architectural limitations.
  • PCI local bus 108 in the depicted example operates in the 5 V (TTL compatible) signaling environment.
  • System PCI bridge 200 provides an interface to PCI local bus 202 and 50 MHz PCI slots 204, 206 and 208.
  • PCI local bus 202 either 32 or 64 conductors, each conductor corresponding to a defined bit of PCI local bus signals.
  • PCI bridge 200 utilizes a 5 V signaling environment and PCI slots 204, 206 and 208 utilize 5 V PCI female connectors.
  • Adapters which are to be inserted into PCI slots 204, 206 and 208 are 50 MHz capable, or designed to operate only up to 50 MHz.
  • adapters or add-in boards installed in PCI slots 204, 206 and 208 may be long, short, or variable short length.
  • PCI clock 210 can be operated at either 33 MHz or 50 MHz.
  • PCI slots 204, 206 and 208 employ 5 V female connectors, only 5 V or universal expansion boards may be inserted into these slots.
  • a 66 MHz adapter which utilizes a universal board may be inserted into one of PCI slots 204, 206 and 208, in which case the PCI local bus 202 would operate at 50 MHz if only 50 MHz and/or 66 MHz adapters are installed.
  • a 66 MHz adapter that employs a universal board is presumably tolerant of the 5 V signaling environment.
  • timing budgets for PCI bus operation at various bus speeds is depicted.
  • the PCI local bus specification defines a specific timing budget that PCI systems and adapters must meet. This timing budget is defined in the equation
  • T CYC is the length of one clock cycle
  • T val is the valid output delay
  • T prop is the total bus propagation time
  • T skew is the total clock skew
  • T su is the input setup time.
  • Valid output delay T val and input setup times T su are specified by the components used on the adapter boards, while total clock skew T skew and bus propagation times T prop are system parameters.
  • Table 300 presents timing budgets for 33 MHz, 66 MHz, and 50 MHz operation. Two variations of the 50 MHz timing budget are presented.
  • the 50 MHz variation designated A is suggested, purely as an example, in Table 7-7 of the current PCI specification. However that variation is not computed for 5 V signaling, but rather presumes a 3.3 V signaling environment.
  • the timing budget variation designated B in FIG. 3 is preferable.
  • a preferred embodiment of the present invention should meet the timing budget values given in that variation: T val and T prop not in excess of 8 ns each; at least 3 ns allowed for T su ; and T skew not in excess of 1 ns.
  • T Val and T prop should not exceed 16 ns and the sum of T su and T prop should not exceed 11 ns.
  • satisfaction of the preferred 50 MHz timing budget should allow support for up to seven loads--including three expansion slots--attached to the PCI local bus. With very tight planar layout, eight loads (including four adapter slots) could be achieved.
  • PCI host bridge 200 should be designed to operate like a universal board, providing 3.3 V signaling as a master but tolerant of 5 V signaling as a target. Additionally, PCI host bridge 200 must also provide the 2 V up level required by 5 V targets. Components on both host bridge 200 and any 50 MHz-capable PCI adapters should satisfy the AC and DC drive for the 66 MHz specification.
  • the bus conductor attached to host bridge 200 corresponding to the M66EN pin should be pulled up with a 5 K ⁇ resistor to V cc , the input power supply voltage.
  • PCI clock generation circuitry 210 should be designed to generate the appropriate clock segment: 33 MHz if the 66 MHz ground pin (M66EN) is grounded and 50 MHz if the 66 MHz ground pin is not grounded. Therefore, PCI clock generation circuitry 210 should be connected to and capable of sensing the state of the 66 MHz ground pin.
  • the pinout for a 50 MHz adapter board should follow the 5 V pinout in the current PCI specification. Specifically, pins 12 and 13 on both sides of the board, where a keyway would be located on universal or 3.3 V boards, should be grounded. As with the 66 MHz specification, the M66EN pin--pin 49 on side B of the adapter board--may be capacitively decoupled to ground using a 0.01 ⁇ F capacitor to complete an AC return path.
  • PCI host bridge 200 and any 50 MHz-capable PCI adapter should identify that it may be operated at 50 MHz. This is done through read-only 66 MHz-capable flag, bit 5 of the PCI status register located on each 50 MHzcapable PCI device. Configuration software may then identify all device capabilities by checking the 66 MHz-capable flag in the status registers on all devices connected to PCI local bus 202, including both the primary and secondary status registers in PCI host bridge 200.
  • the PCI extension architecture illustrated in FIG. 2 defines a 5 V, 50 MHz PCI bus which is a compatible superset of the PCI specification designed to operate at a maximum of 50 MHz while utilizing 5 V connectors and 5 V signaling.
  • This extension provides a high speed PCI bus achieving more slots PCI bus than 66 MHz PCI while utilizing 5 V connectors and supporting both 50 MHz adapters (utilizing 5 V) and 66 MHz adapters (utilizing universal boards) with operations at 50 MHz.
  • the standard approach for generating a high speed PCI bus that operates at a frequency lower than 66 MHz would be to design the system and adapters to the 66 MHz architecture but run the bus at a frequency lower than 66 MHz to allow for additional adapters slots. That is, a lower frequency allows for additional propagation delays which will allow an additional slot or slots, depending on the frequency used. This approach is permitted in the current definition of the 66 MHz PCI architecture.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
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US08/766,914 1996-12-13 1996-12-13 High speed PCI bus utilizing TTL compatible signaling Expired - Fee Related US5774706A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US08/766,914 US5774706A (en) 1996-12-13 1996-12-13 High speed PCI bus utilizing TTL compatible signaling
KR1019970047945A KR100249337B1 (ko) 1996-12-13 1997-09-20 Ttl 호환 시그널링을 사용한 고속 pci
CN97122536A CN1097780C (zh) 1996-12-13 1997-11-12 采用ttl兼容信令的高速pci
JP9329943A JPH10214142A (ja) 1996-12-13 1997-12-01 Ｔｔｌ互換信号環境を利用した高速ｐｃｉ

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5938751A (en) * 1997-08-15 1999-08-17 Compaq Computer Corporation Bus ring-back and voltage over-shoot reduction techniques coupled with hot-pluggability
EP0962867A2 (en) * 1998-06-05 1999-12-08 International Business Machines Corporation Variable computer slot configuration for multi-speed bus
WO2000058815A1 (en) * 1999-03-30 2000-10-05 Qlogic Corporation Add-on card with automatic bus power line selection circuit
US6185642B1 (en) 1998-07-15 2001-02-06 International Business Machines Corporation Bus for high frequency operation with backward compatibility and hot-plug ability
US20020144037A1 (en) * 2001-03-29 2002-10-03 Bennett Joseph A. Data fetching mechanism and method for fetching data
US20040117512A1 (en) * 2002-12-03 2004-06-17 Alcatel Canada Inc. Logical bus overlay for increasing system bus data rate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101703697B1 (ko) 2015-03-10 2017-02-22 (주)아피스 낚시대 받침구

Citations (3)

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US5559968A (en) * 1995-03-03 1996-09-24 Compaq Computer Corporation Non-conforming PCI bus master timing compensation circuit
US5627482A (en) * 1996-02-07 1997-05-06 Ceridian Corporation Electronic digital clock distribution system
US5721935A (en) * 1995-12-20 1998-02-24 Compaq Computer Corporation Apparatus and method for entering low power mode in a computer system

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US5263172A (en) * 1990-04-16 1993-11-16 International Business Machines Corporation Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals
DE69317758T2 (de) * 1992-12-28 1998-10-29 Advanced Micro Devices Inc Mikroprozessorschaltung mit zwei Taktsignalen
US5678065A (en) * 1994-09-19 1997-10-14 Advanced Micro Devices, Inc. Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559968A (en) * 1995-03-03 1996-09-24 Compaq Computer Corporation Non-conforming PCI bus master timing compensation circuit
US5721935A (en) * 1995-12-20 1998-02-24 Compaq Computer Corporation Apparatus and method for entering low power mode in a computer system
US5627482A (en) * 1996-02-07 1997-05-06 Ceridian Corporation Electronic digital clock distribution system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PCI Local Bus Specification, Revision 2.1 (PCI Special Interest Group, Jun. 1, 1995). *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5938751A (en) * 1997-08-15 1999-08-17 Compaq Computer Corporation Bus ring-back and voltage over-shoot reduction techniques coupled with hot-pluggability
EP0962867A2 (en) * 1998-06-05 1999-12-08 International Business Machines Corporation Variable computer slot configuration for multi-speed bus
EP0962867A3 (en) * 1998-06-05 2003-11-26 International Business Machines Corporation Variable computer slot configuration for multi-speed bus
US6185642B1 (en) 1998-07-15 2001-02-06 International Business Machines Corporation Bus for high frequency operation with backward compatibility and hot-plug ability
WO2000058815A1 (en) * 1999-03-30 2000-10-05 Qlogic Corporation Add-on card with automatic bus power line selection circuit
US6327635B1 (en) 1999-03-30 2001-12-04 Qlogic Corporation Add-on card with automatic bus power line selection circuit
US20020144037A1 (en) * 2001-03-29 2002-10-03 Bennett Joseph A. Data fetching mechanism and method for fetching data
US20040117512A1 (en) * 2002-12-03 2004-06-17 Alcatel Canada Inc. Logical bus overlay for increasing system bus data rate
US7051229B2 (en) * 2002-12-03 2006-05-23 Alcatel Canada Inc. Logical bus overlay for increasing the existing system bus data rate

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Publication number Publication date
CN1097780C (zh) 2003-01-01
KR19980063473A (ko) 1998-10-07
JPH10214142A (ja) 1998-08-11
KR100249337B1 (ko) 2000-03-15
CN1184974A (zh) 1998-06-17

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